15a14cf166
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. LEDE/OPENWRT will auto strip executable program file while make. So we need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network fiemware be destroyed, then run make to build ls1012ardb firmware. The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message. This issue have noticed the IP owner for investigate, hope he can solve it earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4" bootargs. Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
29 lines
872 B
Diff
29 lines
872 B
Diff
From ff37b165bdb100450c7996c9fac0fad2e6ffe31d Mon Sep 17 00:00:00 2001
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From: Ying Zhang <ying.zhang22455@nxp.com>
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Date: Thu, 29 Sep 2016 11:40:37 +0800
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Subject: [PATCH 121/124] armv8: aarch32: defconfig: Enable support for AHCI
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SATA
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This patch is to enable support for the Freescale QorIQ AHCI SoC's
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onboard AHCI SATA.
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Signed-off-by: Alison Wang <alison.wang@nxp.com>
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---
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arch/arm/configs/ls_aarch32_defconfig | 5 +++++
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1 file changed, 5 insertions(+)
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--- a/arch/arm/configs/ls_aarch32_defconfig
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+++ b/arch/arm/configs/ls_aarch32_defconfig
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@@ -92,7 +92,12 @@ CONFIG_MTD_SPI_NOR=y
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CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
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CONFIG_SPI_FSL_QUADSPI=y
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CONFIG_BLK_DEV_SD=y
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+CONFIG_CHR_DEV_SG=y
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CONFIG_ATA=y
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+CONFIG_SATA_AHCI=y
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+CONFIG_SATA_AHCI_PLATFORM=y
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+CONFIG_AHCI_QORIQ=y
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+CONFIG_SATA_SIL24=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_RAM=y
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CONFIG_BLK_DEV_RAM_COUNT=8
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