258 lines
7.4 KiB
C
258 lines
7.4 KiB
C
#ifndef AMAZON_TPE_H
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#define AMAZON_TPE_H
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#include <linux/atm.h>
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#include <linux/atmdev.h>
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#include <linux/netdevice.h>
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#include <linux/ioctl.h>
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#ifdef CONFIG_IFX_ATM_MIB
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/* For ATM-MIB lists */
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#include <linux/list.h>
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#endif
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#include <asm/amazon/atm_mib.h>
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/* CBM Queue arranagement
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* Q0: free cells pool
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* Q1~ Q15: upstream queues
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* Q16: QAM downstream
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* Q17~Q31: downstream queues
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*/
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#define AMAZON_ATM_MAX_QUEUE_NUM 32
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#define AMAZON_ATM_PORT_NUM 2
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#define AMAZON_ATM_FREE_CELLS 4000
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#define AMAZON_ATM_MAX_VCC_NUM (AMAZON_ATM_MAX_QUEUE_NUM/2 - 1)
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#define AMAZON_AAL0_SDU (ATM_AAL0_SDU+4) //one more word for status
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#define CBM_RX_OFFSET 16 //offset from the same q for tx
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#define AMAZON_ATM_OAM_Q_ID 16
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#define AMAZON_ATM_RM_Q_ID 16
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#define AMAZON_ATM_OTHER_Q_ID 16
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#define CBM_DEFAULT_Q_OFFSET 1
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#define HTUTIMEOUT 0xffff//timeoutofhtutocbm
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#define QSB_WFQ_NONUBR_MAX 0x3f00
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#define QSB_WFQ_UBR_BYPASS 0x3fff
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#define QSB_TP_TS_MAX 65472
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#define QSB_TAUS_MAX 64512
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#define QSB_GCR_MIN 18
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#define HTU_RAM_ACCESS_MAX 1024//maxium time for HTU RAM access
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#define SWIE_LOCK 1
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#define PROC_ATM 1
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#define PROC_MIB 2
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#define PROC_VCC 3
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#define PROC_AAL5 4
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#define PROC_CBM 5
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#define PROC_HTU 6
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#define PROC_QSB 7
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#define PROC_SWIE 8
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/***************** internal data structure ********************/
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typedef int (*push_back_t)(struct atm_vcc *vcc,struct sk_buff *skb,int err) ;
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/* Device private data */
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typedef struct{
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u8 padding_byte;
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u32 tx_max_sdu;
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u32 rx_max_sdu;
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u32 cnt_cpy; //no. of packets that need a copy due to alignment
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}amazon_aal5_dev_t;
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typedef struct{
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u32 max_q_off; //maxium queues used in real scenario
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u32 nrt_thr;
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u32 clp0_thr;
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u32 clp1_thr;
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u32 free_cell_cnt;
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#ifdef CONFIG_USE_VENUS
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u8 * qd_addr_free; //to work around a bug, bit15 of QDOFF address should be 1
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#endif
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u8 * qd_addr;
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u8 * mem_addr;
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u8 allocated;
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}amazon_cbm_dev_t;
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typedef struct{
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}amazon_htu_dev_t;
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typedef struct{
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u32 tau; //cell delay variation due to concurrency(?)
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u32 tstepc; //time step, all legal values are 1,2,4
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u32 sbl; //scheduler burse length (for PHY)
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}amazon_qsb_dev_t;
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typedef struct{
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u32 qid; //QID of the current extraction queue
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struct semaphore in_sem; // Software-Insertion semaphore
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volatile long lock; //lock that avoids race contions between SWIN and SWEX
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wait_queue_head_t sleep; //wait queue for SWIE and SWEX
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u32 sw; //status word
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}amazon_swie_dev_t;
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//AAL5 MIB Counter
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typedef struct{
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u32 tx,rx; //number AAL5 CPCS PDU from/to higher-layer
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u32 tx_err,rx_err; //ifInErrors and ifOutErros
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u32 tx_drop,rx_drop; //discarded received packets due to mm shortage
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u32 htu_unp; //number of unknown received cells
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u32 rx_cnt_h; //number of octets received, high 32 bits
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u32 rx_cnt_l; //number of octets received, low 32 bits
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u32 tx_cnt_h; //number of octets transmitted, high 32 bits
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u32 tx_cnt_l; //number of octets transmitted, low 32 bits
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u32 tx_ppd; //number of cells for AAL5 upstream PPD discards
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u64 rx_cells; //number of cells for downstream
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u64 tx_cells; //number of cells for upstream
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u32 rx_err_cells; //number of cells dropped due to uncorrectable HEC errors
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}amazon_mib_counter_t;
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typedef enum {QS_PKT,QS_LEN,QS_ERR,QS_HW_DROP,QS_SW_DROP,QS_MAX} qs_t;
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//queue statics no. of packet received / sent
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//queue statics no. of bytes received / sent
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//queue statics no. of packets with error
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//queue statics no. of packets dropped by hw
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//queue statics no. of packets dropped by sw
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typedef struct{
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push_back_t push; //call back function
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struct atm_vcc * vcc; //opened vcc
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struct timeval access_time; //time when last F4/F5 user cells arrive
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int free; //whether this queue is occupied, 0: occupied, 1: free
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u32 aal5VccCrcErrors; //MIB counter
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u32 aal5VccOverSizedSDUs; //MIB counter
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#if defined(AMAZON_ATM_DEBUG) || defined (CONFIG_IFX_ATM_MIB)
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u32 qs[QS_MAX];
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#endif
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}amazon_atm_queue_t;
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typedef struct{
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int enable; //enable / disable
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u32 max_conn; //maximum number of connections per port
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u32 tx_max_cr; //Remaining cellrate for this device for tx direction
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u32 tx_rem_cr; //Remaining cellrate for this device for tx direction
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u32 tx_cur_cr; //Current cellrate for this device for tx direction
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}amazon_atm_port_t;
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typedef struct{
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amazon_aal5_dev_t aal5;
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amazon_cbm_dev_t cbm;
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amazon_htu_dev_t htu;
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amazon_qsb_dev_t qsb;
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amazon_swie_dev_t swie;
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amazon_mib_counter_t mib_counter;
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amazon_atm_queue_t queues[AMAZON_ATM_MAX_QUEUE_NUM];
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amazon_atm_port_t ports[AMAZON_ATM_PORT_NUM];
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atomic_t dma_tx_free_0;//TX_CH0 has availabe descriptors
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} amazon_atm_dev_t;
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struct oam_last_activity{
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u8 vpi; //vpi for this connection
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u16 vci; //vci for t his connection
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struct timeval stamp; //time when last F4/F5 user cells arrive
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struct oam_last_activity * next;//for link list purpose
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};
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typedef union{
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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struct{
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u32 tprs :16;
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u32 twfq :14;
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u32 vbr :1;
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u32 reserved :1;
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}bit;
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u32 w0;
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#else
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struct{
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u32 reserved :1;
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u32 vbr :1;
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u32 twfq :14;
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u32 tprs :16;
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}bit;
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u32 w0;
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#endif
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}qsb_qptl_t;
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typedef union{
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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struct{
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u32 ts :16;
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u32 taus :16;
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}bit;
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u32 w0;
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#else
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struct{
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u32 taus :16;
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u32 ts :16;
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}bit;
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u32 w0;
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#endif
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}qsb_qvpt_t;
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struct amazon_atm_cell_header {
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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struct{
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u32 clp :1; // Cell Loss Priority
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u32 pti :3; // Payload Type Identifier
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u32 vci :16; // Virtual Channel Identifier
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u32 vpi :8; // Vitual Path Identifier
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u32 gfc :4; // Generic Flow Control
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}bit;
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#else
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struct{
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u32 gfc :4; // Generic Flow Control
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u32 vpi :8; // Vitual Path Identifier
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u32 vci :16; // Virtual Channel Identifier
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u32 pti :3; // Payload Type Identifier
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u32 clp :1; // Cell Loss Priority
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}bit;
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#endif
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};
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/************************ Function Declarations **************************/
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amazon_atm_dev_t * amazon_atm_create(void);
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int amazon_atm_open(struct atm_vcc *vcc,push_back_t);
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int amazon_atm_send(struct atm_vcc *vcc,struct sk_buff *skb);
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int amazon_atm_send_oam(struct atm_vcc *vcc,void *cell, int flags);
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void amazon_atm_close(struct atm_vcc *vcc);
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void amazon_atm_cleanup(void);
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const struct oam_last_activity* get_oam_time_stamp(void);
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//mib-related
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int amazon_atm_cell_mib(atm_cell_ifEntry_t * to,u32 itf);
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int amazon_atm_aal5_mib(atm_aal5_ifEntry_t * to);
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int amazon_atm_vcc_mib(struct atm_vcc *vcc,atm_aal5_vcc_t * to);
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int amazon_atm_vcc_mib_x(int vpi, int vci,atm_aal5_vcc_t* to);
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#define AMAZON_WRITE_REGISTER_L(data,addr) do{ *((volatile u32*)(addr)) = (u32)(data); wmb();} while (0)
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#define AMAZON_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
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/******************************* ioctl stuff****************************************/
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#define NUM(dev) (MINOR(dev) & 0xf)
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/*
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* Ioctl definitions
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*/
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/* Use 'o' as magic number */
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#define AMAZON_ATM_IOC_MAGIC 'o'
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/* MIB_CELL: get atm cell level mib counter
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* MIB_AAL5: get aal5 mib counter
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* MIB_VCC: get vcc mib counter
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*/
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typedef struct{
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int vpi;
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int vci;
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atm_aal5_vcc_t mib_vcc;
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}atm_aal5_vcc_x_t;
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#define AMAZON_ATM_MIB_CELL _IOWR(AMAZON_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
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#define AMAZON_ATM_MIB_AAL5 _IOWR(AMAZON_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
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#define AMAZON_ATM_MIB_VCC _IOWR(AMAZON_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
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#define AMAZON_ATM_IOC_MAXNR 3
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//sockopt
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#define SO_AMAZON_ATM_MIB_VCC __SO_ENCODE(SOL_ATM,5,atm_aal5_vcc_t)
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#endif // AMAZON_TPE_H
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