27f23bac8f
Fix some section mismatches found with kernel 4.9. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
227 lines
6.4 KiB
C
227 lines
6.4 KiB
C
/*
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* TP-Link Archer C25 v1 board support
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*
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* Copyright (C) 2017 Ludwig Thomeczek <ledesrc@wxorx.net>
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* based on mach-archer-c60/C59-v1.c
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* Copyright (C) 2016 Henryk Heisig <hyniu@o2.pl>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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#include <linux/ar8216_platform.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <linux/gpio.h>
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#include "common.h"
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#include "dev-m25p80.h"
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#include "machtypes.h"
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#include "pci.h"
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#include "dev-ap9x-pci.h"
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#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-spi.h"
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#include "dev-usb.h"
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#include "dev-wmac.h"
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#include <linux/spi/spi_gpio.h>
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#include <linux/spi/74x164.h>
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#define ARCHER_C25_GPIO_SHIFT_OE 21 /* OE, Output Enable */
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#define ARCHER_C25_GPIO_SHIFT_SER 14 /* DS, Data Serial Input */
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#define ARCHER_C25_GPIO_SHIFT_SRCLK 15 /* SHCP, Shift Reg Clock Input */
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#define ARCHER_C25_GPIO_SHIFT_SRCLR 19 /* MR, Master Reset */
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#define ARCHER_C25_GPIO_SHIFT_RCLK 16 /* STCP, Storage Reg Clock Input */
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#define ARCHER_C25_74HC_GPIO_BASE QCA956X_GPIO_COUNT
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#define ARCHER_C25_74HC_GPIO_LED_WAN_AMBER 27
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#define ARCHER_C25_74HC_GPIO_LED_WAN_GREEN 28
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#define ARCHER_C25_74HC_GPIO_LED_WLAN2 29
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#define ARCHER_C25_74HC_GPIO_LED_WLAN5 30
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#define ARCHER_C25_74HC_GPIO_LED_LAN1 23
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#define ARCHER_C25_74HC_GPIO_LED_LAN2 24
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#define ARCHER_C25_74HC_GPIO_LED_LAN3 25
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#define ARCHER_C25_74HC_GPIO_LED_LAN4 26
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#define ARCHER_C25_V1_SSR_BIT_0 0
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#define ARCHER_C25_V1_SSR_BIT_1 1
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#define ARCHER_C25_V1_SSR_BIT_2 2
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#define ARCHER_C25_V1_SSR_BIT_3 3
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#define ARCHER_C25_V1_SSR_BIT_4 4
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#define ARCHER_C25_V1_SSR_BIT_5 5
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#define ARCHER_C25_V1_SSR_BIT_6 6
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#define ARCHER_C25_V1_SSR_BIT_7 7
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#define ARCHER_C25_V1_KEYS_POLL_INTERVAL 20
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#define ARCHER_C25_V1_KEYS_DEBOUNCE_INTERVAL \
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(3 * ARCHER_C25_V1_KEYS_POLL_INTERVAL)
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#define ARCHER_C25_V1_GPIO_BTN_RESET 1
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#define ARCHER_C25_V1_GPIO_BTN_RFKILL 22
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#define ARCHER_C25_V1_GPIO_LED_POWER 17
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#define ARCHER_C25_V1_GPIO_LED_WPS 2
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#define ARCHER_C25_V1_WMAC_CALDATA_OFFSET 0x1000
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static struct spi_gpio_platform_data archer_c25_v1_spi_data = {
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.sck = ARCHER_C25_GPIO_SHIFT_SRCLK,
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.miso = SPI_GPIO_NO_MISO,
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.mosi = ARCHER_C25_GPIO_SHIFT_SER,
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.num_chipselect = 1,
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};
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static u8 archer_c25_v1_ssr_initdata[] = {
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BIT(ARCHER_C25_V1_SSR_BIT_7) |
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BIT(ARCHER_C25_V1_SSR_BIT_6) |
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BIT(ARCHER_C25_V1_SSR_BIT_5) |
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BIT(ARCHER_C25_V1_SSR_BIT_4) |
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BIT(ARCHER_C25_V1_SSR_BIT_3) |
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BIT(ARCHER_C25_V1_SSR_BIT_2) |
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BIT(ARCHER_C25_V1_SSR_BIT_1)
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};
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static struct gen_74x164_chip_platform_data archer_c25_v1_ssr_data = {
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.base = ARCHER_C25_74HC_GPIO_BASE,
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.num_registers = ARRAY_SIZE(archer_c25_v1_ssr_initdata),
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.init_data = archer_c25_v1_ssr_initdata,
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};
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static struct platform_device archer_c25_v1_spi_device = {
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.name = "spi_gpio",
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.id = 1,
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.dev = {
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.platform_data = &archer_c25_v1_spi_data,
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},
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};
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static struct spi_board_info archer_c25_v1_spi_info[] = {
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{
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.bus_num = 1,
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.chip_select = 0,
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.max_speed_hz = 10000000,
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.modalias = "74x164",
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.platform_data = &archer_c25_v1_ssr_data,
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.controller_data = (void *) ARCHER_C25_GPIO_SHIFT_RCLK,
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},
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};
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static struct gpio_led archer_c25_v1_leds_gpio[] __initdata = {
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{
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.name = "archer-c25-v1:green:power",
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.gpio = ARCHER_C25_V1_GPIO_LED_POWER,
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.active_low = 1,
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}, {
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.name = "archer-c25-v1:green:wps",
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.gpio = ARCHER_C25_V1_GPIO_LED_WPS,
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.active_low = 1,
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}, {
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.name = "archer-c25-v1:green:wlan2g",
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.gpio = ARCHER_C25_74HC_GPIO_LED_WLAN2,
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.active_low = 1,
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}, {
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.name = "archer-c25-v1:green:wlan5g",
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.gpio = ARCHER_C25_74HC_GPIO_LED_WLAN5,
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.active_low = 1,
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}, {
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.name = "archer-c25-v1:green:lan1",
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.gpio = ARCHER_C25_74HC_GPIO_LED_LAN1,
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.active_low = 1,
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}, {
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.name = "archer-c25-v1:green:lan2",
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.gpio = ARCHER_C25_74HC_GPIO_LED_LAN2,
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.active_low = 1,
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}, {
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.name = "archer-c25-v1:green:lan3",
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.gpio = ARCHER_C25_74HC_GPIO_LED_LAN3,
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.active_low = 1,
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}, {
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.name = "archer-c25-v1:green:lan4",
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.gpio = ARCHER_C25_74HC_GPIO_LED_LAN4,
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.active_low = 1,
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}, {
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.name = "archer-c25-v1:green:wan",
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.gpio = ARCHER_C25_74HC_GPIO_LED_WAN_GREEN,
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.active_low = 1,
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}, {
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.name = "archer-c25-v1:amber:wan",
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.gpio = ARCHER_C25_74HC_GPIO_LED_WAN_AMBER,
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.active_low = 1,
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},
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};
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static struct gpio_keys_button archer_c25_v1_gpio_keys[] __initdata = {
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{
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.desc = "Reset button",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = ARCHER_C25_V1_KEYS_DEBOUNCE_INTERVAL,
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.gpio = ARCHER_C25_V1_GPIO_BTN_RESET,
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.active_low = 1,
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}, {
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.desc = "RFKILL button",
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.type = EV_KEY,
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.code = KEY_RFKILL,
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.debounce_interval = ARCHER_C25_V1_KEYS_DEBOUNCE_INTERVAL,
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.gpio = ARCHER_C25_V1_GPIO_BTN_RFKILL,
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.active_low = 1,
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},
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};
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static void __init archer_c25_v1_setup(void)
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{
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u8 *mac = (u8 *) KSEG1ADDR(0x1f7e0008);
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u8 *art = (u8 *) KSEG1ADDR(0x1f7f0000);
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ath79_register_m25p80(NULL);
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spi_register_board_info(archer_c25_v1_spi_info,
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ARRAY_SIZE(archer_c25_v1_spi_info));
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platform_device_register(&archer_c25_v1_spi_device);
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gpio_request_one(ARCHER_C25_GPIO_SHIFT_OE,
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GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
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"LED control");
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gpio_request_one(ARCHER_C25_GPIO_SHIFT_SRCLR,
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GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
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"LED reset");
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ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c25_v1_leds_gpio),
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archer_c25_v1_leds_gpio);
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ath79_register_gpio_keys_polled(-1, ARCHER_C25_V1_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(archer_c25_v1_gpio_keys),
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archer_c25_v1_gpio_keys);
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ath79_register_mdio(0, 0x0);
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ath79_register_mdio(1, 0x0);
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ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
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ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
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/* WAN port */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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ath79_eth0_data.speed = SPEED_100;
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ath79_eth0_data.duplex = DUPLEX_FULL;
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ath79_eth0_data.phy_mask = BIT(4);
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ath79_register_eth(0);
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/* LAN ports */
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
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ath79_eth1_data.speed = SPEED_1000;
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ath79_eth1_data.duplex = DUPLEX_FULL;
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ath79_switch_data.phy_poll_mask |= BIT(4);
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ath79_switch_data.phy4_mii_en = 1;
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ath79_register_eth(1);
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ath79_register_wmac(art + ARCHER_C25_V1_WMAC_CALDATA_OFFSET, mac);
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ap91_pci_init(NULL, NULL);
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}
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MIPS_MACHINE(ATH79_MACH_ARCHER_C25_V1, "ARCHER-C25-V1", "TP-LINK Archer C25 v1",
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archer_c25_v1_setup);
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