403 lines
10 KiB
Diff
403 lines
10 KiB
Diff
--- /dev/null
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+++ b/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt
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@@ -0,0 +1,22 @@
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+* Real Time Clock of the Armada 38x SoCs
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+
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+RTC controller for the Armada 38x SoCs
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+
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+Required properties:
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+- compatible : Should be "marvell,armada-380-rtc"
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+- reg: a list of base address and size pairs, one for each entry in
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+ reg-names
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+- reg names: should contain:
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+ * "rtc" for the RTC registers
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+ * "rtc-soc" for the SoC related registers and among them the one
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+ related to the interrupt.
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+- interrupts: IRQ line for the RTC.
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+
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+Example:
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+
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+rtc@a3800 {
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+ compatible = "marvell,armada-380-rtc";
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+ reg = <0xa3800 0x20>, <0x184a0 0x0c>;
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+ reg-names = "rtc", "rtc-soc";
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+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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+};
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--- a/drivers/rtc/Kconfig
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+++ b/drivers/rtc/Kconfig
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@@ -1262,6 +1262,16 @@ config RTC_DRV_MV
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This driver can also be built as a module. If so, the module
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will be called rtc-mv.
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+config RTC_DRV_ARMADA38X
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+ tristate "Armada 38x Marvell SoC RTC"
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+ depends on ARCH_MVEBU
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+ help
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+ If you say yes here you will get support for the in-chip RTC
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+ that can be found in the Armada 38x Marvell's SoC device
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+
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+ This driver can also be built as a module. If so, the module
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+ will be called armada38x-rtc.
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+
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config RTC_DRV_PS3
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tristate "PS3 RTC"
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depends on PPC_PS3
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--- a/drivers/rtc/Makefile
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+++ b/drivers/rtc/Makefile
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@@ -24,6 +24,7 @@ obj-$(CONFIG_RTC_DRV_88PM860X) += rtc-8
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obj-$(CONFIG_RTC_DRV_88PM80X) += rtc-88pm80x.o
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obj-$(CONFIG_RTC_DRV_AB3100) += rtc-ab3100.o
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obj-$(CONFIG_RTC_DRV_AB8500) += rtc-ab8500.o
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+obj-$(CONFIG_RTC_DRV_ARMADA38X) += rtc-armada38x.o
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obj-$(CONFIG_RTC_DRV_AS3722) += rtc-as3722.o
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obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o
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obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o
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--- /dev/null
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+++ b/drivers/rtc/rtc-armada38x.c
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@@ -0,0 +1,320 @@
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+/*
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+ * RTC driver for the Armada 38x Marvell SoCs
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+ *
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+ * Copyright (C) 2015 Marvell
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+ *
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+ * Gregory Clement <gregory.clement@free-electrons.com>
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of the
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+ * License, or (at your option) any later version.
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+ *
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+ */
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+
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+#include <linux/delay.h>
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+#include <linux/io.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/platform_device.h>
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+#include <linux/rtc.h>
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+
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+#define RTC_STATUS 0x0
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+#define RTC_STATUS_ALARM1 BIT(0)
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+#define RTC_STATUS_ALARM2 BIT(1)
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+#define RTC_IRQ1_CONF 0x4
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+#define RTC_IRQ1_AL_EN BIT(0)
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+#define RTC_IRQ1_FREQ_EN BIT(1)
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+#define RTC_IRQ1_FREQ_1HZ BIT(2)
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+#define RTC_TIME 0xC
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+#define RTC_ALARM1 0x10
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+
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+#define SOC_RTC_INTERRUPT 0x8
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+#define SOC_RTC_ALARM1 BIT(0)
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+#define SOC_RTC_ALARM2 BIT(1)
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+#define SOC_RTC_ALARM1_MASK BIT(2)
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+#define SOC_RTC_ALARM2_MASK BIT(3)
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+
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+struct armada38x_rtc {
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+ struct rtc_device *rtc_dev;
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+ void __iomem *regs;
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+ void __iomem *regs_soc;
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+ spinlock_t lock;
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+ int irq;
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+};
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+
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+/*
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+ * According to the datasheet, the OS should wait 5us after every
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+ * register write to the RTC hard macro so that the required update
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+ * can occur without holding off the system bus
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+ */
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+static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset)
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+{
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+ writel(val, rtc->regs + offset);
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+ udelay(5);
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+}
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+
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+static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm)
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+{
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+ struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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+ unsigned long time, time_check, flags;
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+
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+ spin_lock_irqsave(&rtc->lock, flags);
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+
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+ time = readl(rtc->regs + RTC_TIME);
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+ /*
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+ * WA for failing time set attempts. As stated in HW ERRATA if
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+ * more than one second between two time reads is detected
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+ * then read once again.
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+ */
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+ time_check = readl(rtc->regs + RTC_TIME);
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+ if ((time_check - time) > 1)
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+ time_check = readl(rtc->regs + RTC_TIME);
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+
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+ spin_unlock_irqrestore(&rtc->lock, flags);
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+
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+ rtc_time_to_tm(time_check, tm);
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+
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+ return 0;
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+}
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+
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+static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm)
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+{
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+ struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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+ int ret = 0;
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+ unsigned long time, flags;
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+
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+ ret = rtc_tm_to_time(tm, &time);
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+
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+ if (ret)
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+ goto out;
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+ /*
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+ * Setting the RTC time not always succeeds. According to the
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+ * errata we need to first write on the status register and
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+ * then wait for 100ms before writing to the time register to be
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+ * sure that the data will be taken into account.
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+ */
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+ spin_lock_irqsave(&rtc->lock, flags);
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+
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+ rtc_delayed_write(0, rtc, RTC_STATUS);
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+
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+ spin_unlock_irqrestore(&rtc->lock, flags);
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+
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+ msleep(100);
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+
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+ spin_lock_irqsave(&rtc->lock, flags);
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+
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+ rtc_delayed_write(time, rtc, RTC_TIME);
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+
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+ spin_unlock_irqrestore(&rtc->lock, flags);
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+out:
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+ return ret;
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+}
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+
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+static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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+{
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+ struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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+ unsigned long time, flags;
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+ u32 val;
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+
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+ spin_lock_irqsave(&rtc->lock, flags);
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+
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+ time = readl(rtc->regs + RTC_ALARM1);
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+ val = readl(rtc->regs + RTC_IRQ1_CONF) & RTC_IRQ1_AL_EN;
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+
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+ spin_unlock_irqrestore(&rtc->lock, flags);
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+
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+ alrm->enabled = val ? 1 : 0;
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+ rtc_time_to_tm(time, &alrm->time);
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+
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+ return 0;
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+}
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+
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+static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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+{
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+ struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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+ unsigned long time, flags;
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+ int ret = 0;
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+ u32 val;
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+
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+ ret = rtc_tm_to_time(&alrm->time, &time);
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+
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+ if (ret)
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+ goto out;
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+
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+ spin_lock_irqsave(&rtc->lock, flags);
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+
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+ rtc_delayed_write(time, rtc, RTC_ALARM1);
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+
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+ if (alrm->enabled) {
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+ rtc_delayed_write(RTC_IRQ1_AL_EN, rtc, RTC_IRQ1_CONF);
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+ val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
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+ writel(val | SOC_RTC_ALARM1_MASK,
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+ rtc->regs_soc + SOC_RTC_INTERRUPT);
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+ }
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+
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+ spin_unlock_irqrestore(&rtc->lock, flags);
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+
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+out:
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+ return ret;
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+}
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+
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+static int armada38x_rtc_alarm_irq_enable(struct device *dev,
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+ unsigned int enabled)
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+{
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+ struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&rtc->lock, flags);
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+
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+ if (enabled)
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+ rtc_delayed_write(RTC_IRQ1_AL_EN, rtc, RTC_IRQ1_CONF);
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+ else
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+ rtc_delayed_write(0, rtc, RTC_IRQ1_CONF);
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+
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+ spin_unlock_irqrestore(&rtc->lock, flags);
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+
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+ return 0;
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+}
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+
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+static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data)
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+{
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+ struct armada38x_rtc *rtc = data;
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+ u32 val;
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+ int event = RTC_IRQF | RTC_AF;
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+
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+ dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq);
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+
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+ spin_lock(&rtc->lock);
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+
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+ val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
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+
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+ writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
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+ val = readl(rtc->regs + RTC_IRQ1_CONF);
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+ /* disable all the interrupts for alarm 1 */
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+ rtc_delayed_write(0, rtc, RTC_IRQ1_CONF);
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+ /* Ack the event */
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+ rtc_delayed_write(RTC_STATUS_ALARM1, rtc, RTC_STATUS);
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+
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+ spin_unlock(&rtc->lock);
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+
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+ if (val & RTC_IRQ1_FREQ_EN) {
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+ if (val & RTC_IRQ1_FREQ_1HZ)
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+ event |= RTC_UF;
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+ else
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+ event |= RTC_PF;
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+ }
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+
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+ rtc_update_irq(rtc->rtc_dev, 1, event);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static struct rtc_class_ops armada38x_rtc_ops = {
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+ .read_time = armada38x_rtc_read_time,
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+ .set_time = armada38x_rtc_set_time,
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+ .read_alarm = armada38x_rtc_read_alarm,
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+ .set_alarm = armada38x_rtc_set_alarm,
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+ .alarm_irq_enable = armada38x_rtc_alarm_irq_enable,
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+};
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+
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+static __init int armada38x_rtc_probe(struct platform_device *pdev)
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+{
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+ struct resource *res;
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+ struct armada38x_rtc *rtc;
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+ int ret;
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+
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+ rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc),
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+ GFP_KERNEL);
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+ if (!rtc)
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+ return -ENOMEM;
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+
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+ spin_lock_init(&rtc->lock);
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+
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+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc");
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+ rtc->regs = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(rtc->regs))
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+ return PTR_ERR(rtc->regs);
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+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc");
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+ rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(rtc->regs_soc))
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+ return PTR_ERR(rtc->regs_soc);
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+
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+ rtc->irq = platform_get_irq(pdev, 0);
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+
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+ if (rtc->irq < 0) {
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+ dev_err(&pdev->dev, "no irq\n");
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+ return rtc->irq;
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+ }
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+ if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq,
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+ 0, pdev->name, rtc) < 0) {
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+ dev_warn(&pdev->dev, "Interrupt not available.\n");
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+ rtc->irq = -1;
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+ /*
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+ * If there is no interrupt available then we can't
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+ * use the alarm
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+ */
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+ armada38x_rtc_ops.set_alarm = NULL;
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+ armada38x_rtc_ops.alarm_irq_enable = NULL;
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+ }
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+ platform_set_drvdata(pdev, rtc);
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+ if (rtc->irq != -1)
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+ device_init_wakeup(&pdev->dev, 1);
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+
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+ rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
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+ &armada38x_rtc_ops, THIS_MODULE);
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+ if (IS_ERR(rtc->rtc_dev)) {
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+ ret = PTR_ERR(rtc->rtc_dev);
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+ dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
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+ return ret;
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+ }
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+ return 0;
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+}
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+
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+#ifdef CONFIG_PM_SLEEP
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+static int armada38x_rtc_suspend(struct device *dev)
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+{
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+ if (device_may_wakeup(dev)) {
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+ struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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+
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+ return enable_irq_wake(rtc->irq);
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+ }
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+
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+ return 0;
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+}
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+
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+static int armada38x_rtc_resume(struct device *dev)
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+{
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+ if (device_may_wakeup(dev)) {
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+ struct armada38x_rtc *rtc = dev_get_drvdata(dev);
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+
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+ return disable_irq_wake(rtc->irq);
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+ }
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+
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+ return 0;
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+}
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+#endif
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+
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+static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops,
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+ armada38x_rtc_suspend, armada38x_rtc_resume);
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+
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+#ifdef CONFIG_OF
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+static const struct of_device_id armada38x_rtc_of_match_table[] = {
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+ { .compatible = "marvell,armada-380-rtc", },
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+ {}
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+};
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+#endif
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+
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+static struct platform_driver armada38x_rtc_driver = {
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+ .driver = {
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+ .name = "armada38x-rtc",
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+ .pm = &armada38x_rtc_pm_ops,
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+ .of_match_table = of_match_ptr(armada38x_rtc_of_match_table),
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+ },
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+};
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+
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+module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe);
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+
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+MODULE_DESCRIPTION("Marvell Armada 38x RTC driver");
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+MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
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+MODULE_LICENSE("GPL");
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--- a/MAINTAINERS
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+++ b/MAINTAINERS
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@@ -1136,6 +1136,7 @@ M: Sebastian Hesselbarth <sebastian.hess
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: arch/arm/mach-mvebu/
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+F: drivers/rtc/armada38x-rtc
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ARM/Marvell Berlin SoC support
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M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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--- a/arch/arm/boot/dts/armada-38x.dtsi
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+++ b/arch/arm/boot/dts/armada-38x.dtsi
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@@ -420,6 +420,13 @@
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clocks = <&gateclk 4>;
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};
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+ rtc@a3800 {
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+ compatible = "marvell,armada-380-rtc";
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+ reg = <0xa3800 0x20>, <0x184a0 0x0c>;
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+ reg-names = "rtc", "rtc-soc";
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+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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sata@a8000 {
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compatible = "marvell,armada-380-ahci";
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reg = <0xa8000 0x2000>;
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