39 lines
1.5 KiB
Diff
39 lines
1.5 KiB
Diff
From 6d3a47c29186aa8d26ff05a6209c94291ace0696 Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Sat, 5 Dec 2015 21:16:42 +0800
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Subject: [PATCH] clk: sunxi: Add DRAM gates support for sun4i-a10
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The A10/A20 share the same set of DRAM clock gates, which controls
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direct memory access for some peripherals.
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On the A10, bit 15 controls the system's DRAM clock output (possibly
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to the DRAM chips), which we need to keep on.
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On the A20 this has been moved to the DRAM controller, becoming a no-op.
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However it is still listed in the user manual, so add it anyway.
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
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drivers/clk/sunxi/clk-simple-gates.c | 12 ++++++++++++
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2 files changed, 13 insertions(+)
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--- a/drivers/clk/sunxi/clk-simple-gates.c
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+++ b/drivers/clk/sunxi/clk-simple-gates.c
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@@ -158,3 +158,15 @@ CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner
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sun4i_a10_ahb_init);
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CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
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sun4i_a10_ahb_init);
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+
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+static const int sun4i_a10_dram_critical_clocks[] __initconst = {
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+ 15, /* dram_output */
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+};
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+
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+static void __init sun4i_a10_dram_init(struct device_node *node)
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+{
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+ sunxi_simple_gates_setup(node, sun4i_a10_dram_critical_clocks,
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+ ARRAY_SIZE(sun4i_a10_dram_critical_clocks));
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+}
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+CLK_OF_DECLARE(sun4i_a10_dram, "allwinner,sun4i-a10-dram-gates-clk",
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+ sun4i_a10_dram_init);
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