f5f173e2b7
* fixes NAND * adds latest ethernet patches Signed-off-by: John Crispin <john@phrozen.org>
46 lines
1.9 KiB
Diff
46 lines
1.9 KiB
Diff
From 297ef52cd21e28da671996d7b4f39f268d2d0ec1 Mon Sep 17 00:00:00 2001
|
|
From: John Crispin <blogic@openwrt.org>
|
|
Date: Tue, 29 Mar 2016 14:32:07 +0200
|
|
Subject: [PATCH 070/102] net: mediatek: update the IRQ part of the binding
|
|
document
|
|
|
|
The current binding document only describes a single interrupt. Update the
|
|
document by adding the 2 other interrupts.
|
|
|
|
The driver currently only uses a single interrupt. The HW is however able
|
|
to using IRQ grouping to split TX and RX onto separate GIC irqs.
|
|
|
|
Signed-off-by: John Crispin <blogic@openwrt.org>
|
|
Acked-by: Rob Herring <robh@kernel.org>
|
|
---
|
|
Documentation/devicetree/bindings/net/mediatek-net.txt | 7 +++++--
|
|
1 file changed, 5 insertions(+), 2 deletions(-)
|
|
|
|
diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
|
|
index 5ca7929..32eaaca 100644
|
|
--- a/Documentation/devicetree/bindings/net/mediatek-net.txt
|
|
+++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
|
|
@@ -9,7 +9,8 @@ have dual GMAC each represented by a child node..
|
|
Required properties:
|
|
- compatible: Should be "mediatek,mt7623-eth"
|
|
- reg: Address and length of the register set for the device
|
|
-- interrupts: Should contain the frame engines interrupt
|
|
+- interrupts: Should contain the three frame engines interrupts in numeric
|
|
+ order. These are fe_int0, fe_int1 and fe_int2.
|
|
- clocks: the clock used by the core
|
|
- clock-names: the names of the clock listed in the clocks property. These are
|
|
"ethif", "esw", "gp2", "gp1"
|
|
@@ -42,7 +43,9 @@ eth: ethernet@1b100000 {
|
|
<ðsys CLK_ETHSYS_GP2>,
|
|
<ðsys CLK_ETHSYS_GP1>;
|
|
clock-names = "ethif", "esw", "gp2", "gp1";
|
|
- interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
|
|
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
|
|
+ GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
|
|
+ GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
|
resets = <ðsys MT2701_ETHSYS_ETH_RST>;
|
|
reset-names = "eth";
|
|
--
|
|
1.7.10.4
|
|
|