535 lines
19 KiB
C
535 lines
19 KiB
C
/*****************************************************************************
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** FILE NAME : ifxusb_cif_d.c
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** PROJECT : IFX USB sub-system V3
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** MODULES : IFX USB sub-system Host and Device driver
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** SRC VERSION : 3.2
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** DATE : 1/Jan/2011
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** AUTHOR : Chen, Howard
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** DESCRIPTION : The Core Interface provides basic services for accessing and
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** managing the IFX USB hardware. These services are used by the
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** Peripheral Controller Driver only.
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** FUNCTIONS :
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** COMPILER : gcc
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** REFERENCE : Synopsys DWC-OTG Driver 2.7
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** COPYRIGHT : Copyright (c) 2010
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** LANTIQ DEUTSCHLAND GMBH,
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** Am Campeon 3, 85579 Neubiberg, Germany
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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**
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** Version Control Section **
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** $Author$
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** $Date$
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** $Revisions$
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** $Log$ Revision history
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*****************************************************************************/
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/*
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* This file contains code fragments from Synopsys HS OTG Linux Software Driver.
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* For this code the following notice is applicable:
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*
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* ==========================================================================
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*
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* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
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* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
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* otherwise expressly agreed to in writing between Synopsys and you.
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*
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* The Software IS NOT an item of Licensed Software or Licensed Product under
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* any End User Software License Agreement or Agreement for Licensed Product
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* with Synopsys or any supplement thereto. You are permitted to use and
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* redistribute this Software in source and binary forms, with or without
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* modification, provided that redistributions of source code must retain this
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* notice. You may not view, use, disclose, copy or distribute this file or
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* any information contained herein except pursuant to this license grant from
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* Synopsys. If you do not agree with this notice, including the disclaimer
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* below, then you are not authorized to use the Software.
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*
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGE.
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* ========================================================================== */
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/*!
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\file ifxusb_cif_d.c
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\ingroup IFXUSB_DRIVER_V3
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\brief This file contains the interface to the IFX USB Core.
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*/
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#include <linux/version.h>
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#include "ifxusb_version.h"
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#include <asm/byteorder.h>
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#include <asm/unaligned.h>
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#ifdef __DEBUG__
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#include <linux/jiffies.h>
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#endif
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#include "ifxusb_plat.h"
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#include "ifxusb_regs.h"
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#include "ifxusb_cif.h"
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#include "ifxpcd.h"
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/*!
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\brief Initializes the DevSpd field of the DCFG register depending on the PHY type
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and the enumeration speed of the device.
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\param _core_if Pointer of core_if structure
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*/
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void ifxusb_dev_init_spd(ifxusb_core_if_t *_core_if)
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{
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uint32_t val;
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dcfg_data_t dcfg;
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IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
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if (_core_if->params.speed == IFXUSB_PARAM_SPEED_FULL)
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/* High speed PHY running at full speed */
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val = 0x1;
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else
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/* High speed PHY running at high speed and full speed*/
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val = 0x0;
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IFX_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
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dcfg.d32 = ifxusb_rreg(&_core_if->dev_global_regs->dcfg);
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dcfg.b.devspd = val;
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ifxusb_wreg(&_core_if->dev_global_regs->dcfg, dcfg.d32);
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}
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/*!
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\brief This function enables the Device mode interrupts.
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\param _core_if Pointer of core_if structure
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*/
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void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if)
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{
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gint_data_t intr_mask ={ .d32 = 0};
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ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
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IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
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IFX_DEBUGPL(DBG_CIL, "%s()\n", __func__);
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/* Clear any pending OTG Interrupts */
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ifxusb_wreg( &global_regs->gotgint, 0xFFFFFFFF);
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/* Clear any pending interrupts */
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ifxusb_wreg( &global_regs->gintsts, 0xFFFFFFFF);
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/* Enable the interrupts in the GINTMSK.*/
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intr_mask.b.modemismatch = 1;
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intr_mask.b.conidstschng = 1;
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intr_mask.b.wkupintr = 1;
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intr_mask.b.disconnect = 1;
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intr_mask.b.usbsuspend = 1;
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intr_mask.b.usbreset = 1;
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intr_mask.b.enumdone = 1;
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intr_mask.b.inepintr = 1;
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intr_mask.b.outepintr = 1;
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intr_mask.b.erlysuspend = 1;
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#ifndef __DED_FIFO__
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#ifndef __DED_INTR__
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intr_mask.b.epmismatch = 1;
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#endif
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#endif
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ifxusb_mreg( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
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IFX_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, ifxusb_rreg( &global_regs->gintmsk));
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}
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/*!
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\brief Gets the current USB frame number. This is the frame number from the last SOF packet.
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\param _core_if Pointer of core_if structure
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*/
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uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if)
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{
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dsts_data_t dsts;
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IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
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dsts.d32 = ifxusb_rreg(&_core_if->dev_global_regs->dsts);
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/* read current frame/microfreme number from DSTS register */
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return dsts.b.soffn;
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}
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/*!
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\brief Set the EP STALL.
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*/
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void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in)
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{
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depctl_data_t depctl;
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volatile uint32_t *depctl_addr;
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IFX_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _epno, (_is_in?"IN":"OUT"));
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depctl_addr = (_is_in)? (&(_core_if->in_ep_regs [_epno]->diepctl)):
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(&(_core_if->out_ep_regs[_epno]->doepctl));
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depctl.d32 = ifxusb_rreg(depctl_addr);
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depctl.b.stall = 1;
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if (_is_in && depctl.b.epena)
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depctl.b.epdis = 1;
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ifxusb_wreg(depctl_addr, depctl.d32);
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IFX_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",ifxusb_rreg(depctl_addr));
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return;
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}
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/*!
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\brief Clear the EP STALL.
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*/
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void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in)
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{
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depctl_data_t depctl;
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volatile uint32_t *depctl_addr;
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IFX_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _epno, (_is_in?"IN":"OUT"));
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depctl_addr = (_is_in)? (&(_core_if->in_ep_regs [_epno]->diepctl)):
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(&(_core_if->out_ep_regs[_epno]->doepctl));
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depctl.d32 = ifxusb_rreg(depctl_addr);
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/* clear the stall bits */
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depctl.b.stall = 0;
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/*
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* USB Spec 9.4.5: For endpoints using data toggle, regardless
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* of whether an endpoint has the Halt feature set, a
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* ClearFeature(ENDPOINT_HALT) request always results in the
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* data toggle being reinitialized to DATA0.
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*/
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if (_ep_type == IFXUSB_EP_TYPE_INTR || _ep_type == IFXUSB_EP_TYPE_BULK)
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depctl.b.setd0pid = 1; /* DATA0 */
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ifxusb_wreg(depctl_addr, depctl.d32);
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IFX_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",ifxusb_rreg(depctl_addr));
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return;
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}
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/*!
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\brief This function initializes the IFXUSB controller registers for Device mode.
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This function flushes the Tx and Rx FIFOs and it flushes any entries in the
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request queues.
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\param _core_if Pointer of core_if structure
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\param _params parameters to be set
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*/
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void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params)
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{
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ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
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gusbcfg_data_t usbcfg ={.d32 = 0};
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gahbcfg_data_t ahbcfg ={.d32 = 0};
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dcfg_data_t dcfg ={.d32 = 0};
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grstctl_t resetctl ={.d32 = 0};
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gotgctl_data_t gotgctl ={.d32 = 0};
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uint32_t dir;
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int i;
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IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
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IFX_DEBUGPL(DBG_CILV, "%s(%p)\n",__func__,_core_if);
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/* Copy Params */
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_core_if->params.dma_burst_size = _params->dma_burst_size;
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_core_if->params.speed = _params->speed;
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if(_params->max_transfer_size < 2048 || _params->max_transfer_size > ((1 << (_core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1) )
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_core_if->params.max_transfer_size = ((1 << (_core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1);
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else
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_core_if->params.max_transfer_size = _params->max_transfer_size;
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if(_params->max_packet_count < 16 || _params->max_packet_count > ((1 << (_core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1) )
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_core_if->params.max_packet_count= ((1 << (_core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
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else
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_core_if->params.max_packet_count= _params->max_packet_count;
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_core_if->params.phy_utmi_width = _params->phy_utmi_width;
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_core_if->params.turn_around_time_hs = _params->turn_around_time_hs;
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_core_if->params.turn_around_time_fs = _params->turn_around_time_fs;
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_core_if->params.timeout_cal_hs = _params->timeout_cal_hs;
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_core_if->params.timeout_cal_fs = _params->timeout_cal_fs;
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#ifdef __DED_FIFO__
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_core_if->params.thr_ctl = _params->thr_ctl;
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_core_if->params.tx_thr_length = _params->tx_thr_length;
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_core_if->params.rx_thr_length = _params->rx_thr_length;
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#endif
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/* Reset the Controller */
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do
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{
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while(ifxusb_core_soft_reset_d( _core_if ))
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ifxusb_hard_reset_d(_core_if);
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} while (ifxusb_is_host_mode(_core_if));
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usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg);
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usbcfg.b.ForceDevMode = 1;
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usbcfg.b.ForceHstMode = 0;
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usbcfg.b.term_sel_dl_pulse = 0;
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ifxusb_wreg (&global_regs->gusbcfg, usbcfg.d32);
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/* This programming sequence needs to happen in FS mode before any other
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* programming occurs */
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/* High speed PHY. */
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if (!_core_if->phy_init_done)
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{
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_core_if->phy_init_done = 1;
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/* HS PHY parameters. These parameters are preserved
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* during soft reset so only program the first time. Do
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* a soft reset immediately after setting phyif. */
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usbcfg.b.ulpi_utmi_sel = 0; //UTMI+
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usbcfg.b.phyif = ( _core_if->params.phy_utmi_width == 16)?1:0;
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ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32);
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/* Reset after setting the PHY parameters */
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ifxusb_core_soft_reset_d( _core_if );
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}
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/* Program the GAHBCFG Register.*/
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switch (_core_if->params.dma_burst_size)
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{
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case 0 :
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ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE;
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break;
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case 1 :
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ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR;
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break;
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case 4 :
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ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4;
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break;
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case 8 :
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ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8;
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break;
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case 16:
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ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16;
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break;
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}
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#if defined(__UNALIGNED_BUF_ADJ__) || defined(__UNALIGNED_BUF_CHK__)
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_core_if->unaligned_mask=3;
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#if defined(__UNALIGNED_BUF_BURST__)
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switch (_core_if->params.dma_burst_size)
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{
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case 4 :
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_core_if->unaligned_mask=15;
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break;
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case 8 :
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_core_if->unaligned_mask=31;
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break;
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case 16:
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_core_if->unaligned_mask=63;
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break;
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case 0 :
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case 1 :
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break;
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}
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#endif //defined(__UNALIGNED_BUF_BURST__)
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#endif //defined(__UNALIGNED_BUF_ADJ__) || defined(__UNALIGNED_BUF_CHK__)
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ahbcfg.b.dmaenable = 1;
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ifxusb_wreg(&global_regs->gahbcfg, ahbcfg.d32);
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/* Program the GUSBCFG register. */
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usbcfg.d32 = ifxusb_rreg( &global_regs->gusbcfg );
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usbcfg.b.hnpcap = 0;
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usbcfg.b.srpcap = 0;
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ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32);
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{
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dctl_data_t dctl = {.d32=0};
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dctl.d32=ifxusb_rreg(&_core_if->dev_global_regs->dctl);
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dctl.b.sftdiscon=1;
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ifxusb_wreg(&_core_if->dev_global_regs->dctl,dctl.d32);
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}
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/* Restart the Phy Clock */
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ifxusb_wreg(_core_if->pcgcctl, 0);
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/* Device configuration register */
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ifxusb_dev_init_spd(_core_if);
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dcfg.d32 = ifxusb_rreg( &_core_if->dev_global_regs->dcfg);
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dcfg.b.perfrint = IFXUSB_DCFG_FRAME_INTERVAL_80;
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#if defined(__DED_FIFO__)
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#if defined(__DESC_DMA__)
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dcfg.b.descdma = 1;
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#else
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dcfg.b.descdma = 0;
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#endif
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#endif
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ifxusb_wreg( &_core_if->dev_global_regs->dcfg, dcfg.d32 );
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/* Configure data FIFO sizes */
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_core_if->params.data_fifo_size = _core_if->hwcfg3.b.dfifo_depth;
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_core_if->params.rx_fifo_size = ifxusb_rreg(&global_regs->grxfsiz);
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IFX_DEBUGPL(DBG_CIL, "Initial: FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size);
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IFX_DEBUGPL(DBG_CIL, " Rx FIFO Size=0x%06X\n", _core_if->params.rx_fifo_size);
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_core_if->params.tx_fifo_size[0]= ifxusb_rreg(&global_regs->gnptxfsiz) >> 16;
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#ifdef __DED_FIFO__
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for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++)
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_core_if->params.tx_fifo_size[i] =
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ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i-1]) >> 16;
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#else
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for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
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_core_if->params.tx_fifo_size[i+1] =
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ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
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#endif
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#ifdef __DEBUG__
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#ifdef __DED_FIFO__
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for (i=0; i <= _core_if->hwcfg4.b.num_in_eps; i++)
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IFX_DEBUGPL(DBG_CIL, " Tx[%02d] FIFO Size=0x%06X\n",i, _core_if->params.tx_fifo_size[i]);
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#else
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IFX_DEBUGPL(DBG_CIL, " NPTx FIFO Size=0x%06X\n", _core_if->params.tx_fifo_size[0]);
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for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
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IFX_DEBUGPL(DBG_CIL, " PTx[%02d] FIFO Size=0x%06X\n",i, _core_if->params.tx_fifo_size[i+1]);
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#endif
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#endif
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{
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fifosize_data_t txfifosize;
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if(_params->data_fifo_size >=0 && _params->data_fifo_size < _core_if->params.data_fifo_size)
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_core_if->params.data_fifo_size = _params->data_fifo_size;
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if(_params->rx_fifo_size >=0 && _params->rx_fifo_size < _core_if->params.rx_fifo_size)
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_core_if->params.rx_fifo_size = _params->rx_fifo_size;
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if(_core_if->params.data_fifo_size < _core_if->params.rx_fifo_size)
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_core_if->params.rx_fifo_size = _core_if->params.data_fifo_size;
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ifxusb_wreg( &global_regs->grxfsiz, _core_if->params.rx_fifo_size);
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for (i=0; i < MAX_EPS_CHANNELS; i++)
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if(_params->tx_fifo_size[i] >=0 && _params->tx_fifo_size[i] < _core_if->params.tx_fifo_size[i])
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_core_if->params.tx_fifo_size[i] = _params->tx_fifo_size[i];
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txfifosize.b.startaddr = _core_if->params.rx_fifo_size;
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#ifdef __DED_FIFO__
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if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[0] > _core_if->params.data_fifo_size)
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_core_if->params.tx_fifo_size[0]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
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txfifosize.b.depth=_core_if->params.tx_fifo_size[0];
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ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32);
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txfifosize.b.startaddr += _core_if->params.tx_fifo_size[0];
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for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++)
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{
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if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[i] > _core_if->params.data_fifo_size)
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_core_if->params.tx_fifo_size[i]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
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txfifosize.b.depth=_core_if->params.tx_fifo_size[i];
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ifxusb_wreg( &global_regs->dptxfsiz_dieptxf[i-1], txfifosize.d32);
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txfifosize.b.startaddr += _core_if->params.tx_fifo_size[i];
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}
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#else
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if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[0] > _core_if->params.data_fifo_size)
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_core_if->params.tx_fifo_size[0]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
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txfifosize.b.depth=_core_if->params.tx_fifo_size[0];
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ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32);
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txfifosize.b.startaddr += _core_if->params.tx_fifo_size[0];
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for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
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{
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if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[i+1] > _core_if->params.data_fifo_size)
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_core_if->params.tx_fifo_size[i+1]= _core_if->params.data_fifo_size - txfifosize.b.startaddr;
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//txfifosize.b.depth=_core_if->params.tx_fifo_size[i+1];
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ifxusb_wreg( &global_regs->dptxfsiz_dieptxf[i], txfifosize.d32);
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txfifosize.b.startaddr += _core_if->params.tx_fifo_size[i+1];
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}
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#endif
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}
|
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#ifdef __DEBUG__
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{
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fifosize_data_t fifosize;
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IFX_DEBUGPL(DBG_CIL, "Result : FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size);
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|
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IFX_DEBUGPL(DBG_CIL, " Rx FIFO =0x%06X Sz=0x%06X\n", 0,ifxusb_rreg(&global_regs->grxfsiz));
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#ifdef __DED_FIFO__
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fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz);
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IFX_DEBUGPL(DBG_CIL, " Tx[00] FIFO =0x%06X Sz=0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
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for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++)
|
|
{
|
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fifosize.d32=ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i-1]);
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IFX_DEBUGPL(DBG_CIL, " Tx[%02d] FIFO 0x%06X Sz=0x%06X\n",i, fifosize.b.startaddr,fifosize.b.depth);
|
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}
|
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#else
|
|
fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz);
|
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IFX_DEBUGPL(DBG_CIL, " NPTx FIFO =0x%06X Sz=0x%06X\n", fifosize.b.startaddr,fifosize.b.depth);
|
|
for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
|
|
{
|
|
fifosize.d32=ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i]);
|
|
IFX_DEBUGPL(DBG_CIL, " PTx[%02d] FIFO 0x%06X Sz=0x%06X\n",i, fifosize.b.startaddr,fifosize.b.depth);
|
|
}
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
/* Clear Host Set HNP Enable in the OTG Control Register */
|
|
gotgctl.b.hstsethnpen = 1;
|
|
ifxusb_mreg( &global_regs->gotgctl, gotgctl.d32, 0);
|
|
|
|
/* Flush the FIFOs */
|
|
ifxusb_flush_tx_fifo_d(_core_if, 0x10); /* all Tx FIFOs */
|
|
ifxusb_flush_rx_fifo_d(_core_if);
|
|
|
|
/* Flush the Learning Queue. */
|
|
resetctl.b.intknqflsh = 1;
|
|
ifxusb_wreg( &global_regs->grstctl, resetctl.d32);
|
|
|
|
/* Clear all pending Device Interrupts */
|
|
ifxusb_wreg( &_core_if->dev_global_regs->diepmsk , 0 );
|
|
ifxusb_wreg( &_core_if->dev_global_regs->doepmsk , 0 );
|
|
ifxusb_wreg( &_core_if->dev_global_regs->daint , 0xFFFFFFFF );
|
|
ifxusb_wreg( &_core_if->dev_global_regs->daintmsk, 0 );
|
|
|
|
dir=_core_if->hwcfg1.d32;
|
|
for (i=0; i <= _core_if->hwcfg2.b.num_dev_ep ; i++,dir>>=2)
|
|
{
|
|
depctl_data_t depctl;
|
|
if((dir&0x03)==0 || (dir&0x03) ==1)
|
|
{
|
|
depctl.d32 = ifxusb_rreg(&_core_if->in_ep_regs[i]->diepctl);
|
|
if (depctl.b.epena)
|
|
{
|
|
depctl.d32 = 0;
|
|
depctl.b.epdis = 1;
|
|
depctl.b.snak = 1;
|
|
}
|
|
else
|
|
depctl.d32 = 0;
|
|
ifxusb_wreg( &_core_if->in_ep_regs[i]->diepctl, depctl.d32);
|
|
#ifndef __DESC_DMA__
|
|
ifxusb_wreg( &_core_if->in_ep_regs[i]->dieptsiz, 0);
|
|
#endif
|
|
ifxusb_wreg( &_core_if->in_ep_regs[i]->diepdma, 0);
|
|
ifxusb_wreg( &_core_if->in_ep_regs[i]->diepint, 0xFF);
|
|
}
|
|
|
|
if((dir&0x03)==0 || (dir&0x03) ==2)
|
|
{
|
|
depctl.d32 = ifxusb_rreg(&_core_if->out_ep_regs[i]->doepctl);
|
|
if (depctl.b.epena)
|
|
{
|
|
depctl.d32 = 0;
|
|
depctl.b.epdis = 1;
|
|
depctl.b.snak = 1;
|
|
}
|
|
else
|
|
depctl.d32 = 0;
|
|
ifxusb_wreg( &_core_if->out_ep_regs[i]->doepctl, depctl.d32);
|
|
#ifndef __DESC_DMA__
|
|
ifxusb_wreg( &_core_if->out_ep_regs[i]->doeptsiz, 0);
|
|
#endif
|
|
ifxusb_wreg( &_core_if->out_ep_regs[i]->doepdma, 0);
|
|
ifxusb_wreg( &_core_if->out_ep_regs[i]->doepint, 0xFF);
|
|
}
|
|
}
|
|
}
|
|
|