15a14cf166
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. LEDE/OPENWRT will auto strip executable program file while make. So we need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network fiemware be destroyed, then run make to build ls1012ardb firmware. The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message. This issue have noticed the IP owner for investigate, hope he can solve it earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4" bootargs. Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
105 lines
3.2 KiB
Diff
105 lines
3.2 KiB
Diff
From 56bd0e13d8bc3b4486251b10ac9d2ba7434c21ee Mon Sep 17 00:00:00 2001
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From: Brian Norris <computersforpeace@gmail.com>
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Date: Tue, 10 Nov 2015 12:15:27 -0800
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Subject: [PATCH 081/113] mtd: spi-nor: provide default erase_sector
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implementation
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Some spi-nor drivers perform sector erase by duplicating their
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write_reg() command. Let's not require that the driver fill this out,
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and provide a default instead.
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Tested on m25p80.c and Medatek's MT8173 SPI NOR flash driver.
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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---
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drivers/mtd/spi-nor/spi-nor.c | 37 +++++++++++++++++++++++++++++++++----
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include/linux/mtd/spi-nor.h | 3 ++-
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2 files changed, 35 insertions(+), 5 deletions(-)
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -38,6 +38,7 @@
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#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
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#define SPI_NOR_MAX_ID_LEN 6
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+#define SPI_NOR_MAX_ADDR_WIDTH 4
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struct flash_info {
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char *name;
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@@ -313,6 +314,29 @@ static void spi_nor_unlock_and_unprep(st
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}
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/*
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+ * Initiate the erasure of a single sector
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+ */
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+static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
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+{
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+ u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
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+ int i;
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+
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+ if (nor->erase)
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+ return nor->erase(nor, addr);
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+
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+ /*
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+ * Default implementation, if driver doesn't have a specialized HW
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+ * control
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+ */
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+ for (i = nor->addr_width - 1; i >= 0; i--) {
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+ buf[i] = addr & 0xff;
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+ addr >>= 8;
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+ }
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+
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+ return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
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+}
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+
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+/*
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* Erase an address range on the nor chip. The address range may extend
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* one or more erase sectors. Return an error is there is a problem erasing.
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*/
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@@ -371,10 +395,9 @@ static int spi_nor_erase(struct mtd_info
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while (len) {
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write_enable(nor);
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- if (nor->erase(nor, addr)) {
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- ret = -EIO;
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+ ret = spi_nor_erase_sector(nor, addr);
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+ if (ret)
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goto erase_err;
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- }
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addr += mtd->erasesize;
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len -= mtd->erasesize;
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@@ -1098,7 +1121,7 @@ static int set_quad_mode(struct spi_nor
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static int spi_nor_check(struct spi_nor *nor)
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{
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if (!nor->dev || !nor->read || !nor->write ||
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- !nor->read_reg || !nor->write_reg || !nor->erase) {
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+ !nor->read_reg || !nor->write_reg) {
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pr_err("spi-nor: please fill all the necessary fields!\n");
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return -EINVAL;
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}
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@@ -1299,6 +1322,12 @@ int spi_nor_scan(struct spi_nor *nor, co
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nor->addr_width = 3;
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}
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+ if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
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+ dev_err(dev, "address width is too large: %u\n",
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+ nor->addr_width);
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+ return -EINVAL;
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+ }
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+
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nor->read_dummy = spi_nor_read_dummy_cycles(nor);
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dev_info(dev, "%s (%lld Kbytes)\n", info->name,
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--- a/include/linux/mtd/spi-nor.h
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+++ b/include/linux/mtd/spi-nor.h
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@@ -142,7 +142,8 @@ enum spi_nor_option_flags {
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* @read: [DRIVER-SPECIFIC] read data from the SPI NOR
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* @write: [DRIVER-SPECIFIC] write data to the SPI NOR
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* @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
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- * at the offset @offs
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+ * at the offset @offs; if not provided by the driver,
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+ * spi-nor will send the erase opcode via write_reg()
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* @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
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* @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
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* @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
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