2b1c6b21b5
As usual these patches were extracted and rebased from the raspberry pi repo: https://github.com/raspberrypi/linux/tree/rpi-4.4.y Also adds support for Raspberry Pi Compute Module 3 (untested). Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
133 lines
4.2 KiB
Diff
133 lines
4.2 KiB
Diff
From 111293a9f0aa27bfdbb0ca864d9524691bb5934f Mon Sep 17 00:00:00 2001
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From: Martin Sperl <kernel@martin.sperl.org>
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Date: Mon, 29 Feb 2016 11:39:21 +0000
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Subject: [PATCH] clk: bcm2835: correctly enable fractional clock support
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The current driver calculates the clock divider with
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fractional support enabled.
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But it does not enable fractional support in the
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control register itself resulting in an integer only divider,
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but in clk_set_rate responds back the fractionally divided
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clock frequency.
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This patch enables fractional support in the control register
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whenever there is a fractional bit set in the requested clock divider.
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Mash clock limits are are also handled for the PWM clock
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applying the correct divider limits (2 and max_int) applicable to
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basic fractional divider support (mash order of 1).
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It also adds locking to protect the read/modify/write cycle of
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the register modification.
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Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
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audio domain clocks")
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Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit 959ca92a3235fc4b17c1e18483fc390b3d612254)
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---
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drivers/clk/bcm/clk-bcm2835.c | 45 +++++++++++++++++++++++++++++++++++++------
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1 file changed, 39 insertions(+), 6 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -51,6 +51,7 @@
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#define CM_GNRICCTL 0x000
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#define CM_GNRICDIV 0x004
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# define CM_DIV_FRAC_BITS 12
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+# define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
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#define CM_VPUCTL 0x008
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#define CM_VPUDIV 0x00c
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@@ -128,6 +129,7 @@
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# define CM_GATE BIT(CM_GATE_BIT)
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# define CM_BUSY BIT(7)
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# define CM_BUSYD BIT(8)
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+# define CM_FRAC BIT(9)
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# define CM_SRC_SHIFT 0
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# define CM_SRC_BITS 4
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# define CM_SRC_MASK 0xf
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@@ -647,6 +649,7 @@ struct bcm2835_clock_data {
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u32 frac_bits;
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bool is_vpu_clock;
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+ bool is_mash_clock;
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};
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static const char *const bcm2835_clock_per_parents[] = {
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@@ -828,6 +831,7 @@ static const struct bcm2835_clock_data b
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.div_reg = CM_PWMDIV,
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.int_bits = 12,
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.frac_bits = 12,
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+ .is_mash_clock = true,
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};
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struct bcm2835_pll {
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@@ -1196,7 +1200,7 @@ static u32 bcm2835_clock_choose_div(stru
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GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
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u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
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u64 rem;
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- u32 div;
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+ u32 div, mindiv, maxdiv;
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rem = do_div(temp, rate);
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div = temp;
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@@ -1206,11 +1210,23 @@ static u32 bcm2835_clock_choose_div(stru
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div += unused_frac_mask + 1;
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div &= ~unused_frac_mask;
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- /* clamp to min divider of 1 */
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- div = max_t(u32, div, 1 << CM_DIV_FRAC_BITS);
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- /* clamp to the highest possible fractional divider */
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- div = min_t(u32, div, GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
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- CM_DIV_FRAC_BITS - data->frac_bits));
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+ /* different clamping limits apply for a mash clock */
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+ if (data->is_mash_clock) {
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+ /* clamp to min divider of 2 */
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+ mindiv = 2 << CM_DIV_FRAC_BITS;
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+ /* clamp to the highest possible integer divider */
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+ maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS;
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+ } else {
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+ /* clamp to min divider of 1 */
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+ mindiv = 1 << CM_DIV_FRAC_BITS;
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+ /* clamp to the highest possible fractional divider */
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+ maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
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+ CM_DIV_FRAC_BITS - data->frac_bits);
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+ }
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+
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+ /* apply the clamping limits */
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+ div = max_t(u32, div, mindiv);
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+ div = min_t(u32, div, maxdiv);
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return div;
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}
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@@ -1304,9 +1320,26 @@ static int bcm2835_clock_set_rate(struct
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struct bcm2835_cprman *cprman = clock->cprman;
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const struct bcm2835_clock_data *data = clock->data;
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u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false);
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+ u32 ctl;
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+
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+ spin_lock(&cprman->regs_lock);
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+
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+ /*
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+ * Setting up frac support
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+ *
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+ * In principle it is recommended to stop/start the clock first,
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+ * but as we set CLK_SET_RATE_GATE during registration of the
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+ * clock this requirement should be take care of by the
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+ * clk-framework.
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+ */
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+ ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
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+ ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
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+ cprman_write(cprman, data->ctl_reg, ctl);
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cprman_write(cprman, data->div_reg, div);
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+ spin_unlock(&cprman->regs_lock);
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+
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return 0;
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}
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