e2aa0c3f8b
Refreshed all patches Dropped upstreamed patches: 522-PCI-aardvark-fix-logic-in-PCI-configuration-read-write-functions.patch 523-PCI-aardvark-set-PIO_ADDR_LS-correctly-in-advk_pcie_rd_conf.patch 525-PCI-aardvark-use-isr1-instead-of-isr0-interrupt-in-legacy-irq-mode.patch 527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch updated patches: 524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch 030-USB-serial-option-fix-dwm-158-3g-modem-interface.patch Added new ARM64 symbol: CONFIG_ARM64_ERRATUM_1024718 Compile-tested on: cns3xxx, imx6, mvebu (arm64), x86_64 Runtime-tested on: cns3xxx, imx6, x86_64 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
100 lines
3.3 KiB
Diff
100 lines
3.3 KiB
Diff
From 308c2ef9c4f1be2e1cee699042671eb973b51803 Mon Sep 17 00:00:00 2001
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From: Mathias Kresin <dev@kresin.me>
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Date: Tue, 6 Mar 2018 08:37:43 +0100
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Subject: [PATCH 19/27] MIPS: ath79: get PCIe controller out of reset
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The ar724x pci driver expects the PCIe controller to be brought out of
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reset by the bootloader.
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At least the AVM Fritz 300E bootloader doesn't take care of releasing
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the different PCIe controller related resets which causes an endless
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hang as soon as either the PCIE Reset register (0x180f0018) or the PCI
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Application Control register (0x180f0000) is read from.
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Do the full "PCIE Root Complex Initialization Sequence" if the PCIe
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host controller is still in reset during probing.
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The QCA u-boot sleeps 10ms after the PCIE Application Control bit is
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set to ready. It has been shown that 10ms might not be enough time if
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PCIe should be used right after setting the bit. During my tests it
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took up to 20ms till the link was up. Giving the link up to 100ms
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should work for all cases.
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Signed-off-by: Mathias Kresin <dev@kresin.me>
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---
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arch/mips/pci/pci-ar724x.c | 42 ++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 42 insertions(+)
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--- a/arch/mips/pci/pci-ar724x.c
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+++ b/arch/mips/pci/pci-ar724x.c
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@@ -12,14 +12,18 @@
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#include <linux/irq.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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+#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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+#define AR724X_PCI_REG_APP 0x00
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#define AR724X_PCI_REG_RESET 0x18
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#define AR724X_PCI_REG_INT_STATUS 0x4c
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#define AR724X_PCI_REG_INT_MASK 0x50
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+#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
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+
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#define AR724X_PCI_RESET_LINK_UP BIT(0)
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#define AR724X_PCI_INT_DEV0 BIT(14)
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@@ -325,6 +329,37 @@ static void ar724x_pci_irq_init(struct a
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apc);
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}
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+static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc)
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+{
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+ u32 ppl, app;
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+ int wait = 0;
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+
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+ /* deassert PCIe host controller and PCIe PHY reset */
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+ ath79_device_reset_clear(AR724X_RESET_PCIE);
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+ ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
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+
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+ /* remove the reset of the PCIE PLL */
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+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
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+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
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+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
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+
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+ /* deassert bypass for the PCIE PLL */
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+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
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+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
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+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
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+
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+ /* set PCIE Application Control to ready */
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+ app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
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+ app |= AR724X_PCI_APP_LTSSM_ENABLE;
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+ __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP);
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+
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+ /* wait up to 100ms for PHY link up */
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+ do {
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+ mdelay(10);
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+ wait++;
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+ } while (wait < 10 && !ar724x_pci_check_link(apc));
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+}
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+
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static int ar724x_pci_probe(struct platform_device *pdev)
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{
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struct ar724x_pci_controller *apc;
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@@ -383,6 +418,13 @@ static int ar724x_pci_probe(struct platf
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apc->pci_controller.io_resource = &apc->io_res;
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apc->pci_controller.mem_resource = &apc->mem_res;
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+ /*
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+ * Do the full PCIE Root Complex Initialization Sequence if the PCIe
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+ * host controller is in reset.
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+ */
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+ if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
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+ ar724x_pci_hw_init(apc);
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+
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apc->link_up = ar724x_pci_check_link(apc);
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if (!apc->link_up)
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dev_warn(&pdev->dev, "PCIe link is down\n");
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