openwrtv4/target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts
David Bauer 6555612783 ath79: fix PLL settings for QCA955x
This adds PLL settings for the ethernet ports of the TP-Link TL-WR1043
v2/v3 and the Openmesh OM5P-AC-v2.

We also change the PLL-settings in the qca9557.dtsi to match the ones
used as default on the ar71xx target.

As of 4b9680f138 those devices have broken ethernet ports as the default
PLL settings defined in the QCA9557.dtsi are applied which are off for
those devices.

Signed-off-by: David Bauer <mail@david-bauer.net>
2018-08-09 17:24:39 +01:00

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2.6 KiB
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "qca9557.dtsi"
/ {
compatible = "openmesh,om5p-ac-v2", "qca,qca9557";
model = "OpenMesh OM5P-AC V2";
extosc: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "ref";
clock-frequency = <40000000>;
};
leds {
compatible = "gpio-leds";
power {
label = "om5pac:blue:power";
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
default-state = "off";
};
wifi_green {
label = "om5pac:green:wifi";
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
default-state = "off";
};
wifi_yellow {
label = "om5pac:yellow:wifi";
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
default-state = "off";
};
wifi_red {
label = "om5pac:red:wifi";
gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
keys {
compatible = "gpio-keys-polled";
poll-interval = <100>;
button0 {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
};
};
gpio-export {
compatible = "gpio-export";
#size-cells = <0>;
gpio_pa_dcdc {
gpio-export,name = "om5pac:pa_dcdc";
gpio-export,output = <1>;
gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
};
gpio_pa_high {
gpio-export,name = "om5pac:pa_high";
gpio-export,output = <1>;
gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
};
};
};
&pinmux {
pinmux_pa_dcdc_pins {
pinctrl-single,bits = <0x0 0xff00 0x0>;
};
pinmux_pa_high_pins {
pinctrl-single,bits = <0x10 0xff 0x0>;
};
};
&pcie0 {
status = "okay";
};
&uart {
status = "okay";
};
&pll {
clocks = <&extosc>;
};
&spi {
status = "okay";
num-cs = <1>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x000000 0x040000>;
read-only;
};
partition@1 {
label = "u-boot-env";
reg = <0x040000 0x010000>;
};
partition@2 {
label = "firmware";
reg = <0x850000 0x7a0000>;
};
partition@3 {
label = "ART";
reg = <0xff0000 0x010000>;
read-only;
};
};
};
};
&mdio0 {
status = "okay";
phy4: ethernet-phy@4 {
reg = <4>;
phy-mode = "rgmii-id";
};
};
&mdio1 {
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
phy-mode = "sgmii";
};
};
&eth0 {
status = "okay";
pll-data = <0x82000101 0x80000101 0x80001313>;
phy-handle = <&phy4>;
phy-mode = "rgmii";
};
&eth1 {
status = "okay";
pll-data = <0x03000101 0x80000101 0x80001313>;
phy-handle = <&phy1>;
phy-mode = "sgmii";
};