421 lines
12 KiB
Diff
421 lines
12 KiB
Diff
From 5afd20a1eeef4db1d694d58931519f65e2003503 Mon Sep 17 00:00:00 2001
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From: Stuart Menefy <stuart.menefy@st.com>
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Date: Wed, 26 Jun 2013 12:48:38 +0100
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Subject: [PATCH 01/18] clocksource: arm_global_timer: Add ARM global timer
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support
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This is a simple driver for the global timer module found in the Cortex
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A9-MP cores from revision r1p0 onwards. This should be able to perform
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the functions of the system timer and the local timer in an SMP system.
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The global timer has the following features:
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The global timer is a 64-bit incrementing counter with an
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auto-incrementing feature. It continues incrementing after sending
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interrupts. The global timer is memory mapped in the private memory
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region.
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The global timer is accessible to all Cortex-A9 processors in the
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cluster. Each Cortex-A9 processor has a private 64-bit comparator that
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is used to assert a private interrupt when the global timer has reached
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the comparator value. All the Cortex-A9 processors in a design use the
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banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
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Controller as a Private Peripheral Interrupt. The global timer is
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clocked by PERIPHCLK.
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Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
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Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
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CC: Arnd Bergmann <arnd@arndb.de>
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CC: Rob Herring <robherring2@gmail.com>
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CC: Linus Walleij <linus.walleij@linaro.org>
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CC: Will Deacon <will.deacon@arm.com>
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CC: Thomas Gleixner <tglx@linutronix.de>
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Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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---
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.../devicetree/bindings/arm/global_timer.txt | 24 ++
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drivers/clocksource/Kconfig | 13 +
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drivers/clocksource/Makefile | 1 +
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drivers/clocksource/arm_global_timer.c | 321 ++++++++++++++++++++
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4 files changed, 359 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/arm/global_timer.txt
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create mode 100644 drivers/clocksource/arm_global_timer.c
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/arm/global_timer.txt
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@@ -0,0 +1,24 @@
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+
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+* ARM Global Timer
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+ Cortex-A9 are often associated with a per-core Global timer.
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+
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+** Timer node required properties:
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+
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+- compatible : Should be "arm,cortex-a9-global-timer"
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+ Driver supports versions r2p0 and above.
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+
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+- interrupts : One interrupt to each core
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+
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+- reg : Specify the base address and the size of the GT timer
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+ register window.
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+
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+- clocks : Should be phandle to a clock.
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+
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+Example:
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+
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+ timer@2c000600 {
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+ compatible = "arm,cortex-a9-global-timer";
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+ reg = <0x2c000600 0x20>;
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+ interrupts = <1 13 0xf01>;
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+ clocks = <&arm_periph_clk>;
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+ };
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--- a/drivers/clocksource/Kconfig
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+++ b/drivers/clocksource/Kconfig
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@@ -67,6 +67,19 @@ config ARM_ARCH_TIMER
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bool
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select CLKSRC_OF if OF
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+config ARM_GLOBAL_TIMER
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+ bool
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+ select CLKSRC_OF if OF
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+ help
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+ This options enables support for the ARM global timer unit
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+
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+config CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
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+ bool
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+ depends on ARM_GLOBAL_TIMER
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+ default y
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+ help
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+ Use ARM global timer clock source as sched_clock
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+
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config CLKSRC_METAG_GENERIC
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def_bool y if METAG
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help
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--- a/drivers/clocksource/Makefile
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+++ b/drivers/clocksource/Makefile
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@@ -28,4 +28,5 @@ obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exyno
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obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o
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obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
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+obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
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obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o
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--- /dev/null
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+++ b/drivers/clocksource/arm_global_timer.c
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@@ -0,0 +1,321 @@
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+/*
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+ * drivers/clocksource/arm_global_timer.c
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+ *
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+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
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+ * Author: Stuart Menefy <stuart.menefy@st.com>
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+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/interrupt.h>
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+#include <linux/clocksource.h>
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+#include <linux/clockchips.h>
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+#include <linux/cpu.h>
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+#include <linux/clk.h>
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/of.h>
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+#include <linux/of_irq.h>
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+#include <linux/of_address.h>
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+#include <asm/sched_clock.h>
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+
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+#include <asm/cputype.h>
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+
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+#define GT_COUNTER0 0x00
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+#define GT_COUNTER1 0x04
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+
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+#define GT_CONTROL 0x08
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+#define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */
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+#define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */
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+#define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */
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+#define GT_CONTROL_AUTO_INC BIT(3) /* banked */
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+
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+#define GT_INT_STATUS 0x0c
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+#define GT_INT_STATUS_EVENT_FLAG BIT(0)
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+
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+#define GT_COMP0 0x10
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+#define GT_COMP1 0x14
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+#define GT_AUTO_INC 0x18
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+
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+/*
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+ * We are expecting to be clocked by the ARM peripheral clock.
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+ *
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+ * Note: it is assumed we are using a prescaler value of zero, so this is
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+ * the units for all operations.
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+ */
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+static void __iomem *gt_base;
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+static unsigned long gt_clk_rate;
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+static int gt_ppi;
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+static struct clock_event_device __percpu *gt_evt;
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+
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+/*
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+ * To get the value from the Global Timer Counter register proceed as follows:
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+ * 1. Read the upper 32-bit timer counter register
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+ * 2. Read the lower 32-bit timer counter register
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+ * 3. Read the upper 32-bit timer counter register again. If the value is
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+ * different to the 32-bit upper value read previously, go back to step 2.
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+ * Otherwise the 64-bit timer counter value is correct.
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+ */
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+static u64 gt_counter_read(void)
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+{
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+ u64 counter;
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+ u32 lower;
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+ u32 upper, old_upper;
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+
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+ upper = readl_relaxed(gt_base + GT_COUNTER1);
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+ do {
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+ old_upper = upper;
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+ lower = readl_relaxed(gt_base + GT_COUNTER0);
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+ upper = readl_relaxed(gt_base + GT_COUNTER1);
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+ } while (upper != old_upper);
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+
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+ counter = upper;
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+ counter <<= 32;
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+ counter |= lower;
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+ return counter;
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+}
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+
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+/**
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+ * To ensure that updates to comparator value register do not set the
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+ * Interrupt Status Register proceed as follows:
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+ * 1. Clear the Comp Enable bit in the Timer Control Register.
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+ * 2. Write the lower 32-bit Comparator Value Register.
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+ * 3. Write the upper 32-bit Comparator Value Register.
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+ * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.
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+ */
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+static void gt_compare_set(unsigned long delta, int periodic)
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+{
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+ u64 counter = gt_counter_read();
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+ unsigned long ctrl;
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+
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+ counter += delta;
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+ ctrl = GT_CONTROL_TIMER_ENABLE;
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+ writel(ctrl, gt_base + GT_CONTROL);
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+ writel(lower_32_bits(counter), gt_base + GT_COMP0);
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+ writel(upper_32_bits(counter), gt_base + GT_COMP1);
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+
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+ if (periodic) {
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+ writel(delta, gt_base + GT_AUTO_INC);
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+ ctrl |= GT_CONTROL_AUTO_INC;
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+ }
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+
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+ ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
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+ writel(ctrl, gt_base + GT_CONTROL);
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+}
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+
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+static void gt_clockevent_set_mode(enum clock_event_mode mode,
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+ struct clock_event_device *clk)
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+{
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+ unsigned long ctrl;
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+
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+ switch (mode) {
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+ case CLOCK_EVT_MODE_PERIODIC:
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+ gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1);
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+ break;
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+ case CLOCK_EVT_MODE_ONESHOT:
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+ case CLOCK_EVT_MODE_UNUSED:
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+ case CLOCK_EVT_MODE_SHUTDOWN:
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+ ctrl = readl(gt_base + GT_CONTROL);
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+ ctrl &= ~(GT_CONTROL_COMP_ENABLE |
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+ GT_CONTROL_IRQ_ENABLE | GT_CONTROL_AUTO_INC);
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+ writel(ctrl, gt_base + GT_CONTROL);
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+ break;
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+ default:
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+ break;
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+ }
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+}
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+
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+static int gt_clockevent_set_next_event(unsigned long evt,
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+ struct clock_event_device *unused)
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+{
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+ gt_compare_set(evt, 0);
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+ return 0;
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+}
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+
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+static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
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+{
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+ struct clock_event_device *evt = dev_id;
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+
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+ if (!(readl_relaxed(gt_base + GT_INT_STATUS) &
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+ GT_INT_STATUS_EVENT_FLAG))
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+ return IRQ_NONE;
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+
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+ /**
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+ * ERRATA 740657( Global Timer can send 2 interrupts for
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+ * the same event in single-shot mode)
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+ * Workaround:
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+ * Either disable single-shot mode.
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+ * Or
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+ * Modify the Interrupt Handler to avoid the
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+ * offending sequence. This is achieved by clearing
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+ * the Global Timer flag _after_ having incremented
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+ * the Comparator register value to a higher value.
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+ */
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+ if (evt->mode == CLOCK_EVT_MODE_ONESHOT)
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+ gt_compare_set(ULONG_MAX, 0);
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+
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+ writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
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+ evt->event_handler(evt);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static int __cpuinit gt_clockevents_init(struct clock_event_device *clk)
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+{
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+ int cpu = smp_processor_id();
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+
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+ clk->name = "arm_global_timer";
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+ clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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+ clk->set_mode = gt_clockevent_set_mode;
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+ clk->set_next_event = gt_clockevent_set_next_event;
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+ clk->cpumask = cpumask_of(cpu);
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+ clk->rating = 300;
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+ clk->irq = gt_ppi;
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+ clockevents_config_and_register(clk, gt_clk_rate,
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+ 1, 0xffffffff);
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+ enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
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+ return 0;
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+}
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+
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+static void gt_clockevents_stop(struct clock_event_device *clk)
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+{
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+ gt_clockevent_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
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+ disable_percpu_irq(clk->irq);
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+}
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+
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+static cycle_t gt_clocksource_read(struct clocksource *cs)
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+{
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+ return gt_counter_read();
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+}
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+
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+static struct clocksource gt_clocksource = {
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+ .name = "arm_global_timer",
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+ .rating = 300,
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+ .read = gt_clocksource_read,
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+ .mask = CLOCKSOURCE_MASK(64),
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+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
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+};
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+
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+#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
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+static u32 notrace gt_sched_clock_read(void)
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+{
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+ return gt_counter_read();
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+}
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+#endif
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+
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+static void __init gt_clocksource_init(void)
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+{
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+ writel(0, gt_base + GT_CONTROL);
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+ writel(0, gt_base + GT_COUNTER0);
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+ writel(0, gt_base + GT_COUNTER1);
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+ /* enables timer on all the cores */
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+ writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
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+
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+#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
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+ setup_sched_clock(gt_sched_clock_read, 32, gt_clk_rate);
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+#endif
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+ clocksource_register_hz(>_clocksource, gt_clk_rate);
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+}
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+
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+static int __cpuinit gt_cpu_notify(struct notifier_block *self,
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+ unsigned long action, void *hcpu)
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+{
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+ switch (action & ~CPU_TASKS_FROZEN) {
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+ case CPU_STARTING:
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+ gt_clockevents_init(this_cpu_ptr(gt_evt));
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+ break;
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+ case CPU_DYING:
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+ gt_clockevents_stop(this_cpu_ptr(gt_evt));
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+ break;
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+ }
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+
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+ return NOTIFY_OK;
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+}
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+static struct notifier_block gt_cpu_nb __cpuinitdata = {
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+ .notifier_call = gt_cpu_notify,
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+};
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+
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+static void __init global_timer_of_register(struct device_node *np)
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+{
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+ struct clk *gt_clk;
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+ int err = 0;
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+
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+ /*
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+ * In r2p0 the comparators for each processor with the global timer
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+ * fire when the timer value is greater than or equal to. In previous
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+ * revisions the comparators fired when the timer value was equal to.
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+ */
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+ if ((read_cpuid_id() & 0xf0000f) < 0x200000) {
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+ pr_warn("global-timer: non support for this cpu version.\n");
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+ return;
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+ }
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+
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+ gt_ppi = irq_of_parse_and_map(np, 0);
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+ if (!gt_ppi) {
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+ pr_warn("global-timer: unable to parse irq\n");
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+ return;
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+ }
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+
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+ gt_base = of_iomap(np, 0);
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+ if (!gt_base) {
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+ pr_warn("global-timer: invalid base address\n");
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+ return;
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+ }
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+
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+ gt_clk = of_clk_get(np, 0);
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+ if (!IS_ERR(gt_clk)) {
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+ err = clk_prepare_enable(gt_clk);
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+ if (err)
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+ goto out_unmap;
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+ } else {
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+ pr_warn("global-timer: clk not found\n");
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+ err = -EINVAL;
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+ goto out_unmap;
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+ }
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+
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+ gt_clk_rate = clk_get_rate(gt_clk);
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+ gt_evt = alloc_percpu(struct clock_event_device);
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+ if (!gt_evt) {
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+ pr_warn("global-timer: can't allocate memory\n");
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+ err = -ENOMEM;
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+ goto out_clk;
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+ }
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+
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+ err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt,
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+ "gt", gt_evt);
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+ if (err) {
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+ pr_warn("global-timer: can't register interrupt %d (%d)\n",
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+ gt_ppi, err);
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+ goto out_free;
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+ }
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+
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+ err = register_cpu_notifier(>_cpu_nb);
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+ if (err) {
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+ pr_warn("global-timer: unable to register cpu notifier.\n");
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+ goto out_irq;
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+ }
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+
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+ /* Immediately configure the timer on the boot CPU */
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+ gt_clocksource_init();
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+ gt_clockevents_init(this_cpu_ptr(gt_evt));
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+
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+ return;
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+
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+out_irq:
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+ free_percpu_irq(gt_ppi, gt_evt);
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+out_free:
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+ free_percpu(gt_evt);
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+out_clk:
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+ clk_disable_unprepare(gt_clk);
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+out_unmap:
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+ iounmap(gt_base);
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+ WARN(err, "ARM Global timer register failed (%d)\n", err);
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+}
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+
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+/* Only tested on r2p2 and r3p0 */
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+CLOCKSOURCE_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
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+ global_timer_of_register);
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