b50fd8c2b3
Register SPI controllers through device tree. We will wire up the clocks at a later stage. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
35 lines
1,015 B
Diff
35 lines
1,015 B
Diff
From d03f23df6ff47898d76f06b3aa5dadcfa1ec8f4f Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Sun, 19 Feb 2017 23:40:22 +0100
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Subject: [PATCH 1/3] spi/bcm63xx-hsspi: allow providing clock rate through a
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second clock
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Instead of requiring the hsspi clock to have a rate, allow using a second
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clock for providing the Hz rate, which is probably more correct anyway.
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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drivers/spi/spi-bcm63xx-hsspi.c | 12 ++++++++++--
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1 file changed, 10 insertions(+), 2 deletions(-)
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--- a/drivers/spi/spi-bcm63xx-hsspi.c
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+++ b/drivers/spi/spi-bcm63xx-hsspi.c
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@@ -351,8 +351,16 @@ static int bcm63xx_hsspi_probe(struct pl
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return PTR_ERR(clk);
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rate = clk_get_rate(clk);
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- if (!rate)
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- return -EINVAL;
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+ if (!rate) {
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+ struct clk *pll_clk = devm_clk_get(dev, "pll");
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+
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+ if (IS_ERR(pll_clk))
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+ return PTR_ERR(pll_clk);
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+
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+ rate = clk_get_rate(pll_clk);
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+ if (!rate)
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+ return -EINVAL;
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+ }
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ret = clk_prepare_enable(clk);
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if (ret)
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