092e77d948
Patches by Jes Sorensen: https://git.kernel.org/cgit/linux/kernel/git/jes/linux.git/ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
102 lines
2.6 KiB
Diff
102 lines
2.6 KiB
Diff
From 7016570c33d1f135f60b38461a3b7ed161911157 Mon Sep 17 00:00:00 2001
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From: Jes Sorensen <Jes.Sorensen@redhat.com>
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Date: Mon, 27 Jun 2016 17:08:30 -0400
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Subject: [PATCH] rtl8xxxu: First stab at rtl8188e_power_on()
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Code based on code from Andrea Merello.
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Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
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---
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.../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c | 79 ++++++++++++++++++++++
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1 file changed, 79 insertions(+)
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--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
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+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c
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@@ -92,8 +92,87 @@ static int rtl8188eu_load_firmware(struc
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return ret;
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}
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+static int rtl8188e_emu_to_active(struct rtl8xxxu_priv *priv)
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+{
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+ u8 val8;
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+ u32 val32;
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+ u16 val16;
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+ int count, ret = 0;
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+
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+ /* wait till 0x04[17] = 1 power ready*/
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+ for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
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+ val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
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+ if (val32 & BIT(17))
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+ break;
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+
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+ udelay(10);
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+ }
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+
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+ if (!count) {
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+ ret = -EBUSY;
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+ goto exit;
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+ }
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+
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+ /* reset baseband */
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+ val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
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+ val8 &= ~(SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN);
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+ rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
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+
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+ /*0x24[23] = 2b'01 schmit trigger */
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+ val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
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+ val32 |= BIT(23);
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+ rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
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+
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+ /* 0x04[15] = 0 disable HWPDN (control by DRV)*/
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+ val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
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+ val16 &= ~APS_FSMCO_HW_POWERDOWN;
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+ rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
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+
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+ /*0x04[12:11] = 2b'00 disable WL suspend*/
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+ val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
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+ val16 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
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+ rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
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+
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+ /* set, then poll until 0 */
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+ val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
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+ val32 |= APS_FSMCO_MAC_ENABLE;
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+ rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
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+
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+ for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
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+ val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
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+ if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
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+ ret = 0;
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+ break;
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+ }
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+ udelay(10);
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+ }
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+
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+ if (!count) {
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+ ret = -EBUSY;
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+ goto exit;
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+ }
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+
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+ /* LDO normal mode*/
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+ val8 = rtl8xxxu_read8(priv, REG_LPLDO_CTRL);
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+ val8 &= ~BIT(4);
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+ rtl8xxxu_write8(priv, REG_LPLDO_CTRL, val8);
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+
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+exit:
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+ return ret;
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+}
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+
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+static int rtl8188eu_power_on(struct rtl8xxxu_priv *priv)
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+{
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+ int ret;
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+
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+ ret = rtl8188e_emu_to_active(priv);
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+
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+ return ret;
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+}
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+
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struct rtl8xxxu_fileops rtl8188eu_fops = {
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.parse_efuse = rtl8188eu_parse_efuse,
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.load_firmware = rtl8188eu_load_firmware,
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+ .power_on = rtl8188eu_power_on,
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.reset_8051 = rtl8xxxu_reset_8051,
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};
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