c6c731fe31
Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
81 lines
1.7 KiB
Diff
81 lines
1.7 KiB
Diff
From e2b301610e6201df40deb62942b18c772365eb1c Mon Sep 17 00:00:00 2001
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From: Shaohui Xie <Shaohui.Xie@freescale.com>
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Date: Thu, 21 Jan 2016 11:29:22 +0800
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Subject: [PATCH 13/70] dts: ls1043ardb: add mdio & phy nodes
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Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 65 +++++++++++++++++++++
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1 file changed, 65 insertions(+)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
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@@ -115,3 +115,68 @@
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&duart1 {
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status = "okay";
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};
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+
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+&fman0 {
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+ ethernet@e0000 {
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+ phy-handle = <&qsgmii_phy1>;
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+ phy-connection-type = "qsgmii";
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+ };
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+
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+ ethernet@e2000 {
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+ phy-handle = <&qsgmii_phy2>;
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+ phy-connection-type = "qsgmii";
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+ };
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+
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+ ethernet@e4000 {
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+ phy-handle = <&rgmii_phy1>;
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+ phy-connection-type = "rgmii";
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+ };
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+
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+ ethernet@e6000 {
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+ phy-handle = <&rgmii_phy2>;
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+ phy-connection-type = "rgmii";
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+ };
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+
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+ ethernet@e8000 {
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+ phy-handle = <&qsgmii_phy3>;
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+ phy-connection-type = "qsgmii";
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+ };
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+
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+ ethernet@ea000 {
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+ phy-handle = <&qsgmii_phy4>;
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+ phy-connection-type = "qsgmii";
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+ };
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+
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+ ethernet@f0000 { /* 10GEC1 */
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+ phy-handle = <&aqr105_phy>;
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+ phy-connection-type = "xgmii";
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+ };
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+
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+ mdio@fc000 {
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+ rgmii_phy1: ethernet-phy@1 {
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+ reg = <0x1>;
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+ };
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+ rgmii_phy2: ethernet-phy@2 {
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+ reg = <0x2>;
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+ };
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+ qsgmii_phy1: ethernet-phy@3 {
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+ reg = <0x4>;
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+ };
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+ qsgmii_phy2: ethernet-phy@4 {
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+ reg = <0x5>;
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+ };
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+ qsgmii_phy3: ethernet-phy@5 {
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+ reg = <0x6>;
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+ };
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+ qsgmii_phy4: ethernet-phy@6 {
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+ reg = <0x7>;
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+ };
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+ };
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+
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+ mdio@fd000 {
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+ aqr105_phy: ethernet-phy@c {
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ reg = <0x1>;
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+ };
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+ };
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+};
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