21802f22f0
accidentially removed the files in the v4.4 commit Signed-off-by: John Crispin <john@phrozen.org>
160 lines
3.2 KiB
Diff
160 lines
3.2 KiB
Diff
From a32d6e7c8fca6371a2614924b89981bc912b6378 Mon Sep 17 00:00:00 2001
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From: Mathieu Olivari <mathieu@codeaurora.org>
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Date: Tue, 7 Apr 2015 19:58:58 -0700
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Subject: [PATCH] ARM: dts: qcom: add initial DB149 device-tree
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Add basic DB149 (IPQ806x based platform) device-tree. It supports UART,
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SATA, USB2, USB3 and NOR flash.
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Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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---
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arch/arm/boot/dts/Makefile | 1 +
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arch/arm/boot/dts/qcom-ipq8064-db149.dts | 257 +++++++++++++++++++++++++++++++
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2 files changed, 258 insertions(+)
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create mode 100644 arch/arm/boot/dts/qcom-ipq8064-db149.dts
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -360,6 +360,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
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qcom-apq8084-ifc6540.dtb \
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qcom-apq8084-mtp.dtb \
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qcom-ipq8064-ap148.dtb \
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+ qcom-ipq8064-db149.dtb \
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qcom-msm8660-surf.dtb \
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qcom-msm8960-cdp.dtb \
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qcom-msm8974-sony-xperia-honami.dtb
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--- /dev/null
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+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
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@@ -0,0 +1,132 @@
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+#include "qcom-ipq8064-v1.0.dtsi"
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+
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+/ {
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+ model = "Qualcomm IPQ8064/DB149";
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+ compatible = "qcom,ipq8064-db149", "qcom,ipq8064";
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+
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+ reserved-memory {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ rsvd@41200000 {
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+ reg = <0x41200000 0x300000>;
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+ no-map;
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+ };
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+ };
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+
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+ alias {
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+ serial0 = &uart2;
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+ };
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+
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+ chosen {
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+ linux,stdout-path = "serial0:115200n8";
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+ };
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+
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+ soc {
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+ pinmux@800000 {
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+ i2c4_pins: i2c4_pinmux {
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+ pins = "gpio12", "gpio13";
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+ function = "gsbi4";
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+ bias-disable;
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+ };
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+
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+ spi_pins: spi_pins {
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+ mux {
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+ pins = "gpio18", "gpio19", "gpio21";
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+ function = "gsbi5";
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+ drive-strength = <10>;
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+ bias-none;
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+ };
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+ };
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+ };
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+
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+ gsbi2: gsbi@12480000 {
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+ qcom,mode = <GSBI_PROT_I2C_UART>;
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+ status = "ok";
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+ uart2: serial@12490000 {
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+ status = "ok";
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+ };
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+ };
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+
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+ gsbi5: gsbi@1a200000 {
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+ qcom,mode = <GSBI_PROT_SPI>;
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+ status = "ok";
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+
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+ spi4: spi@1a280000 {
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+ status = "ok";
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+ spi-max-frequency = <50000000>;
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+
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+ pinctrl-0 = <&spi_pins>;
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+ pinctrl-names = "default";
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+
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+ cs-gpios = <&qcom_pinmux 20 0>;
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+
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+ flash: m25p80@0 {
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+ compatible = "s25fl256s1";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <50000000>;
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+ reg = <0>;
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+ m25p,fast-read;
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+
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+ partition@0 {
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+ label = "lowlevel_init";
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+ reg = <0x0 0x1b0000>;
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+ };
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+
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+ partition@1 {
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+ label = "u-boot";
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+ reg = <0x1b0000 0x80000>;
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+ };
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+
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+ partition@2 {
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+ label = "u-boot-env";
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+ reg = <0x230000 0x40000>;
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+ };
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+
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+ partition@3 {
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+ label = "caldata";
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+ reg = <0x270000 0x40000>;
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+ };
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+
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+ partition@4 {
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+ label = "firmware";
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+ reg = <0x2b0000 0x1d50000>;
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+ };
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+ };
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+ };
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+ };
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+
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+ sata-phy@1b400000 {
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+ status = "ok";
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+ };
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+
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+ sata@29000000 {
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+ status = "ok";
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+ };
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+
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+ phy@100f8800 { /* USB3 port 1 HS phy */
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+ status = "ok";
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+ };
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+
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+ phy@100f8830 { /* USB3 port 1 SS phy */
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+ status = "ok";
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+ };
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+
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+ phy@110f8800 { /* USB3 port 0 HS phy */
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+ status = "ok";
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+ };
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+
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+ phy@110f8830 { /* USB3 port 0 SS phy */
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+ status = "ok";
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+ };
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+
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+ usb30@0 {
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+ status = "ok";
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+ };
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+
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+ usb30@1 {
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+ status = "ok";
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+ };
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+ };
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+};
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