060b161ca6
SVN-Revision: 32953
1458 lines
46 KiB
C
1458 lines
46 KiB
C
/*****************************************************************************
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** FILE NAME : ifxusb_cif.c
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** PROJECT : IFX USB sub-system V3
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** MODULES : IFX USB sub-system Host and Device driver
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** SRC VERSION : 1.0
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** DATE : 1/Jan/2009
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** AUTHOR : Chen, Howard
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** DESCRIPTION : The Core Interface provides basic services for accessing and
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** managing the IFX USB hardware. These services are used by both the
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** Host Controller Driver and the Peripheral Controller Driver.
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*****************************************************************************/
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/*!
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\file ifxusb_cif.c
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\ingroup IFXUSB_DRIVER_V3
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\brief This file contains the interface to the IFX USB Core.
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*/
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#include <linux/clk.h>
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#include <linux/version.h>
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#include "ifxusb_version.h"
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#include <asm/byteorder.h>
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#include <asm/unaligned.h>
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#include <linux/jiffies.h>
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#if defined(__UEIP__)
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// #include <asm/ifx/ifx_pmu.h>
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// #include <ifx_pmu.h>
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#endif
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#include "ifxusb_plat.h"
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#include "ifxusb_regs.h"
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#include "ifxusb_cif.h"
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#ifdef __IS_DEVICE__
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#include "ifxpcd.h"
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#endif
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#ifdef __IS_HOST__
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#include "ifxhcd.h"
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#endif
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#include <linux/mm.h>
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#include <linux/gfp.h>
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#if defined(__UEIP__)
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// #include <asm/ifx/ifx_board.h>
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//#include <ifx_board.h>
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#endif
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//#include <asm/ifx/ifx_gpio.h>
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//#include <ifx_gpio.h>
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#if defined(__UEIP__)
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// #include <asm/ifx/ifx_led.h>
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//#include <ifx_led.h>
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#endif
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#if defined(__UEIP__)
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#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
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#ifndef USB_CTRL_PMU_SETUP
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#define USB_CTRL_PMU_SETUP(__x) USB0_CTRL_PMU_SETUP(__x)
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#endif
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#ifndef USB_PHY_PMU_SETUP
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#define USB_PHY_PMU_SETUP(__x) USB0_PHY_PMU_SETUP(__x)
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#endif
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#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
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#endif // defined(__UEIP__)
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/*!
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\brief This function is called to allocate buffer of specified size.
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The allocated buffer is mapped into DMA accessable address.
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\param size Size in BYTE to be allocated
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\param clear 0: don't do clear after buffer allocated, other: do clear to zero
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\return 0/NULL: Fail; uncached pointer of allocated buffer
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*/
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void *ifxusb_alloc_buf(size_t size, int clear)
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{
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uint32_t *cached,*uncached;
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uint32_t totalsize,page;
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if(!size)
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return 0;
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size=(size+3)&0xFFFFFFFC;
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totalsize=size + 12;
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page=get_order(totalsize);
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cached = (void *) __get_free_pages(( GFP_ATOMIC | GFP_DMA), page);
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if(!cached)
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{
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IFX_PRINT("%s Allocation Failed size:%d\n",__func__,size);
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return NULL;
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}
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uncached = (uint32_t *)(KSEG1ADDR(cached));
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if(clear)
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memset(uncached, 0, totalsize);
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*(uncached+0)=totalsize;
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*(uncached+1)=page;
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*(uncached+2)=(uint32_t)cached;
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return (void *)(uncached+3);
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}
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/*!
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\brief This function is called to free allocated buffer.
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\param vaddr the uncached pointer of the buffer
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*/
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void ifxusb_free_buf(void *vaddr)
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{
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uint32_t totalsize,page;
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uint32_t *cached,*uncached;
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if(vaddr != NULL)
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{
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uncached=vaddr;
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uncached-=3;
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totalsize=*(uncached+0);
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page=*(uncached+1);
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cached=(uint32_t *)(*(uncached+2));
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if(totalsize && page==get_order(totalsize) && cached==(uint32_t *)(KSEG0ADDR(uncached)))
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{
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free_pages((unsigned long)cached, page);
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return;
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}
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// the memory is not allocated by ifxusb_alloc_buf. Allowed but must be careful.
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return;
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}
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}
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/*!
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\brief This function is called to initialize the IFXUSB CSR data
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structures. The register addresses in the device and host
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structures are initialized from the base address supplied by the
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caller. The calling function must make the OS calls to get the
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base address of the IFXUSB controller registers.
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\param _core_if Pointer of core_if structure
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\param _irq irq number
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\param _reg_base_addr Base address of IFXUSB core registers
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\param _fifo_base_addr Fifo base address
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\param _fifo_dbg_addr Fifo debug address
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\return 0: success;
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*/
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int ifxusb_core_if_init(ifxusb_core_if_t *_core_if,
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int _irq,
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uint32_t _reg_base_addr,
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uint32_t _fifo_base_addr,
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uint32_t _fifo_dbg_addr)
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{
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int retval = 0;
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uint32_t *reg_base =NULL;
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uint32_t *fifo_base =NULL;
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uint32_t *fifo_dbg =NULL;
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int i;
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IFX_DEBUGPL(DBG_CILV, "%s(%p,%d,0x%08X,0x%08X,0x%08X)\n", __func__,
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_core_if,
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_irq,
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_reg_base_addr,
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_fifo_base_addr,
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_fifo_dbg_addr);
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if( _core_if == NULL)
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{
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IFX_ERROR("%s() invalid _core_if\n", __func__);
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retval = -ENOMEM;
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goto fail;
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}
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//memset(_core_if, 0, sizeof(ifxusb_core_if_t));
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_core_if->irq=_irq;
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reg_base =ioremap_nocache(_reg_base_addr , IFXUSB_IOMEM_SIZE );
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fifo_base =ioremap_nocache(_fifo_base_addr, IFXUSB_FIFOMEM_SIZE);
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fifo_dbg =ioremap_nocache(_fifo_dbg_addr , IFXUSB_FIFODBG_SIZE);
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if( reg_base == NULL || fifo_base == NULL || fifo_dbg == NULL)
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{
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IFX_ERROR("%s() usb ioremap() failed\n", __func__);
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retval = -ENOMEM;
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goto fail;
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}
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_core_if->core_global_regs = (ifxusb_core_global_regs_t *)reg_base;
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/*
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* Attempt to ensure this device is really a IFXUSB Controller.
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* Read and verify the SNPSID register contents. The value should be
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* 0x45F42XXX
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*/
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{
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int32_t snpsid;
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snpsid = ifxusb_rreg(&_core_if->core_global_regs->gsnpsid);
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if ((snpsid & 0xFFFFF000) != 0x4F542000)
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{
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IFX_ERROR("%s() snpsid error(0x%08x) failed\n", __func__,snpsid);
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retval = -EINVAL;
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goto fail;
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}
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_core_if->snpsid=snpsid;
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}
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#ifdef __IS_HOST__
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_core_if->host_global_regs = (ifxusb_host_global_regs_t *)
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((uint32_t)reg_base + IFXUSB_HOST_GLOBAL_REG_OFFSET);
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_core_if->hprt0 = (uint32_t*)((uint32_t)reg_base + IFXUSB_HOST_PORT_REGS_OFFSET);
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for (i=0; i<MAX_EPS_CHANNELS; i++)
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{
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_core_if->hc_regs[i] = (ifxusb_hc_regs_t *)
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((uint32_t)reg_base + IFXUSB_HOST_CHAN_REGS_OFFSET +
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(i * IFXUSB_CHAN_REGS_OFFSET));
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IFX_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
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i, &_core_if->hc_regs[i]->hcchar);
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}
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#endif //__IS_HOST__
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#ifdef __IS_DEVICE__
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_core_if->dev_global_regs =
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(ifxusb_device_global_regs_t *)((uint32_t)reg_base + IFXUSB_DEV_GLOBAL_REG_OFFSET);
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for (i=0; i<MAX_EPS_CHANNELS; i++)
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{
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_core_if->in_ep_regs[i] = (ifxusb_dev_in_ep_regs_t *)
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((uint32_t)reg_base + IFXUSB_DEV_IN_EP_REG_OFFSET +
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(i * IFXUSB_EP_REG_OFFSET));
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_core_if->out_ep_regs[i] = (ifxusb_dev_out_ep_regs_t *)
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((uint32_t)reg_base + IFXUSB_DEV_OUT_EP_REG_OFFSET +
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(i * IFXUSB_EP_REG_OFFSET));
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IFX_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p/%p %p/0x%08X/0x%08X\n",
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i, &_core_if->in_ep_regs[i]->diepctl, _core_if->in_ep_regs[i],
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reg_base,IFXUSB_DEV_IN_EP_REG_OFFSET,(i * IFXUSB_EP_REG_OFFSET)
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);
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IFX_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p/%p %p/0x%08X/0x%08X\n",
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i, &_core_if->out_ep_regs[i]->doepctl, _core_if->out_ep_regs[i],
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reg_base,IFXUSB_DEV_OUT_EP_REG_OFFSET,(i * IFXUSB_EP_REG_OFFSET)
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);
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}
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#endif //__IS_DEVICE__
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/* Setting the FIFO and other Address. */
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for (i=0; i<MAX_EPS_CHANNELS; i++)
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{
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_core_if->data_fifo[i] = fifo_base + (i * IFXUSB_DATA_FIFO_SIZE);
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IFX_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n",
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i, (unsigned)_core_if->data_fifo[i]);
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}
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_core_if->data_fifo_dbg = fifo_dbg;
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_core_if->pcgcctl = (uint32_t*)(((uint32_t)reg_base) + IFXUSB_PCGCCTL_OFFSET);
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/*
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* Store the contents of the hardware configuration registers here for
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* easy access later.
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*/
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_core_if->hwcfg1.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg1);
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_core_if->hwcfg2.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg2);
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_core_if->hwcfg3.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg3);
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_core_if->hwcfg4.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg4);
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IFX_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",_core_if->hwcfg1.d32);
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IFX_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",_core_if->hwcfg2.d32);
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IFX_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",_core_if->hwcfg3.d32);
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IFX_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",_core_if->hwcfg4.d32);
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#ifdef __DED_FIFO__
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IFX_PRINT("Waiting for PHY Clock Lock!\n");
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while(!( ifxusb_rreg(&_core_if->core_global_regs->grxfsiz) & (1<<9)))
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{
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}
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IFX_PRINT("PHY Clock Locked!\n");
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//ifxusb_clean_spram(_core_if,128*1024/4);
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#endif
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/* Create new workqueue and init works */
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#if 0
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_core_if->wq_usb = create_singlethread_workqueue(_core_if->core_name);
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if(_core_if->wq_usb == 0)
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{
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IFX_DEBUGPL(DBG_CIL, "Creation of wq_usb failed\n");
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retval = -EINVAL;
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goto fail;
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}
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
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INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change, core_if);
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INIT_WORK(&core_if->w_wkp, w_wakeup_detected, core_if);
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#else
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INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change);
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INIT_DELAYED_WORK(&core_if->w_wkp, w_wakeup_detected);
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#endif
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#endif
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return 0;
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fail:
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if( reg_base != NULL) iounmap(reg_base );
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if( fifo_base != NULL) iounmap(fifo_base);
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if( fifo_dbg != NULL) iounmap(fifo_dbg );
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return retval;
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}
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/*!
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\brief This function free the mapped address in the IFXUSB CSR data structures.
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\param _core_if Pointer of core_if structure
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*/
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void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if)
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{
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/* Disable all interrupts */
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if( _core_if->core_global_regs != NULL)
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{
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ifxusb_mreg( &_core_if->core_global_regs->gahbcfg, 1, 0);
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ifxusb_wreg( &_core_if->core_global_regs->gintmsk, 0);
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}
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if( _core_if->core_global_regs != NULL) iounmap(_core_if->core_global_regs );
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if( _core_if->data_fifo[0] != NULL) iounmap(_core_if->data_fifo[0] );
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if( _core_if->data_fifo_dbg != NULL) iounmap(_core_if->data_fifo_dbg );
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#if 0
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if (_core_if->wq_usb)
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destroy_workqueue(_core_if->wq_usb);
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#endif
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memset(_core_if, 0, sizeof(ifxusb_core_if_t));
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}
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/*!
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\brief This function enbles the controller's Global Interrupt in the AHB Config register.
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\param _core_if Pointer of core_if structure
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*/
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void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if )
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{
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gahbcfg_data_t ahbcfg ={ .d32 = 0};
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ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
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ifxusb_mreg(&_core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
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}
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/*!
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\brief This function disables the controller's Global Interrupt in the AHB Config register.
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\param _core_if Pointer of core_if structure
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*/
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void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if )
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{
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gahbcfg_data_t ahbcfg ={ .d32 = 0};
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ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
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ifxusb_mreg(&_core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
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}
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/*!
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\brief Flush Tx and Rx FIFO.
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\param _core_if Pointer of core_if structure
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*/
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void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if )
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{
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ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
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volatile grstctl_t greset ={ .d32 = 0};
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int count = 0;
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IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__);
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greset.b.rxfflsh = 1;
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greset.b.txfflsh = 1;
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greset.b.txfnum = 0x10;
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greset.b.intknqflsh=1;
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greset.b.hstfrm=1;
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ifxusb_wreg( &global_regs->grstctl, greset.d32 );
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do
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{
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greset.d32 = ifxusb_rreg( &global_regs->grstctl);
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if (++count > 10000)
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{
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IFX_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, greset.d32);
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break;
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}
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} while (greset.b.rxfflsh == 1 || greset.b.txfflsh == 1);
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/* Wait for 3 PHY Clocks*/
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UDELAY(1);
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}
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/*!
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\brief Flush a Tx FIFO.
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\param _core_if Pointer of core_if structure
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\param _num Tx FIFO to flush. ( 0x10 for ALL TX FIFO )
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*/
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void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num )
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{
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ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
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volatile grstctl_t greset ={ .d32 = 0};
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int count = 0;
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IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", _num);
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greset.b.intknqflsh=1;
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greset.b.txfflsh = 1;
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greset.b.txfnum = _num;
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ifxusb_wreg( &global_regs->grstctl, greset.d32 );
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|
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do
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{
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greset.d32 = ifxusb_rreg( &global_regs->grstctl);
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if (++count > 10000&&(_num==0 ||_num==0x10))
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{
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IFX_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
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__func__, greset.d32,
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ifxusb_rreg( &global_regs->gnptxsts));
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break;
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}
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} while (greset.b.txfflsh == 1);
|
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/* Wait for 3 PHY Clocks*/
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UDELAY(1);
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}
|
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|
|
|
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/*!
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\brief Flush Rx FIFO.
|
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\param _core_if Pointer of core_if structure
|
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*/
|
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void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if )
|
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{
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ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
|
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volatile grstctl_t greset ={ .d32 = 0};
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int count = 0;
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|
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IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__);
|
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greset.b.rxfflsh = 1;
|
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ifxusb_wreg( &global_regs->grstctl, greset.d32 );
|
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|
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do
|
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{
|
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greset.d32 = ifxusb_rreg( &global_regs->grstctl);
|
|
if (++count > 10000)
|
|
{
|
|
IFX_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, greset.d32);
|
|
break;
|
|
}
|
|
} while (greset.b.rxfflsh == 1);
|
|
/* Wait for 3 PHY Clocks*/
|
|
UDELAY(1);
|
|
}
|
|
|
|
|
|
#define SOFT_RESET_DELAY 100
|
|
|
|
/*!
|
|
\brief Do a soft reset of the core. Be careful with this because it
|
|
resets all the internal state machines of the core.
|
|
\param _core_if Pointer of core_if structure
|
|
*/
|
|
int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if)
|
|
{
|
|
ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
|
|
volatile grstctl_t greset ={ .d32 = 0};
|
|
int count = 0;
|
|
|
|
IFX_DEBUGPL(DBG_CILV, "%s\n", __func__);
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
UDELAY(10);
|
|
greset.d32 = ifxusb_rreg( &global_regs->grstctl);
|
|
if (++count > 100000)
|
|
{
|
|
IFX_WARN("%s() HANG! AHB Idle GRSTCTL=%0x %x\n", __func__,
|
|
greset.d32, greset.b.ahbidle);
|
|
break;
|
|
}
|
|
} while (greset.b.ahbidle == 0);
|
|
|
|
UDELAY(1);
|
|
|
|
/* Core Soft Reset */
|
|
count = 0;
|
|
greset.b.csftrst = 1;
|
|
ifxusb_wreg( &global_regs->grstctl, greset.d32 );
|
|
|
|
#ifdef SOFT_RESET_DELAY
|
|
MDELAY(SOFT_RESET_DELAY);
|
|
#endif
|
|
|
|
do
|
|
{
|
|
UDELAY(10);
|
|
greset.d32 = ifxusb_rreg( &global_regs->grstctl);
|
|
if (++count > 100000)
|
|
{
|
|
IFX_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__, greset.d32);
|
|
return -1;
|
|
}
|
|
} while (greset.b.csftrst == 1);
|
|
|
|
#ifdef SOFT_RESET_DELAY
|
|
MDELAY(SOFT_RESET_DELAY);
|
|
#endif
|
|
|
|
|
|
#if defined(__IS_VR9__)
|
|
if(_core_if->core_no==0)
|
|
{
|
|
set_bit (4, VR9_RCU_USBRESET2);
|
|
MDELAY(50);
|
|
clear_bit (4, VR9_RCU_USBRESET2);
|
|
}
|
|
else
|
|
{
|
|
set_bit (5, VR9_RCU_USBRESET2);
|
|
MDELAY(50);
|
|
clear_bit (5, VR9_RCU_USBRESET2);
|
|
}
|
|
MDELAY(50);
|
|
#endif //defined(__IS_VR9__)
|
|
|
|
IFX_PRINT("USB core #%d soft-reset\n",_core_if->core_no);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*!
|
|
\brief Turn on the USB Core Power
|
|
\param _core_if Pointer of core_if structure
|
|
*/
|
|
void ifxusb_power_on (ifxusb_core_if_t *_core_if)
|
|
{
|
|
struct clk *clk0 = clk_get_sys("usb0", NULL);
|
|
struct clk *clk1 = clk_get_sys("usb1", NULL);
|
|
// set clock gating
|
|
IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
|
|
#if defined(__UEIP__)
|
|
|
|
#if defined(__IS_TWINPASS) || defined(__IS_DANUBE__)
|
|
set_bit (4, (volatile unsigned long *)DANUBE_CGU_IFCCR);
|
|
set_bit (5, (volatile unsigned long *)DANUBE_CGU_IFCCR);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
// clear_bit (4, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR);
|
|
clear_bit (5, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
set_bit (0, (volatile unsigned long *)AR9_CGU_IFCCR);
|
|
set_bit (1, (volatile unsigned long *)AR9_CGU_IFCCR);
|
|
#endif //defined(__IS_AR9__)
|
|
#if defined(__IS_VR9__)
|
|
// set_bit (0, (volatile unsigned long *)VR9_CGU_IFCCR);
|
|
// set_bit (1, (volatile unsigned long *)VR9_CGU_IFCCR);
|
|
#endif //defined(__IS_VR9__)
|
|
|
|
MDELAY(50);
|
|
|
|
// set power
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
|
|
USB_CTRL_PMU_SETUP(IFX_PMU_ENABLE);
|
|
//#if defined(__IS_TWINPASS__)
|
|
// ifxusb_enable_afe_oc();
|
|
//#endif
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__) || defined(__IS_VR9__)
|
|
if(_core_if->core_no==0)
|
|
clk_enable(clk0);
|
|
// USB0_CTRL_PMU_SETUP(IFX_PMU_ENABLE);
|
|
else
|
|
clk_enable(clk1);
|
|
// USB1_CTRL_PMU_SETUP(IFX_PMU_ENABLE);
|
|
#endif //defined(__IS_AR9__) || defined(__IS_VR9__)
|
|
|
|
if(_core_if->core_global_regs)
|
|
{
|
|
// PHY configurations.
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_AR9__)
|
|
#if defined(__IS_VR9__)
|
|
//ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_VR9__)
|
|
}
|
|
#else //defined(__UEIP__)
|
|
#if defined(__IS_TWINPASS) || defined(__IS_DANUBE__)
|
|
set_bit (4, (volatile unsigned long *)DANUBE_CGU_IFCCR);
|
|
set_bit (5, (volatile unsigned long *)DANUBE_CGU_IFCCR);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
// clear_bit (4, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR);
|
|
clear_bit (5, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
set_bit (0, (volatile unsigned long *)AMAZON_S_CGU_IFCCR);
|
|
set_bit (1, (volatile unsigned long *)AMAZON_S_CGU_IFCCR);
|
|
#endif //defined(__IS_AR9__)
|
|
|
|
MDELAY(50);
|
|
|
|
// set power
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
clear_bit (6, (volatile unsigned long *)DANUBE_PMU_PWDCR);//USB
|
|
clear_bit (9, (volatile unsigned long *)DANUBE_PMU_PWDCR);//DSL
|
|
clear_bit (15, (volatile unsigned long *)DANUBE_PMU_PWDCR);//AHB
|
|
#if defined(__IS_TWINPASS__)
|
|
ifxusb_enable_afe_oc();
|
|
#endif
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
clear_bit (6, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);
|
|
clear_bit (9, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);
|
|
clear_bit (15, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
if(_core_if->core_no==0)
|
|
clear_bit (6, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB
|
|
else
|
|
clear_bit (27, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB
|
|
clear_bit (9, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//DSL
|
|
clear_bit (15, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//AHB
|
|
#endif //defined(__IS_AR9__)
|
|
|
|
if(_core_if->core_global_regs)
|
|
{
|
|
// PHY configurations.
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_AR9__)
|
|
}
|
|
|
|
#endif //defined(__UEIP__)
|
|
}
|
|
|
|
/*!
|
|
\brief Turn off the USB Core Power
|
|
\param _core_if Pointer of core_if structure
|
|
*/
|
|
void ifxusb_power_off (ifxusb_core_if_t *_core_if)
|
|
{
|
|
struct clk *clk0 = clk_get_sys("usb0", NULL);
|
|
struct clk *clk1 = clk_get_sys("usb1", NULL);
|
|
ifxusb_phy_power_off (_core_if);
|
|
|
|
// set power
|
|
#if defined(__UEIP__)
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
|
|
USB_CTRL_PMU_SETUP(IFX_PMU_DISABLE);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__) || defined(__IS_VR9__)
|
|
if(_core_if->core_no==0)
|
|
clk_disable(clk0);
|
|
//USB0_CTRL_PMU_SETUP(IFX_PMU_DISABLE);
|
|
else
|
|
clk_disable(clk1);
|
|
//USB1_CTRL_PMU_SETUP(IFX_PMU_DISABLE);
|
|
#endif //defined(__IS_AR9__) || defined(__IS_VR9__)
|
|
#else //defined(__UEIP__)
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
set_bit (6, (volatile unsigned long *)DANUBE_PMU_PWDCR);//USB
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
set_bit (6, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);//USB
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
if(_core_if->core_no==0)
|
|
set_bit (6, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB
|
|
else
|
|
set_bit (27, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB
|
|
#endif //defined(__IS_AR9__)
|
|
#endif //defined(__UEIP__)
|
|
}
|
|
|
|
/*!
|
|
\brief Turn on the USB PHY Power
|
|
\param _core_if Pointer of core_if structure
|
|
*/
|
|
void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if)
|
|
{
|
|
struct clk *clk0 = clk_get_sys("usb0", NULL);
|
|
struct clk *clk1 = clk_get_sys("usb1", NULL);
|
|
#if defined(__UEIP__)
|
|
if(_core_if->core_global_regs)
|
|
{
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_AR9__)
|
|
#if defined(__IS_VR9_S__)
|
|
if(_core_if->core_no==0)
|
|
set_bit (0, VR9_RCU_USB_ANA_CFG1A);
|
|
else
|
|
set_bit (0, VR9_RCU_USB_ANA_CFG1B);
|
|
#endif //defined(__IS_VR9__)
|
|
}
|
|
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
|
|
USB_PHY_PMU_SETUP(IFX_PMU_ENABLE);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__) || defined(__IS_VR9__)
|
|
if(_core_if->core_no==0)
|
|
clk_enable(clk0);
|
|
//USB0_PHY_PMU_SETUP(IFX_PMU_ENABLE);
|
|
else
|
|
clk_enable(clk1);
|
|
//USB1_PHY_PMU_SETUP(IFX_PMU_ENABLE);
|
|
#endif //defined(__IS_AR9__) || defined(__IS_VR9__)
|
|
|
|
// PHY configurations.
|
|
if(_core_if->core_global_regs)
|
|
{
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_AR9__)
|
|
#if defined(__IS_VR9_S__)
|
|
if(_core_if->core_no==0)
|
|
set_bit (0, VR9_RCU_USB_ANA_CFG1A);
|
|
else
|
|
set_bit (0, VR9_RCU_USB_ANA_CFG1B);
|
|
#endif //defined(__IS_VR9__)
|
|
}
|
|
#else //defined(__UEIP__)
|
|
// PHY configurations.
|
|
if(_core_if->core_global_regs)
|
|
{
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_AR9__)
|
|
}
|
|
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
clear_bit (0, (volatile unsigned long *)DANUBE_PMU_PWDCR);//PHY
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
clear_bit (0, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
if(_core_if->core_no==0)
|
|
clear_bit (0, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY
|
|
else
|
|
clear_bit (26, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY
|
|
#endif //defined(__IS_AR9__)
|
|
|
|
// PHY configurations.
|
|
if(_core_if->core_global_regs)
|
|
{
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_AR9__)
|
|
}
|
|
#endif //defined(__UEIP__)
|
|
}
|
|
|
|
|
|
/*!
|
|
\brief Turn off the USB PHY Power
|
|
\param _core_if Pointer of core_if structure
|
|
*/
|
|
void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if)
|
|
{
|
|
struct clk *clk0 = clk_get_sys("usb0", NULL);
|
|
struct clk *clk1 = clk_get_sys("usb1", NULL);
|
|
#if defined(__UEIP__)
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
|
|
USB_PHY_PMU_SETUP(IFX_PMU_DISABLE);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__) || defined(__IS_VR9__)
|
|
if(_core_if->core_no==0)
|
|
clk_disable(clk0);
|
|
//USB0_PHY_PMU_SETUP(IFX_PMU_DISABLE);
|
|
else
|
|
clk_disable(clk1);
|
|
//USB1_PHY_PMU_SETUP(IFX_PMU_DISABLE);
|
|
#endif // defined(__IS_AR9__) || defined(__IS_VR9__)
|
|
#else //defined(__UEIP__)
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
set_bit (0, (volatile unsigned long *)DANUBE_PMU_PWDCR);//PHY
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
set_bit (0, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);//PHY
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
if(_core_if->core_no==0)
|
|
set_bit (0, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY
|
|
else
|
|
set_bit (26, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY
|
|
#endif //defined(__IS_AR9__)
|
|
#endif //defined(__UEIP__)
|
|
}
|
|
|
|
|
|
/*!
|
|
\brief Reset on the USB Core RCU
|
|
\param _core_if Pointer of core_if structure
|
|
*/
|
|
#if defined(__IS_VR9__)
|
|
int already_hard_reset=0;
|
|
#endif
|
|
void ifxusb_hard_reset(ifxusb_core_if_t *_core_if)
|
|
{
|
|
#if defined(__UEIP__)
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined (__IS_HOST__)
|
|
clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
|
|
#elif defined (__IS_DEVICE__)
|
|
set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
|
|
#endif
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
|
|
#if defined(__IS_AMAZON_SE__)
|
|
#if defined (__IS_HOST__)
|
|
clear_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
|
|
#elif defined (__IS_DEVICE__)
|
|
set_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
|
|
#endif
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
|
|
#if defined(__IS_AR9__)
|
|
if(_core_if->core_no==0)
|
|
{
|
|
#if defined (__IS_HOST__)
|
|
clear_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG);
|
|
#elif defined (__IS_DEVICE__)
|
|
set_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG);
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
#if defined (__IS_HOST__)
|
|
clear_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG);
|
|
#elif defined (__IS_DEVICE__)
|
|
set_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG);
|
|
#endif
|
|
}
|
|
#endif //defined(__IS_AR9__)
|
|
|
|
#if defined(__IS_VR9__)
|
|
if(_core_if->core_no==0)
|
|
{
|
|
#if defined (__IS_HOST__)
|
|
clear_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG);
|
|
#elif defined (__IS_DEVICE__)
|
|
set_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG);
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
#if defined (__IS_HOST__)
|
|
clear_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG);
|
|
#elif defined (__IS_DEVICE__)
|
|
set_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG);
|
|
#endif
|
|
}
|
|
#endif //defined(__IS_VR9__)
|
|
|
|
|
|
// set the HC's byte-order to big-endian
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
|
|
clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
set_bit (AMAZON_SE_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
|
|
clear_bit (AMAZON_SE_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
if(_core_if->core_no==0)
|
|
{
|
|
set_bit (AR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG);
|
|
clear_bit (AR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG);
|
|
}
|
|
else
|
|
{
|
|
set_bit (AR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG);
|
|
clear_bit (AR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG);
|
|
}
|
|
#endif //defined(__IS_AR9__)
|
|
#if defined(__IS_VR9__)
|
|
if(_core_if->core_no==0)
|
|
{
|
|
set_bit (VR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG);
|
|
clear_bit (VR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG);
|
|
}
|
|
else
|
|
{
|
|
set_bit (VR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG);
|
|
clear_bit (VR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG);
|
|
}
|
|
#endif //defined(__IS_VR9__)
|
|
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
set_bit (4, DANUBE_RCU_RESET);
|
|
MDELAY(500);
|
|
clear_bit (4, DANUBE_RCU_RESET);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
|
|
#if defined(__IS_AMAZON_SE__)
|
|
set_bit (4, AMAZON_SE_RCU_RESET);
|
|
MDELAY(500);
|
|
clear_bit (4, AMAZON_SE_RCU_RESET);
|
|
MDELAY(500);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
|
|
#if defined(__IS_AR9__)
|
|
if(_core_if->core_no==0)
|
|
{
|
|
set_bit (4, AR9_RCU_USBRESET);
|
|
MDELAY(500);
|
|
clear_bit (4, AR9_RCU_USBRESET);
|
|
}
|
|
else
|
|
{
|
|
set_bit (28, AR9_RCU_USBRESET);
|
|
MDELAY(500);
|
|
clear_bit (28, AR9_RCU_USBRESET);
|
|
}
|
|
MDELAY(500);
|
|
#endif //defined(__IS_AR9__)
|
|
#if defined(__IS_VR9__)
|
|
if(!already_hard_reset)
|
|
{
|
|
set_bit (4, VR9_RCU_USBRESET);
|
|
MDELAY(500);
|
|
clear_bit (4, VR9_RCU_USBRESET);
|
|
MDELAY(500);
|
|
already_hard_reset=1;
|
|
}
|
|
#endif //defined(__IS_VR9__)
|
|
|
|
#if defined(__IS_TWINPASS__)
|
|
ifxusb_enable_afe_oc();
|
|
#endif
|
|
|
|
if(_core_if->core_global_regs)
|
|
{
|
|
// PHY configurations.
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_AR9__)
|
|
#if defined(__IS_VR9__)
|
|
// ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_VR9__)
|
|
}
|
|
#else //defined(__UEIP__)
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined (__IS_HOST__)
|
|
clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
|
|
#elif defined (__IS_DEVICE__)
|
|
set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
|
|
#endif
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
|
|
#if defined(__IS_AMAZON_SE__)
|
|
#if defined (__IS_HOST__)
|
|
clear_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
|
|
#elif defined (__IS_DEVICE__)
|
|
set_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
|
|
#endif
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
|
|
#if defined(__IS_AR9__)
|
|
if(_core_if->core_no==0)
|
|
{
|
|
#if defined (__IS_HOST__)
|
|
clear_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG);
|
|
#elif defined (__IS_DEVICE__)
|
|
set_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG);
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
#if defined (__IS_HOST__)
|
|
clear_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG);
|
|
#elif defined (__IS_DEVICE__)
|
|
set_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG);
|
|
#endif
|
|
}
|
|
#endif //defined(__IS_AR9__)
|
|
|
|
// set the HC's byte-order to big-endian
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
|
|
clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
set_bit (AMAZON_SE_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
|
|
clear_bit (AMAZON_SE_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
if(_core_if->core_no==0)
|
|
{
|
|
set_bit (AMAZON_S_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG);
|
|
clear_bit (AMAZON_S_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG);
|
|
}
|
|
else
|
|
{
|
|
set_bit (AMAZON_S_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG);
|
|
clear_bit (AMAZON_S_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG);
|
|
}
|
|
#endif //defined(__IS_AR9__)
|
|
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
set_bit (4, DANUBE_RCU_RESET);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
set_bit (4, AMAZON_SE_RCU_RESET);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
if(_core_if->core_no==0)
|
|
{
|
|
set_bit (4, AMAZON_S_RCU_USBRESET);
|
|
}
|
|
else
|
|
{
|
|
set_bit (28, AMAZON_S_RCU_USBRESET);
|
|
}
|
|
#endif //defined(__IS_AR9__)
|
|
|
|
MDELAY(500);
|
|
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
clear_bit (4, DANUBE_RCU_RESET);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
clear_bit (4, AMAZON_SE_RCU_RESET);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
if(_core_if->core_no==0)
|
|
{
|
|
clear_bit (4, AMAZON_S_RCU_USBRESET);
|
|
}
|
|
else
|
|
{
|
|
clear_bit (28, AMAZON_S_RCU_USBRESET);
|
|
}
|
|
#endif //defined(__IS_AR9__)
|
|
|
|
MDELAY(500);
|
|
|
|
#if defined(__IS_TWINPASS__)
|
|
ifxusb_enable_afe_oc();
|
|
#endif
|
|
|
|
if(_core_if->core_global_regs)
|
|
{
|
|
// PHY configurations.
|
|
#if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
|
|
#if defined(__IS_AMAZON_SE__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_AMAZON_SE__)
|
|
#if defined(__IS_AR9__)
|
|
ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
|
|
#endif //defined(__IS_AR9__)
|
|
}
|
|
#endif //defined(__UEIP__)
|
|
}
|
|
|
|
#if defined(__GADGET_LED__) || defined(__HOST_LED__)
|
|
#if defined(__UEIP__)
|
|
static void *g_usb_led_trigger = NULL;
|
|
#endif
|
|
|
|
void ifxusb_led_init(ifxusb_core_if_t *_core_if)
|
|
{
|
|
#if defined(__UEIP__)
|
|
if ( !g_usb_led_trigger )
|
|
{
|
|
ifx_led_trigger_register("usb_link", &g_usb_led_trigger);
|
|
if ( g_usb_led_trigger != NULL )
|
|
{
|
|
struct ifx_led_trigger_attrib attrib = {0};
|
|
attrib.delay_on = 250;
|
|
attrib.delay_off = 250;
|
|
attrib.timeout = 2000;
|
|
attrib.def_value = 1;
|
|
attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE;
|
|
IFX_DEBUGP("Reg USB LED!!\n");
|
|
ifx_led_trigger_set_attrib(g_usb_led_trigger, &attrib);
|
|
}
|
|
}
|
|
#endif //defined(__UEIP__)
|
|
}
|
|
|
|
void ifxusb_led_free(ifxusb_core_if_t *_core_if)
|
|
{
|
|
#if defined(__UEIP__)
|
|
if ( g_usb_led_trigger )
|
|
{
|
|
ifx_led_trigger_deregister(g_usb_led_trigger);
|
|
g_usb_led_trigger = NULL;
|
|
}
|
|
#endif //defined(__UEIP__)
|
|
}
|
|
|
|
/*!
|
|
\brief Turn off the USB 5V VBus Power
|
|
\param _core_if Pointer of core_if structure
|
|
*/
|
|
void ifxusb_led(ifxusb_core_if_t *_core_if)
|
|
{
|
|
#if defined(__UEIP__)
|
|
if(g_usb_led_trigger)
|
|
ifx_led_trigger_activate(g_usb_led_trigger);
|
|
#else
|
|
#endif //defined(__UEIP__)
|
|
}
|
|
#endif // defined(__GADGET_LED__) || defined(__HOST_LED__)
|
|
|
|
|
|
|
|
#if defined(__IS_HOST__) && defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__)
|
|
/*!
|
|
\brief Turn on the OC Int
|
|
*/
|
|
void ifxusb_oc_int_on()
|
|
{
|
|
#if defined(__UEIP__)
|
|
#else
|
|
#if defined(__IS_TWINPASS__)
|
|
irq_enable(DANUBE_USB_OC_INT);
|
|
#endif
|
|
#endif //defined(__UEIP__)
|
|
}
|
|
/*!
|
|
\brief Turn off the OC Int
|
|
*/
|
|
void ifxusb_oc_int_off()
|
|
{
|
|
#if defined(__UEIP__)
|
|
#else
|
|
#if defined(__IS_TWINPASS__)
|
|
irq_disable(DANUBE_USB_OC_INT);
|
|
#endif
|
|
#endif //defined(__UEIP__)
|
|
}
|
|
#endif //defined(__IS_HOST__) && defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__)
|
|
|
|
/* internal routines for debugging */
|
|
void ifxusb_dump_msg(const u8 *buf, unsigned int length)
|
|
{
|
|
#ifdef __DEBUG__
|
|
unsigned int start, num, i;
|
|
char line[52], *p;
|
|
|
|
if (length >= 512)
|
|
return;
|
|
start = 0;
|
|
while (length > 0)
|
|
{
|
|
num = min(length, 16u);
|
|
p = line;
|
|
for (i = 0; i < num; ++i)
|
|
{
|
|
if (i == 8)
|
|
*p++ = ' ';
|
|
sprintf(p, " %02x", buf[i]);
|
|
p += 3;
|
|
}
|
|
*p = 0;
|
|
IFX_PRINT( "%6x: %s\n", start, line);
|
|
buf += num;
|
|
start += num;
|
|
length -= num;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/* This functions reads the SPRAM and prints its content */
|
|
void ifxusb_dump_spram(ifxusb_core_if_t *_core_if)
|
|
{
|
|
#ifdef __ENABLE_DUMP__
|
|
volatile uint8_t *addr, *start_addr, *end_addr;
|
|
uint32_t size;
|
|
IFX_PRINT("SPRAM Data:\n");
|
|
start_addr = (void*)_core_if->core_global_regs;
|
|
IFX_PRINT("Base Address: 0x%8X\n", (uint32_t)start_addr);
|
|
|
|
start_addr = (void*)_core_if->data_fifo_dbg;
|
|
IFX_PRINT("Starting Address: 0x%8X\n", (uint32_t)start_addr);
|
|
|
|
size=_core_if->hwcfg3.b.dfifo_depth;
|
|
size<<=2;
|
|
size+=0x200;
|
|
size&=0x0003FFFC;
|
|
|
|
end_addr = (void*)_core_if->data_fifo_dbg;
|
|
end_addr += size;
|
|
|
|
for(addr = start_addr; addr < end_addr; addr+=16)
|
|
{
|
|
IFX_PRINT("0x%8X:\t%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", (uint32_t)addr,
|
|
addr[ 0], addr[ 1], addr[ 2], addr[ 3],
|
|
addr[ 4], addr[ 5], addr[ 6], addr[ 7],
|
|
addr[ 8], addr[ 9], addr[10], addr[11],
|
|
addr[12], addr[13], addr[14], addr[15]
|
|
);
|
|
}
|
|
return;
|
|
#endif //__ENABLE_DUMP__
|
|
}
|
|
|
|
|
|
|
|
|
|
/* This function reads the core global registers and prints them */
|
|
void ifxusb_dump_registers(ifxusb_core_if_t *_core_if)
|
|
{
|
|
#ifdef __ENABLE_DUMP__
|
|
int i;
|
|
volatile uint32_t *addr;
|
|
#ifdef __IS_DEVICE__
|
|
volatile uint32_t *addri,*addro;
|
|
#endif
|
|
|
|
IFX_PRINT("Core Global Registers\n");
|
|
addr=&_core_if->core_global_regs->gotgctl;
|
|
IFX_PRINT("GOTGCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->core_global_regs->gotgint;
|
|
IFX_PRINT("GOTGINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->core_global_regs->gahbcfg;
|
|
IFX_PRINT("GAHBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->core_global_regs->gusbcfg;
|
|
IFX_PRINT("GUSBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->core_global_regs->grstctl;
|
|
IFX_PRINT("GRSTCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->core_global_regs->gintsts;
|
|
IFX_PRINT("GINTSTS @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->core_global_regs->gintmsk;
|
|
IFX_PRINT("GINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->core_global_regs->gi2cctl;
|
|
IFX_PRINT("GI2CCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->core_global_regs->gpvndctl;
|
|
IFX_PRINT("GPVNDCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->core_global_regs->ggpio;
|
|
IFX_PRINT("GGPIO @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->core_global_regs->guid;
|
|
IFX_PRINT("GUID @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->core_global_regs->gsnpsid;
|
|
IFX_PRINT("GSNPSID @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->core_global_regs->ghwcfg1;
|
|
IFX_PRINT("GHWCFG1 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->core_global_regs->ghwcfg2;
|
|
IFX_PRINT("GHWCFG2 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->core_global_regs->ghwcfg3;
|
|
IFX_PRINT("GHWCFG3 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->core_global_regs->ghwcfg4;
|
|
IFX_PRINT("GHWCFG4 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
|
|
addr=_core_if->pcgcctl;
|
|
IFX_PRINT("PCGCCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
|
|
addr=&_core_if->core_global_regs->grxfsiz;
|
|
IFX_PRINT("GRXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
|
|
#ifdef __IS_HOST__
|
|
addr=&_core_if->core_global_regs->gnptxfsiz;
|
|
IFX_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->core_global_regs->hptxfsiz;
|
|
IFX_PRINT("HPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
#endif //__IS_HOST__
|
|
|
|
#ifdef __IS_DEVICE__
|
|
#ifdef __DED_FIFO__
|
|
addr=&_core_if->core_global_regs->gnptxfsiz;
|
|
IFX_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
for (i=0; i<= _core_if->hwcfg4.b.num_in_eps; i++)
|
|
{
|
|
addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i];
|
|
IFX_PRINT("DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,ifxusb_rreg(addr));
|
|
}
|
|
#else
|
|
addr=&_core_if->core_global_regs->gnptxfsiz;
|
|
IFX_PRINT("TXFSIZ[00] @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
for (i=0; i< _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
|
|
{
|
|
addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i];
|
|
IFX_PRINT("TXFSIZ[%02d] @0x%08X : 0x%08X\n",i+1,(uint32_t)addr,ifxusb_rreg(addr));
|
|
}
|
|
#endif
|
|
#endif //__IS_DEVICE__
|
|
|
|
#ifdef __IS_HOST__
|
|
IFX_PRINT("Host Global Registers\n");
|
|
addr=&_core_if->host_global_regs->hcfg;
|
|
IFX_PRINT("HCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->host_global_regs->hfir;
|
|
IFX_PRINT("HFIR @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->host_global_regs->hfnum;
|
|
IFX_PRINT("HFNUM @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->host_global_regs->hptxsts;
|
|
IFX_PRINT("HPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->host_global_regs->haint;
|
|
IFX_PRINT("HAINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->host_global_regs->haintmsk;
|
|
IFX_PRINT("HAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr= _core_if->hprt0;
|
|
IFX_PRINT("HPRT0 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
|
|
for (i=0; i<MAX_EPS_CHANNELS; i++)
|
|
{
|
|
IFX_PRINT("Host Channel %d Specific Registers\n", i);
|
|
addr=&_core_if->hc_regs[i]->hcchar;
|
|
IFX_PRINT("HCCHAR @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->hc_regs[i]->hcsplt;
|
|
IFX_PRINT("HCSPLT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->hc_regs[i]->hcint;
|
|
IFX_PRINT("HCINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->hc_regs[i]->hcintmsk;
|
|
IFX_PRINT("HCINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->hc_regs[i]->hctsiz;
|
|
IFX_PRINT("HCTSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->hc_regs[i]->hcdma;
|
|
IFX_PRINT("HCDMA @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
}
|
|
#endif //__IS_HOST__
|
|
|
|
#ifdef __IS_DEVICE__
|
|
IFX_PRINT("Device Global Registers\n");
|
|
addr=&_core_if->dev_global_regs->dcfg;
|
|
IFX_PRINT("DCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->dev_global_regs->dctl;
|
|
IFX_PRINT("DCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->dev_global_regs->dsts;
|
|
IFX_PRINT("DSTS @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->dev_global_regs->diepmsk;
|
|
IFX_PRINT("DIEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->dev_global_regs->doepmsk;
|
|
IFX_PRINT("DOEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->dev_global_regs->daintmsk;
|
|
IFX_PRINT("DAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->dev_global_regs->daint;
|
|
IFX_PRINT("DAINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->dev_global_regs->dvbusdis;
|
|
IFX_PRINT("DVBUSID @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
addr=&_core_if->dev_global_regs->dvbuspulse;
|
|
IFX_PRINT("DVBUSPULSE @0x%08X : 0x%08X\n", (uint32_t)addr,ifxusb_rreg(addr));
|
|
|
|
addr=&_core_if->dev_global_regs->dtknqr1;
|
|
IFX_PRINT("DTKNQR1 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
|
|
if (_core_if->hwcfg2.b.dev_token_q_depth > 6) {
|
|
addr=&_core_if->dev_global_regs->dtknqr2;
|
|
IFX_PRINT("DTKNQR2 @0x%08X : 0x%08X\n", (uint32_t)addr,ifxusb_rreg(addr));
|
|
}
|
|
|
|
if (_core_if->hwcfg2.b.dev_token_q_depth > 14)
|
|
{
|
|
addr=&_core_if->dev_global_regs->dtknqr3_dthrctl;
|
|
IFX_PRINT("DTKNQR3_DTHRCTL @0x%08X : 0x%08X\n", (uint32_t)addr, ifxusb_rreg(addr));
|
|
}
|
|
|
|
if (_core_if->hwcfg2.b.dev_token_q_depth > 22)
|
|
{
|
|
addr=&_core_if->dev_global_regs->dtknqr4_fifoemptymsk;
|
|
IFX_PRINT("DTKNQR4 @0x%08X : 0x%08X\n", (uint32_t)addr, ifxusb_rreg(addr));
|
|
}
|
|
|
|
//for (i=0; i<= MAX_EPS_CHANNELS; i++)
|
|
//for (i=0; i<= 10; i++)
|
|
for (i=0; i<= 3; i++)
|
|
{
|
|
IFX_PRINT("Device EP %d Registers\n", i);
|
|
addri=&_core_if->in_ep_regs[i]->diepctl;addro=&_core_if->out_ep_regs[i]->doepctl;
|
|
IFX_PRINT("DEPCTL I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro));
|
|
addro=&_core_if->out_ep_regs[i]->doepfn;
|
|
IFX_PRINT("DEPFN I: O: 0x%08X\n",ifxusb_rreg(addro));
|
|
addri=&_core_if->in_ep_regs[i]->diepint;addro=&_core_if->out_ep_regs[i]->doepint;
|
|
IFX_PRINT("DEPINT I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro));
|
|
addri=&_core_if->in_ep_regs[i]->dieptsiz;addro=&_core_if->out_ep_regs[i]->doeptsiz;
|
|
IFX_PRINT("DETSIZ I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro));
|
|
addri=&_core_if->in_ep_regs[i]->diepdma;addro=&_core_if->out_ep_regs[i]->doepdma;
|
|
IFX_PRINT("DEPDMA I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro));
|
|
addri=&_core_if->in_ep_regs[i]->dtxfsts;
|
|
IFX_PRINT("DTXFSTS I: 0x%08X\n",ifxusb_rreg(addri) );
|
|
addri=&_core_if->in_ep_regs[i]->diepdmab;addro=&_core_if->out_ep_regs[i]->doepdmab;
|
|
IFX_PRINT("DEPDMAB I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro));
|
|
}
|
|
#endif //__IS_DEVICE__
|
|
#endif //__ENABLE_DUMP__
|
|
}
|
|
|
|
void ifxusb_clean_spram(ifxusb_core_if_t *_core_if,uint32_t dwords)
|
|
{
|
|
volatile uint32_t *addr1,*addr2, *start_addr, *end_addr;
|
|
|
|
if(!dwords)
|
|
return;
|
|
|
|
start_addr = (uint32_t *)_core_if->data_fifo_dbg;
|
|
|
|
end_addr = (uint32_t *)_core_if->data_fifo_dbg;
|
|
end_addr += dwords;
|
|
|
|
IFX_PRINT("Clearning SPRAM: 0x%8X-0x%8X\n", (uint32_t)start_addr,(uint32_t)end_addr);
|
|
for(addr1 = start_addr; addr1 < end_addr; addr1+=4)
|
|
{
|
|
for(addr2 = addr1; addr2 < addr1+4; addr2++)
|
|
*addr2=0x00000000;
|
|
}
|
|
IFX_PRINT("Clearning SPRAM: 0x%8X-0x%8X Done\n", (uint32_t)start_addr,(uint32_t)end_addr);
|
|
return;
|
|
}
|
|
|