3af779eb17
This is a backport of the patches accepted to the Linux mainline related to mvebu SoC (Armada XP and Armada 370) between Linux v3.11, and Linux v3.12. This work mainly covers: * Ground work for sharing the pxa nand driver(drivers/mtd/nand/pxa3xx_nand.c) between the PXA family,and the Armada family. * Further updates to the mvebu MBus. * Work and ground work for enabling MSI on the Armada family. * some phy / mdio bus initialization related work. * Device tree binding documentation update. Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com> CC: Luka Perkov <luka@openwrt.org> SVN-Revision: 39565
64 lines
2.9 KiB
Diff
64 lines
2.9 KiB
Diff
From 4aa571afd29f88898ef2fb954effcf53fec3264e Mon Sep 17 00:00:00 2001
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From: Huang Shijie <b32955@freescale.com>
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Date: Fri, 17 May 2013 11:17:25 +0800
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Subject: [PATCH 090/203] mtd: add datasheet's ECC information to nand_chip{}
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1.) Why add the ECC information to the nand_chip{} ?
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Each nand chip has its requirement for the ECC correctability, such as
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"4bit ECC for each 512Byte" or "40bit ECC for each 1024Byte".
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This ECC info is very important to the nand controller, such as gpmi.
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Take the Micron MT29F64G08CBABA for example, its geometry is
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8KiB page size, 744 bytes oob size and it requires 40bit ECC per 1KiB.
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If we do not provide the ECC info to the gpmi nand driver, it has to
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calculate the ECC correctability itself. The gpmi driver will gets the 56bit
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ECC for per 1KiB which is beyond its BCH's 40bit ecc capibility.
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The gpmi will quits in this case. But in actually, the gpmi can supports
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this nand chip if it can get the right ECC info.
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2.) about the new fields.
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The @ecc_strength_ds stands for the ecc bits needed within the @ecc_step_ds.
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The two fields should be set from the nand chip's datasheets.
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For example:
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"4bit ECC for each 512Byte" could be:
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@ecc_strength_ds = 4, @ecc_step_ds = 512.
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"40bit ECC for each 1024Byte" could be:
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@ecc_strength_ds = 40, @ecc_step_ds = 1024.
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3.) Why do not re-use the @strength and @size in the nand_ecc_ctrl{}?
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The @strength and @size in nand_ecc_ctrl{} is used by the nand controller
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driver, while the @ecc_strength_ds and @ecc_step_ds are get from the datasheet.
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Signed-off-by: Huang Shijie <b32955@freescale.com>
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Reviewed-and-tested-by: Brian Norris <computersforpeace@gmail.com>
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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---
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include/linux/mtd/nand.h | 8 ++++++++
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1 file changed, 8 insertions(+)
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--- a/include/linux/mtd/nand.h
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+++ b/include/linux/mtd/nand.h
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@@ -434,6 +434,12 @@ struct nand_buffers {
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* bad block marker position; i.e., BBM == 11110111b is
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* not bad when badblockbits == 7
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* @cellinfo: [INTERN] MLC/multichip data from chip ident
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+ * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
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+ * Minimum amount of bit errors per @ecc_step_ds guaranteed
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+ * to be correctable. If unknown, set to zero.
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+ * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
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+ * also from the datasheet. It is the recommended ECC step
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+ * size, if known; if unknown, set to zero.
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* @numchips: [INTERN] number of physical chips
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* @chipsize: [INTERN] the size of one chip for multichip arrays
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* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
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@@ -510,6 +516,8 @@ struct nand_chip {
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unsigned int pagebuf_bitflips;
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int subpagesize;
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uint8_t cellinfo;
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+ uint16_t ecc_strength_ds;
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+ uint16_t ecc_step_ds;
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int badblockpos;
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int badblockbits;
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