From fb143ba7f7cd215bc2fc34a478c4c0b6dc56e537 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens <hauke@hauke-m.de> Date: Mon, 6 Jan 2014 14:51:59 +0100 Subject: [PATCH] MIPS: BCM47XX: fix position of cpu_wait disabling The disabling of cpu_wait was done too early, before the detection was done. This moves the code to a position where it actually works. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Rafa? Mi?ecki <zajec5@gmail.com> --- arch/mips/bcm47xx/setup.c | 34 +++++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 9 deletions(-) --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -37,6 +37,7 @@ #include <asm/prom.h> #include <asm/reboot.h> #include <asm/time.h> +#include <asm/idle.h> #include <bcm47xx.h> #include <bcm47xx_nvram.h> #include <bcm47xx_board.h> @@ -231,6 +232,31 @@ void __init plat_mem_setup(void) mips_set_machine_name(bcm47xx_board_get_name()); } +static int __init bcm47xx_cpu_fixes(void) +{ + switch (bcm47xx_bus_type) { +#ifdef CONFIG_BCM47XX_SSB + case BCM47XX_BUS_TYPE_SSB: + /* Nothing to do */ + break; +#endif +#ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + /* The BCM4706 has a problem with the CPU wait instruction. + * When r4k_wait or r4k_wait_irqoff is used will just hang and + * not return from a msleep(). Removing the cpu_wait + * functionality is a workaround for this problem. The BCM4716 + * does not have this problem. + */ + if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706) + cpu_wait = NULL; + break; +#endif + } + return 0; +} +arch_initcall(bcm47xx_cpu_fixes); + static int __init bcm47xx_register_bus_complete(void) { switch (bcm47xx_bus_type) {