--- /dev/null +++ b/arch/mips/include/asm/mach-ath79/mangle-port.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org> + * + * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h + * Copyright (C) 2003, 2004 Ralf Baechle + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H +#define __ASM_MACH_ATH79_MANGLE_PORT_H + +#ifdef CONFIG_PCI +extern unsigned long (ath79_pci_swizzle_b)(unsigned long port); +extern unsigned long (ath79_pci_swizzle_w)(unsigned long port); +#else +#define ath79_pci_swizzle_b(port) (port) +#define ath79_pci_swizzle_w(port) (port) +#endif + +#define __swizzle_addr_b(port) ath79_pci_swizzle_b(port) +#define __swizzle_addr_w(port) ath79_pci_swizzle_w(port) +#define __swizzle_addr_l(port) (port) +#define __swizzle_addr_q(port) (port) + +# define ioswabb(a, x) (x) +# define __mem_ioswabb(a, x) (x) +# define ioswabw(a, x) (x) +# define __mem_ioswabw(a, x) cpu_to_le16(x) +# define ioswabl(a, x) (x) +# define __mem_ioswabl(a, x) cpu_to_le32(x) +# define ioswabq(a, x) (x) +# define __mem_ioswabq(a, x) cpu_to_le64(x) + +#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */ --- a/arch/mips/ath79/pci.c +++ b/arch/mips/ath79/pci.c @@ -13,6 +13,7 @@ */ #include <linux/init.h> +#include <linux/export.h> #include <linux/pci.h> #include <linux/resource.h> #include <linux/platform_device.h> @@ -25,6 +26,9 @@ static int (*ath79_pci_plat_dev_init)(st static const struct ath79_pci_irq *ath79_pci_irq_map __initdata; static unsigned ath79_pci_nr_irqs __initdata; +static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port); +static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port); + static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { { .slot = 17, @@ -202,12 +206,50 @@ ath79_register_pci_ar724x(int id, return pdev; } +static inline bool ar71xx_is_pci_addr(unsigned long port) +{ + unsigned long phys = CPHYSADDR(port); + + return (phys >= AR71XX_PCI_MEM_BASE && + phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE); +} + +static unsigned long ar71xx_pci_swizzle_b(unsigned long port) +{ + return ar71xx_is_pci_addr(port) ? port ^ 3 : port; +} + +static unsigned long ar71xx_pci_swizzle_w(unsigned long port) +{ + return ar71xx_is_pci_addr(port) ? port ^ 2 : port; +} + +unsigned long ath79_pci_swizzle_b(unsigned long port) +{ + if (__ath79_pci_swizzle_b) + return __ath79_pci_swizzle_b(port); + + return port; +} +EXPORT_SYMBOL(ath79_pci_swizzle_b); + +unsigned long ath79_pci_swizzle_w(unsigned long port) +{ + if (__ath79_pci_swizzle_w) + return __ath79_pci_swizzle_w(port); + + return port; +} +EXPORT_SYMBOL(ath79_pci_swizzle_w); + int __init ath79_register_pci(void) { struct platform_device *pdev = NULL; if (soc_is_ar71xx()) { pdev = ath79_register_pci_ar71xx(); + __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b; + __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w; } else if (soc_is_ar724x()) { pdev = ath79_register_pci_ar724x(-1, AR724X_PCI_CFG_BASE,