Commit graph

6 commits

Author SHA1 Message Date
Mathias Kresin
f8a6987cd1 lantiq: make dts files and kernel config kernel version specific
Move the devicetree source files to a kernel specific directory in
preparation of adding kernel 4.14 support.

Rename the subtarget kernel config files to match a specific kernel
version.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2018-02-20 19:25:17 +01:00
Mathias Kresin
627a28eb09 lantiq: rename gphy firmware
Rename the gphy firmware to match the name requested by kernel 4.14 and
update the devicetree source files to use the new name.

Update the u-boot lantiq Makefile to be compatible with the new names as
well.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2018-02-20 19:25:17 +01:00
Mathias Kresin
26dc65b126 lantiq: remove the former board name from device tree model
Remove the former used board name from the device model property and
use the model name as it is.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2017-12-16 23:33:56 +01:00
Mathias Kresin
7bab49fd7a lantiq: add compatible strings to dts files
The compatible string is mandetory for devicetree source file.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2017-12-16 23:33:56 +01:00
Mathias Kresin
259fc1e778 lantiq: show xdsl line init status on shared dsl/internet led
On boards which don't have a distinct internet and dsl led, use the
shared LED to indicate the xdsl line state and any traffic that is
send/received via the netdev. This traffic doesn't necessarily need to
be internet traffic.

Rename the shared LED of existing configs to "dsl", to match the new
defaults. The configuration of the to be renamed LED is identical with
the new defaults.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2017-06-17 15:38:18 +02:00
Alex Maclean
6254a2028c lantiq: add support for the Alpha ASL56026
The ASL56026 is a VDSL2 router with dual 100mbit ethernet,
also known as the ECI B-FOCuS V-2FUb/I.

CPU: Lantiq XRX268 v1.1 at 333MHz
Modem: Lantiq VRX208
RAM: 32MiB DDR2 at 167MHz
Flash: 8MiB NOR, Spansion S29GL064N90TF04

UART is at JP1:
Pin 1 TX
Pin 2 GND
Pin 3 +3.3V
Pin 4 NC
Pin 5 RX

Boot selection pins are exposed via several resistor jumpers:
boot_sel0 is at J15, on the rear of the board. Default is high.
boot_sel1 is at J3, next to the flash - it is also the flash CE# pin. Default is low.
boot_sel2 is at J12, directly below the SoC. Default is low.
boot_sel3 is at J16, on the rear of the board. Default is low.

The boot_sel pins should never be shorted, the jumper must be moved or
a lower value resistor used to change the pull (existing resistors are 4k7, 1k should work)

To install with the stock bootloader you must break the built in image selection process
which uses at least the following vars: f_upgrade_addr, f_upgrade2_addr, loadaddr, kernel_addr, activeregion, committedregion
This is done by setting loadaddr and both f_upgrade_addr vars to the same address:

	VR9 # setenv loadaddr 0xB0040000
	VR9 # setenv f_upgrade_addr 0xB0040000
	VR9 # setenv f_upgrade2_addr 0xB0040000
	VR9 # saveenv

Then flash the firmware image:

	VR9 # tftpboot 0x81000000 lede-lantiq-xrx200-ASL56026-squashfs-sysupgrade.bin
	VR9 # erase B0040000 +${filesize}
	VR9 # cp.b 0x81000000 0xB0040000 ${filesize}

Signed-off-by: Alex Maclean <monkeh@monkeh.net>
2017-03-08 19:06:04 +01:00