As explained earlier, using SWITCH_TYPE_LINK gives more flexibility,
it doesn't require e.g. string parsing to read some data.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 47999
So far we were sending link data as a string. It got some drawbacks:
1) Didn't allow writing clean user space apps reading link state. It was
needed to do some screen scraping.
2) Forced whole PORT_LINK communication to be string based. Adding
support for *setting* port link required passing string and parting
it in the kernel space.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 47997
Previously switching to non-existing device (interface) could result in
leaving LED on.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 47990
We may just delete timer on every trigger update and then start it again
if needed. This will let us avoid both: races and locking in frequently
called timer callback.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 47987
Read/write lock was adding useless complexity, there wasn't any real
gain in case of this driver.
Also switch to _bh variants to avoid deadlocks.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 47986
All supported kernels require patching ledtrig-netdev in the same way,
so it's safe to just move these changes to the base version of this
driver. We needed these patches for some old kernels 2.6.36 and 3.11.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 47962
In r45970 the MAC swap handling was made opt-in, however some boards
have been forgotten during the conversion. Since the reference design
uses this MAC swapping, and pretty much all known boards using this chip
seem to do so too, enabling the swapping is a more reasonable default
than leaving it disabled.
Change the code to still allow boards to opt-out of this.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 47956
Kernel 3.14 added aditional genphy_soft_reset phy reset to phy_init_hw in drivers/net/phy/phy_device.c
Since adm6996 does in driver soft reset and doesn't use BMCR_RESET for soft reset
add dummy soft_reset callback to adm6996 driver, like it is done in ar8216.
This fixes ticket #20147
Signed-off-by: Andrej Vlasic <andrej.vlasic0@gmail.com>
SVN-Revision: 47272
The previous "link" and "status" functions were non-standard,
and thus less useful for parsing.
Signed-off-by: Claudio Leite <leitec@staticky.com>
SVN-Revision: 46864
This also clears any bootloader-set FDB defaults. This had
caused issues creating port-based VLANs when mappings
overlapped previous VLANs. Packets destined to a port
not in the default port group flooded all ports.
Tested on a 88E6171 (Linksys EA4500) and 88E6172 ('1900AC)
Signed-off-by: Claudio Leite <leitec@staticky.com>
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
SVN-Revision: 46699
no-op since 2.6.35
removed in Kernel 4.1
see https://lwn.net/Articles/380931/
Signed-off-by: Dirk Neukirchen <dirkneukirchen@web.de>
SVN-Revision: 46671
In addition to the update this also fixes compile problems with kernel 4.1.
This closes#20323.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 46609
If a link goes down, don't flush the complete ARL table.
Only flush the entries for the respective port.
Don't touch ARL table if a link goes up.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 46381
Adds functions for flushing ARL table entries per port.
Successfully tested on AR8327. Implementation for AR8216/AR8236/AR8316
is based on the AR8236 datasheet and assumes that the three chips
share a common ATU register layout.
Compile-tested only for AR8216/AR8236/AR8316.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 46380
Adds the chip-specific part of reading ARL table for AR8216/AR8236/AR8316.
It's based on the AR8236 datasheet and compile-tested only as I couldn't
find datasheets for AR8216/AR8316 and don't own devices with these chips.
The existing ar8216_atu_flush implementation was used for all three
chip types, therefore I guess they share a common ATU register layout.
More testing would be appreciated.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 46379
To improve reproducibility, prevent the inclusion of timestamps
in the gzip header.
Signed-off-by: Reiner Herrmann <reiner@reiner-h.de>
SVN-Revision: 46361
The position of the nvram header file on brcm47xx changed with kernel
version 4.1.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 46170
On two tested devices: Netgear R6250 (BCM53011 rev 2) and Luxul XWC-1000
(BCM53011 rev 3) it was possible to use port 7 and eth1 (instead of port
5 and eth0). It seems BCM53011 just like BCM53012 has 8 ports and
usually 3 of them are connected to the SoC.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 46104
AR8337 supports a configuration bit to swap MAC0 and MAC6.
Currently this is set in general if an AR8337 is detected and causes
issues with devices using an AR8334 (internally an AR8337, just
less chip pins).
And it might even cause issues with AR8337-based devices with
different board designs.
Swapping the MAC's however isn't needed for AR8337 in general.
It's just needed in case of certain board designs (affected devices
seem to be based on Atheros reference board AP135/136-010).
Therefore this configuration bit should be moved to platform data.
The patch includes the needed changes to the device initialization
code of affected devices. Hopefully I didn't miss any ..
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 45970
On device reset the sizes for the vlan and port tables were wrongly
calculated based on the pointer size instead of the struct size. This
causes buffer overruns on 64 bit targets, resulting in panics.
Fix this by dereferencing the pointers.
Reported-by: Fedor Konstantinov <blmink@mink.su>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45938
At least on my b53 chip, the mask is 3 bits wide, and because
of this some STP states are not set properly and discarded when read.
Maybe for some other chips it makes sense to have just 2 bits width,
but I don't have other versions around to test/validate.
If that's the case then maybe we could add another STP state mask.
Signed-off-by: Alexandru Ardelean <ardeleanalex@gmail.com>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45937
This chipset has at least 8 usable ports, e.g. Netgear R8000 has ports
5, 7 and 8 connected to Ethernet interfaces:
vlan1ports=0 1 2 3 5 7 8*
vlan2ports=4 8u
Port 6 seems to be always disabled.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45676
On BCM5301X there are two different cases to handle: CPU port 8 vs. any
other one. Support for CPU port 8 was already partially implemented but
it lacked setting some extra bit for 2G speed. It also will need to be
extended to implement "SMP dual core 3 GMAC setup". That's the reason
for handling it in separated code block.
This patch also adds overriding CPU port state for port other than 8. It
requires using recently defined GMII_PORT registers.
It was tested for regressions on BCM53011 revs 2 & 3. It was also
confirmed to fix switch on some internal Broadcom board.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45402
* properly enclose macro arguments in paranthesis on use
* remove trailing white space
* convert C99 // comments
* add missing blank lines after declaration
* remove braces from single statement blocks
* split lines > 80 chars (except for one)
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45356
Use the latest version of the yaffs code. Fetched from the
yaffs2 git tree and it is based on the following commit:
commit 7e5cf0fa1b694f835cdc184a8395b229fa29f9ae
Author: Charles Manning <cdhmanning@gmail.com>
Date: Thu Aug 7 11:25:05 2014 +1200
yaffs-direct: Basic tests. Add lpthread flag for background gc support
Signed-off-by: Charles Manning <cdhmanning@gmail.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 45188
If this option is enabled, the FIT image format will be detected and
split by the mtdsplit code. Detection is based upon the FDT magic, which
will trigger the parsing and detection of the rootfs, ending-up in the
creation of the 2 new partitions.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 44792
It will now actually enable the mib counters instead of enabling rx/tx for
the first switch port.
Reported-by: Daniel Gonzalez <dgcbueu@gmail.com>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 44788
For bcm63xx integrated switches, broadcom changed the data endianess
to match the system endianess. But this only applies to within one word,
which causes 48/64 bit values to be still split into their "litte endian"
groups.
E.g. 48 bit values (with 5 being the most significant byte) aligned
0x00 ..01 or 0123
0x04 2345 45..
will become
0x00 ..10 resp. 3210
0x04 5432 54..
Likewise for 64 bit values.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 44568
We shouldn't read data directly into the header struct, as some devices
(e.g. Edimax) need more bytes due to some extra header.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 44414
Some devices have uImage headers after some extra headers (e.g. Edimax
devices). To support such cases our verify callback function should be
allowed to return header offset, not just a boolean value.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 44412
drivers/net/phy/adm6996.c:881:5: warning: format '%lu' expects argument of type 'long unsigned int', but argument 5 has type 'u32' [-Wformat=]
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 44333
The board is already supported by OpenWrt. WNR1000v2/WNR1000v2-VC are
pretty much the same as WNR2000v3/WNR612v2, therefore the same
initialization code and flash layout is used.
Signed-off-by: Ștefan Rusu <saltwaterc@gmail.com>
Tested-by: Douglas Fraser <1dsfraser@gmail.com>
SVN-Revision: 44221
Add global read-only swconfig attribute "arl_table" to display the
address resolution table.
So far the chip-specific part is implemented for AR8327/AR8337 only
as I don't have the datasheets for the other AR8XXX chips.
Successfully tested on TL-WDR4300 (AR8327rev2)
and TL-WDR4900 (AR8327rev4).
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 44104
Until a few years ago the page switch wait time was set to msleep(1)
what was changed to usleep_range(1000, 2000) later.
I can not imagine that a low-level operation like switching page
on register level takes so much time.
Most likely the value of 1ms was initially set to check whether
it fixes an issue and then remained w/o further checking whether
also a smaller value would be sufficient.
Now the wait time is set to 5us and I successfully tested this on
AR8327. IMHO 5us should be plenty of time for all supported chips.
However I couldn't test this due to missing hardware.
If other chips should need a longer wait time we can add the
wait time as a parameter to the ar8xxx_chip struct.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 44103
