These pins seem to be used by hw exclusively, so claiming it in
kernel causes an error in syslog in k4.14+.
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
[slh: rebase for kernel v4.14 as well]
Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
EA8500 has pcie2 slot unequipped.
By EA8500 hw design default pcie2 reset gpio (gpio63) is used to
reset the switch. That's why enabling pcie2 brings the switch into
a working state.
So let's just control the gpio63 without enabling the pcie2 slot.
We have to remove the pcie2_pins node so the gpio63 is not defined
twice. Because pcie2 node has a reference to pcie2_pins we have to
remove it as well.
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
[slh: rebase for kernel v4.14 as well]
Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
According to OEM bootlog entry mass market devices are ipq8064 SoC
v2.0:
> socinfo_init: v6, id=202, ver=2.0, raw_id=2064, raw_ver=2064, hw_plat=0, hw_plat_ver=65536
I've checked C2600, EA8500 and VR2600v but couldn't find other
boards bootlog. I think it's safe to assume that other boards are
also v2.0. R7500 may be an exception because it was the first
device to hit the market.
So switch to v2.0 dtsi.
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
[slh: rebase for kernel v4.14 as well]
Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
- Rebased the patches for 4.14
- Dropped spi-qup and 0027, 0028, 0029
clk patches since it's already included
in upstream.
Tested on IPQ AP148 Board:
1) NOR boot and NAND boot
2) Tested USB and PCIe interfaces
3) WDOG test
4) cpu frequency scaling
5) ethernet, 2G and 5G WiFi
6) ubi sysupgrade
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
Tested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
