Gabor Juhos
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40a5f5c16e
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ar71xx: define NAND controller base address and register size for AR934X/QCA955x
SVN-Revision: 33382
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2012-09-12 19:06:38 +00:00 |
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Gabor Juhos
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f4be8a76de
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ar71xx: fix CPU/DDR frequency calculation for SRIF PLLs on AR934x
SVN-Revision: 33335
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2012-09-08 13:39:09 +00:00 |
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Gabor Juhos
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d1b237b335
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ar71xx: add initial support for the QCA955X SoCs
SVN-Revision: 32606
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2012-07-05 08:26:47 +00:00 |
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Gabor Juhos
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7284cf73d6
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ar71xx: refactor PCI code to allow registering multiple PCI controllers
SVN-Revision: 32605
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2012-07-05 08:26:45 +00:00 |
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Felix Fietkau
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5d364d0ca1
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ar71xx: add support for reading the MAC address from OTP ROM on AR933x
SVN-Revision: 32446
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2012-06-19 00:21:58 +00:00 |
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