Have gpio driver adopt irqdomain support so that there are
non-overlapping allocations of irq numbers mapped to gpio's.
Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com>
SVN-Revision: 42844
This patch originally failed to combine INTA/B/C/D onto a single ARM CPU
interrupt. Instead, it mapped INTA/B/C and excluded D. This patch
corrects the issue by mapping all four interrupts to the single ARM CPU
interrupt. The original intent of the patch still holds as the newer PCB
take advantage of isolated interrupts. This fix only applies to older
PCB's that do not route INTA/B/C/D to unique external ARM CPU
interrupts.
Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com>
SVN-Revision: 42830
The cns3xxx uses irq61 for pcie0_intr which in the case of a PCIe-to-PCI
bridge ends up combining INTA/B/C/D on a single ARM CPU interrupt. This is
not optimal when you have multiple cores. To overcome this limitation an
enhancement was made on newer Laguna PCB's that support miniPCI cards
to route the INTA/B/C/D signals to unique external ARM CPU interrupts which
can help balance CPU core utilization and in some cases increase overall
system performance or responsiveness.
For more details see:
http://trac.gateworks.com/wiki/multicoreprocessing#PCIInterruptsteering
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 42400
ARGC is a 'C-ism', but not known/valid in shell-syntax - insert the correct
var $# (=number of args) here. under normal conditions this had no impact,
but we should at least correct it. the error was observable like this:
root@box:~ [ -e "/etc/functions.sh" ] && . /etc/functions.sh
root@box:~ [ -e "/lib/functions.sh" ] && . /lib/functions.sh
root@box:~ . /lib/upgrade/platform.sh
root@box:~ . /lib/upgrade/common.sh
root@box:~ platform_check_image /tmp/myfirmware.bin
ash: bad number
root@box:~ echo $?
0
Signed-off-by: Bastian Bittorf <bittorf@bluebottle.com>
SVN-Revision: 40915
This reverts commit 0772ab938c0aedd7f4cc7127059d6ce8cf929dfa.
Trying to optimize calls to eth_complete_tx in this fasion causes a regression
where when sending only the tx queue can get disabled until a packet is
received. This original call to eth_schedule_poll() is scheduled so it
should not cause a performance issue.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 40592
The uImage target will always fail on a clean build due to dependency issues.
Building the uImage isn't necessary anyway as its re-built with correct
entry points in image/Makefile so remove it.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 39778
We already clean up tx descriptors in the napi eth_poll() function so it
would likely be rare to run out of available descriptors in eth_xmit. Thus
we can clean them up only when needed and return busy only when we
still don't have enough.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 39762
The combination of r35942 and r35952 causes an issue where eth_schedule_poll()
can be called from a different CPU between the call to napi_complete() and the
setting of cur_index which can break the rx ring accounting and cause ethernet
latency and/or ethernet stalls. The issue can be easilly created by adding
a couple of artificial delays such as:
@@ -715,6 +715,7 @@ static int eth_poll(struct napi_struct *napi, int budget)
if (!received) {
napi_complete(napi);
+udelay(1000);
enable_irq(IRQ_CNS3XXX_SW_R0RXC);
}
@@ -727,6 +728,7 @@ static int eth_poll(struct napi_struct *napi, int budget)
rx_ring->cur_index = i;
wmb();
+udelay(1000);
enable_rx_dma(sw);
return received;
This patch moves the setting of cur_index back up where it needs to be and
addresses the original corner case that r35942 was trying to catch in an
improved fashion by checking to see if the rx descriptor ring has become
full before interrupts were re-enabled so that a poll can be scheduled again
and avoid an rx stall caused by rx interrupts ceasing to fire again.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 39761
- add building of a standard uImage along with the combined kernel+rootfs
- remove 'old' image build - that was for a very old and obsolete bootloader
To update the bootloader for GW2387,GW2388,GW2391 (NOR Flash) from uboot:
put latest NOR bootloader on tftp server:
http://svn.gateworks.com/laguna/trunk/images/u-boot_nor.bin
Laguna> setenv ipaddr <localip>
Laguna> setenv ipaddr <serverip>
Laguna> tftpboot 0x800000 laguna/u-boot-nor.bin
Laguna> erase 0x10000000 +$(filesize)
Laguna> cp.b 0x800000 0x10000000 $(filesize)
Laguna> reset
To update the bootloader for GW2380,GW2382,GW2383 (SPI Flash) from uboot:
put latest SPI bootloader on tftp server:
http://svn.gateworks.com/laguna/trunk/images/u-boot_spi.bin
Laguna> setenv ipaddr <localip>
Laguna> setenv ipaddr <serverip>
Laguna> tftpboot 0x800000 laguna/u-boot-spi.bin
Laguna> erase 0x60000000 +$(filesize)
Laguna> cp.b 0x800000 0x60000000 $(filesize)
Laguna> reset
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 38703
In order to support both normal images and initramfs, ensure that each
target sets KERNELNAME properly so that the generic kernel building code
can copy the corresponding files over $(KDIR) with the appropriate
extension. Update the various paths to the kernel and wrapper images
from $(LINUX_DIR)/arch/$(ARCH)/boot/$(foo) to $(KDIR)/$(foo).
Signed-off-by: Florian Fainelli <florian@openwrt.org>
SVN-Revision: 37049
Update ehci/ohci driver registration to conform to the new platform
drivers.
This fixes missing USB host support in 3.8.x
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 36309
When an rx interrupt comes in, rx interrupts are disabled and NAPI
polling is scheduled. During the NAPI poll, the driver first processes
received frames in the ring, then fills the dma descriptor slots with
new buffers and calls tx complete, before finally re-enabling rx
interrupts and completing NAPI (if below the budget).
If the hardware rx queue overflows before the napi complete is called,
the hardware will not throw any further rx interrupts and rx processing
stops completely.
Fix this by keeping NAPI polling scheduled until it completes a poll
without receiving any packets, and also handle NAPI completion before
refilling rx or completing tx.
SVN-Revision: 35942
L2 cache via L2X0 cache controller available on some ARM boards can
provide a performance boost in some situations but decrease performance
in others. This adds a kernel cmdline to disable L2X0 for cns3xxx based
boards.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 34874
function. This removes those from the dwc_otg driver and removes the patch
that comments out the linkage of udc-core so that the dwc_otg driver can
co-exist happily with other USB Device Controllers.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
SVN-Revision: 34475
Combine two pcie patches (2nd patch undid the 1st patch) together
and refresh the other affected patches
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 34132
Many Laguna products have on-board GPS with Pulse-per-second (PPS)
support. This patch adds kernel support (statically) and adds
the platform data in laguna board support.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 34115
ARM Linux PCI/PCIe hardware intialization needs to occur before device_init
as it does not support hotplug. I have modeled the cns3xxx PCIe init after
other ARM platforms. Registering it early resolves resource issues occuring
during bus enumeration that occur when a device driver is linked static in
the kernel.
Instead of passing in a bitmask to enable the 2 available ports, link detect
is used to enable ports that have a valid link.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 34044
Update header file appropriately and disable read for ownership
Note that the FIQ support implements a workaround that provides a performance
boost over the traditional upstream workaround which ensures cache lines
are exclusive on driver CPU using 'read for ownership'.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
target/linux/cns3xxx/config-3.3 | 2 +-
target/linux/cns3xxx/patches-3.3/460-cns3xxx_fiq_support.patch | 9 ++++-----
2 files changed, 5 insertions(+), 6 deletions(-)
SVN-Revision: 33827
The Laguna boards do not use all the same pins for SDHCI as the Cavium
reference board.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33684
The ARM11MPCore Timer/Watchdog registers start at offset 0x600 which is where
all mpcore-wdt boards point the driver base too. I believe this is wrong
because 0x600 is aliased to the timer/watchdog of the 'current CPU' where
0x700 is CPU0's timer/watchdog, and 0x800 is CPU1's timer/watchdog. Thus
if your timer/watchdog application is switching between CPU's it can end up
writing to the wrong CPU's registers which results in random board resets
from watchdog timeouts etc.
This patch forces the timer/watchdog driver to use CPU0's registers always.
Its my opinion that other mpcore-wdt boards should be doing the same thing.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33683
Resolves an issue where isochronouse USB would cause the driver to hang as
well as scheduling issues.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33579
For cns3xxx SCU_CONFIGURATION always shows multipe cores but SCU_CPU_STATUS
shows which ones are active.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33566
Increase the size of the buffer used for eeprom reads during the platform configuration of the Gateworks laguna. The model name read in is 16 bytes but the original buffer was only 8 bytes.
Signed-off-by: David Acker <dacker@rajant.com>
SVN-Revision: 32833
