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27 commits

Author SHA1 Message Date
Gabor Juhos
ee3dfafaf1 ar71xx: add a helper function for setting up ETH_CFG register on QCA955x 
Signed-off-by: Jon Suphammer <jon@suphammer.net>
Patchwork: http://patchwork.openwrt.org/patch/5839/
[juhosg: fix coding style]
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 41623
 2014-07-13 19:43:56 +00:00
Felix Fietkau
f80f0c7d22 ar71xx: add support for QCA953x SoC 
I don't have access to the specs, so I'm not sure about every detail, but I
haven't seen any problems with my test system, a TL-WR841N v9. It looks pretty
much like a QCA955x without PCI, a little twist in the clock calculation and
a AR9331-compatible switch.

Features not yet supported:

* EHCI (my test system doesn't have USB)
* ? (I have no idea if the QCA953x has any other features I don't know about
that aren't used by the TL-WR841N v9)

Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>

SVN-Revision: 40399
 2014-04-07 07:59:45 +00:00
Gabor Juhos
05f8604e2e ar71xx: fix max frame length of the QCA955x SoCs 
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 39161
 2013-12-23 17:05:23 +00:00
Gabor Juhos
76f37c5d46 ar71xx: don't set builtin_switch flag for QCA9558 
It makes no sense, the SoC has no built-in switch.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 39160
 2013-12-23 17:05:21 +00:00
Gabor Juhos
f2cd3399f7 ar71xx: allow to use large ethernet frames on AR934x SoCs 
The hardware supports large ethernet frames. Override
the maximum frame length and packet lenght mask in the
platform data to allow to use large MTU on the ethernet
interfaces.

Limit the feature to AR934x SoCs for now. It should work
on some other SoCs as well, but those has not been tested
yet.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 39149
 2013-12-20 11:41:23 +00:00
Gabor Juhos
2c4e3cf33a ar71xx: ag71xx: get max_frame_len and desc_pktlen_mask from platform data 
This will allow to use SoC specific values for both.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 39145
 2013-12-20 11:41:17 +00:00
Gabor Juhos
ba860e4c3a ar71xx: make ag71xx_mdio_platform_data visible 
This enables us to modify the ag71xx_mdio_platform_data from within the
board support files.

Signed-off-by: Felix Kaechele <heffer@fedoraproject.org>
Patchwork: http://patchwork.openwrt.org/patch/4613/
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 39126
 2013-12-17 22:14:07 +00:00
Gabor Juhos
e312a917d3 ar71xx: rename ath79_parse_mac_addr to ath79_parse_ascii_mac 
Rename the function and extend it in order to make it
usable from board setup code.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 38085
 2013-09-20 16:41:30 +00:00
Gabor Juhos
1d55249d7c ar71xx: use backported QCA955x patches 
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 35878
 2013-03-04 11:48:15 +00:00
Gabor Juhos
8a9d92f125 ar71xx: fix ethernet device registration for the QCA9556 SoC 
Based on http://patchwork.openwrt.org/patch/3162/

Signed-off-by: Embedded Wireless GmbH <info at embeddedwireless.de>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 35394
 2013-01-29 19:12:28 +00:00
Gabor Juhos
5dec87afef ar71xx: fix ethernet device registration for QCA9558 
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 34853
 2012-12-22 12:12:48 +00:00
Gabor Juhos
4085a5773d ar71xx: fixup allowed PHY interface types for QCA9558 
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 34851
 2012-12-22 12:12:44 +00:00
Gabor Juhos
f01a786825 ar71xx: don't assign any MII bus device on QCA9558 by default 
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 34850
 2012-12-22 12:12:43 +00:00
Gabor Juhos
5ffc08e3dc ar71xx: add a helper function for setting up ETH_CFG register on AR934x 
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 33817
 2012-10-17 18:27:45 +00:00
Gabor Juhos
170cd7a19a ar71xx: avoid possible NULL pointer dereference in ath79_init_{,local}_mac 
SVN-Revision: 33575
 2012-09-27 20:05:42 +00:00
Gabor Juhos
94bac7366c ar71xx: use dynamic clock dividers on the 2nd MDIO of AR934x 
SVN-Revision: 33343
 2012-09-09 14:05:20 +00:00
Gabor Juhos
11c3392b7f Revert "ar71xx: only allow RGMII mode on the 2nd ethernet MAC of the AR7240" 
That was based on assumptions.

SVN-Revision: 33310
 2012-08-29 10:37:55 +00:00
Gabor Juhos
cca873e8e0 ar71xx: only allow RGMII mode on the 2nd ethernet MAC of the AR7240 
Signed-off-by: Daniel Golle <dgolle@allnet.de>

SVN-Revision: 33280
 2012-08-27 14:55:26 +00:00
Gabor Juhos
d1b237b335 ar71xx: add initial support for the QCA955X SoCs 
SVN-Revision: 32606
 2012-07-05 08:26:47 +00:00
Felix Fietkau
dc9675282e ar71xx: add a helper function for setting up PHY4 swapping on ar933x 
SVN-Revision: 32092
 2012-06-06 17:24:09 +00:00
Felix Fietkau
8039a1bbb2 ar71xx: fix MII clock settings for various chips, improves ethernet stability on AR934x 
SVN-Revision: 31925
 2012-05-27 21:02:41 +00:00
Gabor Juhos
3e3a4d3d6b ar71xx: allow to disable link polling on unused PHYs 
SVN-Revision: 31533
 2012-04-29 18:29:24 +00:00
Gabor Juhos
e9b45ebaba ar71xx: add AR934x specific interface speed setup for ge0 
SVN-Revision: 31017
 2012-03-19 11:11:20 +00:00
Gabor Juhos
1c5ac02a29 ar71xx: reset the switch on AR934x before ethernet device registration 
SVN-Revision: 30922
 2012-03-13 17:29:33 +00:00
Gabor Juhos
66df117d1b ar71xx: use a dummy callback for interfaces with fixed speed 
SVN-Revision: 30913
 2012-03-12 20:38:58 +00:00
Gabor Juhos
8b2b37ae58 ar71xx: merge ar934x_bo_ddr_flush patch 
SVN-Revision: 30912
 2012-03-12 20:38:57 +00:00
Gabor Juhos
d72bde99cd ar71xx: merge files-3.2 to files 
SVN-Revision: 30405
 2012-02-10 08:19:31 +00:00
Renamed from target/linux/ar71xx/files-3.2/arch/mips/ath79/dev-eth.c (Browse further)