even it's a little bit verbose, unmacrod board descriptions are much
easier to read and to understand.
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
The user benpicco in #openwrt reported that images are build which are
bigger that the available flash size.
He provided a proof of concept fix and gave permission to me to send it
for inclusion.
Signed-off-by: Mathias Kresin <dev@kresin.me>
The RJ45 WAN port is used for xDSL as well as the IP101A.
The pins 1,2,3,6 of the RJ45 are connected to the IP101A and the
pins 4,5 are connected to the xdsl chip.
Drop the ip101a-rst node. It can't be controlled and is not required
at all.
Signed-off-by: Mathias Kresin <dev@kresin.me>
The STP pinmux was initially added in assumption LAN2 led is driven by
it. It worked somehow because STP group and gphy0 led0 share the GPIO.
Do it the right way by adding the gphy0 led0 the gphy function.
According to the author, the SPI node is a copy & paste leftover. Which
makes sense since nothing is connected to the SPI bus on this device.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Use the brnboot partition layout as it is listed in the OpenWrt wiki
article for this board.
Configure the brnboot root selector for this device as well.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Cleanup the pinmux configuration by removing the unused spi node. Nothing is connected to the SPI bus on devices.
The stp_out pinmux child node covers the same GPIOs as the already used
stp group.
The same applies to the gphy-leds_out pinmux node and the "gphy0
led1" as well as "gphy1 led0" groups.
Signed-off-by: Mathias Kresin <dev@kresin.me>
This patch fixes the missing Lan interface config in the file
/etc/config/network for ARV4518PWR01/A which results in eth0 and br-lan
being down and therefore no way to access the router unless via UART-TTL.
Signed-off-by: Mohammed Berdai <mohammed.berdai@gmail.com>
The only difference between the VG3503J profiles is the version of the
gphy firmware that gets loaded. This can be handled perfect fine in one
device tree source file.
Signed-off-by: Mathias Kresin <dev@kresin.me>
VGV7510KW2 with VRX288 v1.2 has brnboot 1.8 installed. Starting with
this brnboot version, the "GPHY Clock Source" isn't set anymore by
brnboot, with the result that xrx200-net fails to probe/initialize the
phys.
Use the phy clock source device tree binding to specify the clock source.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
SVN-Revision: 49284
brnboot based devices can have two Image partitions. When flashing
images via the brnboot recovery web interface, the Image partitions are
written alternating.
The current active Image partition is stored in the first byte of the
Primary_Setting partition by using 0x00 for Code_Image_0 and 0x01 for
Code_Image_1.
By using the information about the active "Code Image", it is possible
to ensure that the rootfs belongs to the current booted Image/Kernel.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
SVN-Revision: 49281
Starting with kernel 4.4, the use of partitions as direct subnodes of the
mtd device is discouraged and only supported for backward compatiblity
reasons.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
SVN-Revision: 49280
Use the same name for TP-Link images as it was with the old image build
code.
Move the BOARD_ID export to the TP-Link image build recipe, to indicate
that the variable is only related in this context.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
SVN-Revision: 49279
Based on the vg3503j_gphy_led.sh script published in the VG3503J wiki
article, the OEM Firmware uses the following PHY led functionality:
gphy led 0: LINK/ACTIVITY
gphy led 1: LINK
gphy led 2: ACTIVITY
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
SVN-Revision: 49278
The VGV7510KW22 has the leds for LAN1-3 connected to pin1 of the phys
and the led for LAN4 connect to pin0 of the phy. This results with the
current configuration in a fast flashing LAN4 led as soon as a network
cable is connected. Something similar was reported on the forum[1] for
the VGV7519 as well.
Since it isn't predicable to which pin a (single) phy led is connected,
use the (default) pin1 functionality
Constant On: 10/100/1000MBit
Blink Fast: None
Blink Slow: None
Pulse: TX/RX
for all ethernet phy leds.
After checking pictures of all vr9 boards, it looks like only the VG3503J
has more than one led connected per phy. Using the phy led device tree
bindings to assign the functionality to the "additional" leds, the
VG3503J phy leds should behave as before.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
[1] https://forum.openwrt.org/viewtopic.php?pid=321523
SVN-Revision: 49270
Commit 8c130dd (lantiq: use new image build process for some images) broke
image generation for the xway target since the generated macros reference not
existing WBMRA.dts and WBMRB.dts files leading to the following build error:
mips-openwrt-linux-musl-cpp: error: ../dts/WBMRA.dts: No such file or directory
mips-openwrt-linux-musl-cpp: warning: '-x assembler-with-cpp' after last input file has no effect
mips-openwrt-linux-musl-cpp: fatal error: no input files
Previously both the WBMRA and WBMRB profiles shared a common WBMR DT since
the only difference is the embedded firmware kmod package.
Extend the lantiqImage macro to optionally support specifying a different
DTS file and use this facility to let the both WBMR profiles reference the
correct device tree file.
Signed-off-by: Jo-Philipp Wich <jo@mein.io>
The dwc2 USB driver now works on Lantiq ar9, but the
default is still ltq-hcd-ar9. This patch switches to
dwc2 by default.
v2: all ar9 boards (v1 was just for BTHOMEHUBV3A and WBMR)
Signed-off-by: Ben Mulvihill <ben.mulvihill@gmail.com>
SVN-Revision: 49254
The only way to access the u-boot console on the BTHOMEHUBV3A
is by soldering a serial console onto some really tiny pads.
To enable installation without soldering it would be helpful
to be able to modify the uboot environment from within
the ramdisk image used as part of the installation process.
Signed-off-by: Ben Mulvihill <ben.mulvihill@gmail.com>
SVN-Revision: 49253
Remove read-only flag on two partitions on BTHOMEHUBV3A:
uboot-config - otherwise fw_setenv command cannot be used.
ath9k-cal - so that ath9k calibration data can be copied
to the partition on a newly installed board.
Signed-off-by: Ben Mulvihill <ben.mulvihill@gmail.com>
SVN-Revision: 49250
LZMA compress the kernel without dictionary, otherwise brnboot fails to
uncompress the kernel.
The filesystem parameter of mkbrncmdline was dropped since the used
filesystem isn't exported in the kernel build step and at least in my
tests everything works without the parameter. If the parameter is
required for some reason, the static keyword "squashfs" can be used.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
SVN-Revision: 49241
Set the kernel entry address to the same value as it is used for the old
image build build process.
Fixes boot of uImages on VGV7510KW22NOR and others.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
SVN-Revision: 49237
This adds for some easy images the new build process.
This was only tested on some TP-Link devices, please test.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 49210
According to the calling convention of the o32 ABI the
caller function must reserve stack space for $a0-$a3
registers in case the callee needs to save its arguments.
The assembly startup code does not reserve stack space
for these registers thus when the main C function needs
to save its arguments, that will cause a stack overflow.
Fix the assembly code to reserve stack space for the
registers to avoid that.
Compile tested only.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 49061
Instead of using our patch-dtb program just place the device tree
behind the kernel binary and then let the in kernel mechanism fetch it.
This also adds support for having the device tree file in the boot
loader.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 49050
Avoids inadvertent file creation when executing
`/etc/init.d/dsl_control status`.
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
SVN-Revision: 48700
With the backport of the kernel 4.5 pinctrl-xway patches (3551609d &
826bca29) the pinmux group "spi" was splitted into "spi_di", "spi_do" &
"spi_clk". But the no longer existing group "spi" is still used by some
device tree source files.
This fixes the detection of the wireless chipset of the VGV7510KW22.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
SVN-Revision: 48658
The stock u-boot doesn't disable unused flash banks. Therefore, the nand
driver tries to initialize a not connected NOR flash and the device
hangs on boot.
Workaround the issue by selecting the second flash bank (NAND).
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48657
All other SoC types are using "lantiq,sram" and "simple-bus" to ensure
that all child nodes are set up correctly during linux kernel
initialization (plat_of_setup(void) in arch/mips/lantiq/prom.c). Without
this some of sram child nodes might not be parsed.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48548
This removes a lot of duplicate register and interrupt definitions by
moving the xrx200-net definition to vr9.dtsi and making all devices re-
use it.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48547
r48381 added CONFIG_MTD_SPLIT_UIMAGE_FW=Y to the lantiq kernel
configuration. That unfortunately contains a typo since the "y" has to
be lower-case. This leads to the kernel asking whether the config
symbol should be enabled and thus breaking the build.
FIXES: r48381/feab990887b4: lantiq: Enable the uImage mtd splitter
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48389
Until linux 4.1 the lantiq target used CONFIG_MTD_UIMAGE_SPLIT=y. That
option however is only available until linux 4.3 - thus it was not added
to lantiq's 4.4 kernel config (in r48307). This results in broken images
for devices which are using uImages. This fixes#21652
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48381
This adds basic support for TP-Link VR200v.
Currently the following parts are not working: FXO, Voice, DECT, WIFI (both)
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 48328
The following patches were dropped because they are already applied
upstream:
- 0038-MIPS-lantiq-fpi-on-ar9.patch
- 0039-MIPS-lantiq-initialize-usb-on-boot.patch
- 0042-USB-DWC2-big-endian-support.patch
- 0043-gpio-stp-xway-fix-phy-mask.patch
All other patches were simply refreshed, except the following:
- 0001-MIPS-lantiq-add-pcie-driver.patch
Changes to arch/mips/lantiq/xway/sysctrl.c (these changes disabled
some PMU gates for the vrx200 / VR9 SoCs) were removed since the
upstream kernel disables unused PMU gates automatically (since
95135bfa7ead1becc2879230f72583dde2b71a0c
"MIPS: Lantiq: Deactivate most of the devices by default").
- 0025-NET-MIPS-lantiq-adds-xrx200-net.patch
Since OpenWrt commit 55ba20afcc2fe785146316e5be2c2473cb329885 drivers
should use of_get_mac_address(). of_get_mac_address_mtd is not
available for drivers anymore since it's called automatically within
of_get_mac_address().
- 0028-NET-lantiq-various-etop-fixes.patch
Same changes as in 0025-NET-MIPS-lantiq-adds-xrx200-net.patch
While refreshing the kernel configuration SPI support had to be moved to
config-4.4 because otherwise M25P80 was disabled.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48307
Re-defining the compatible property is not required since the correct
value is inherited from vr9.dtsi.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48295
Compared to the "old" driver:
- Each device must assign a pinctrl setting to the SPI node to allow the
new SPI driver to configure the SPI pins.
While here we are also using separate input and output settings so we
are independent of whether the bootloader configures the pins correctly.
- We use the new "compatible" strings to make the driver choose the
correct number of chip-selects for each SoC.
- The new driver starts counting the chip-selects at 1 (instead of 0, like
the old one did). Thus we have to adjust the devices accordingly.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48293
The new driver provides a few improvements over the old one:
- Separate compatible strings per SoC type (this allows removing some
hardcoded of_device_is_compatible() checks)
- It does not rely upon spi-bitbang anymore
- chip-selects are numbered as in the datasheet (= starting at 1 instead
of 0)
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48292
All devices are now using the HW SPI driver, so this is not necessary
anymore.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48291
This allows devices to use SPI without having to re-define (and thus
duplicating) the whole SPI node.
By default SPI is disabled (as before) because only few devices need it.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48286
After the latest pinctrl backports there are only 50 (instead of 56 as
before) GPIOs/pins exported (thus the first GPIO on VRX200 SoCs is now
462, before it was 456). This means that any hardcoded GPIOs have to be
adjusted.
This broke the PCIe driver (which seems to be the only driver which uses
hardcoded GPIO numbers), it only reports:
ifx_pcie_wait_phy_link_up timeout
ifx_pcie_wait_phy_link_up timeout
ifx_pcie_wait_phy_link_up timeout
ifx_pcie_wait_phy_link_up timeout
ifx_pcie_wait_phy_link_up timeout
pcie_rc_initialize link up failed!!!!!
To prevent more of these issues in the future we remove the hardcoded
PCIe reset GPIO definition and simply pass it via device-tree (like the
PCI driver does).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48285
These were introduced in upstream commit
be14811c03cf "pinctrl/lantiq: introduce new dedicated devicetree
bindings" and finally allow us to use the individual pins within our dts
(for example spi_clk, etc.).
Please note that this changes the number of GPIOs which are available for
some SoCs. VRX200 SoCs for example only have 50 pins, but previously 56
pins were exposed. This means that all places which are using hardcoded
GPIO numbers (which are not passed via device-tree) need to be adjusted
(because the first GPIO number is now 462, instead of 456).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48284
Upstream commit be14811c03cf2 "pinctrl/lantiq: introduce new dedicated
devicetree bindings" allows us to use each pin in the pinmux. This is
useful for example in the "spi" group which contains some pins which
are inputs, and some which are outputs.
These can only be used once the new compatible strings for the pinctrl
node are used.
Additionally 0150-lantiq-pinctrl-xway.patch and the "GPIO PORT3 fix"
(which was part of 0012-pinctrl-lantiq-fix-up-pinmux.patch) were
replaced with their upstream variants which are also in 4.5.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48283
The old signature only worked because brnboot ignores the leading "5" in
the signature. We can see the correct signature when flashing a brnImage
via recovery web-interface, in this case brnboot reports:
[CGI-Signature Check] buf:[BRNDA6431], sigInFlash:[BRNDA6431]
Thanks to Mathias Kresin for reporting this.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48269
This removes the arch-specific mtdsplit parsers and enables the generic
implementations for brnImage, EVA and TP-Link instead.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 48264
This patch was merged into upstream Linux 4.1.
This fixes#21587 and was introduced in r48223.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 48229
linux 4.4 (since commit 08b3c894e56580b8ed3e601212a25bda974c3cc2
"MIPS: lantiq: Disable xbar fpi burst mode") requires that the xbar is
defined in the .dts of vrx200 (VR9) SoCs.
SVN-Revision: 48056
