In dtc version 1.4.6 the macro names in header include guards changed,
but the build relies on them matching in order to replace selected
headers. This is a horrible hack to work around this.
Signed-off-by: Thomas Nixon <tom@tomn.co.uk>
only thing not working is the b43 5GHz wifi band as upstream
kernel
doesn't supporthe 0x4360 chip so far
Signed-off-by: Rene Kjellerup <rk.katana.steel@gmail.com>
Backport commit 3d9c8f6b3f033a6092425b7344647fb51dbed5c6
Without this binutils doesn't properly link u-boot
Source:
https://sourceware.org/bugzilla/show_bug.cgi?id=23571
Signed-off-by: Daniel Engberg <daniel.engberg.lists@pyret.net>
221ce7e ubusd_acl: event send access list support
da503db ubusd_acl: event listen access list support
c035bab ubusd_acl: rework wildcard support
73bd847 ubusd_event: move strmatch_len to ubus_common.h
0327a91 ubus/lua: add support for BLOBMSG_TYPE_DOUBLE
Signed-off-by: Hans Dedecker <dedeckeh@gmail.com>
* Account for big-endian 2^26 conversion in Poly1305.
* Account for big-endian NEON in Curve25519.
* Fix macros in big-endian AArch64 code so that this will actually run there
at all.
* Prefer if (IS_ENABLED(...)) over ifdef mazes when possible.
* Call simd_relax() within any preempt-disabling glue code every once in a
while so as not to increase latency if folks pass in super long buffers.
* Prefer compiler-defined architecture macros in assembly code, which puts us
in closer alignment with upstream CRYPTOGAMS code, and is cleaner.
* Non-static symbols are prefixed with wg_ to avoid polluting the global
namespace.
* Return a bool from simd_relax() indicating whether or not we were
rescheduled.
* Reflect the proper simd conditions on arm.
* Do not reorder lines in Kbuild files for the simd asm-generic addition,
since we don't want to cause merge conflicts.
* WARN() if the selftests fail in Zinc, since if this is an initcall, it won't
block module loading, so we want to be loud.
* Document some interdependencies beside include statements.
* Add missing static statement to fpu init functions.
* Use union in chacha to access state words as a flat matrix, instead of
casting a struct to a u8 and hoping all goes well. Then, by passing around
that array as a struct for as long as possible, we can update counter[0]
instead of state[12] in the generic blocks, which makes it clearer what's
happening.
* Remove __aligned(32) for chacha20_ctx since we no longer use vmovdqa on x86,
and the other implementations do not require that kind of alignment either.
* Submit patch to ARM tree for adjusting RiscPC's cflags to be -march=armv3 so
that we can build code that uses umull.
* Allow CONFIG_ARM[64] to imply [!]CONFIG_64BIT, and use zinc arch config
variables consistently throughout.
* Document rationale for the 2^26->2^64/32 conversion in code comments.
* Convert all of remaining BUG_ON to WARN_ON.
* Replace `bxeq lr` with `reteq lr` in ARM assembler to be compatible with old
ISAs via the macro in <asm/assembler.h>.
* Do not allow WireGuard to be a built-in if IPv6 is a module.
* Writeback the base register and reorder multiplications in the NEON x25519
implementation.
* Try all combinations of different implementations in selftests, so that
potential bugs are more immediately unearthed.
* Self tests and SIMD glue code work with #include, which lets the compiler
optimize these. Previously these files were .h, because they were included,
but a simple grep of the kernel tree shows 259 other files that carry out
this same pattern. Only they prefer to instead name the files with a .c
instead of a .h, so we now follow the convention.
* Support many more platforms in QEMU, especially big endian ones.
* Kernels < 3.17 don't have read_cpuid_part, so fix building there.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
The IRQ init structs are marked as __initconst which
means this memory can be free after init.
On this platform, the PCI IRQ init happens very late _after_ the
kernel already freed the memory allocated for these structs.
During IRQ allocation, the allocation function is passed
with invalid data at this point leading to following error:
[ 0.000000] SoC: Qualcomm Atheros QCA9533 ver 2 rev 0
[ 2.382828] Freeing unused kernel memory: 264K
[ 34.414816] pci 0000:00:00.0: no irq found for pin 1
and
[ 0.000000] SoC: Qualcomm Atheros QCA956X ver 1 rev 0
[ 2.125401] Freeing unused kernel memory: 284K
[ 9.526479] pci 0000:00:00.0: no irq found for pin 1
After this patch:
[ 14.960814] pci 0000:00:00.0: using irq 40 for pin 1
Commit 318e19ba67 ("ar71xx: add v4.14 support") fixed this for the
default targets already present in the source by default but forgot
to remove the __initconst attribute for targets QCA953x and QCA956x
which are only added later through platform patches.
Fixes: 318e19ba67 ("ar71xx: add v4.14 support")
Reported-by: Sven Schönhoff <sven.schoenhoff@gmail.com>
Reported-by: Dirk Brenken <dev@brenken.org>
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
Tested-by: Dirk Brenken <dev@brenken.org>
CONFIG_SUN4I_A10_CCU controls both the A10 and the A20 enabling of the
CCU (LCCF) driver, this will be necessary once we move beyond kernel
4.14 because 4.15 has commit f18698e1c66338b902de386e4ad97b8b1b9d999d
("ARM: dts: sun7i: Convert to CCU") which requires this driver.
Fixes: ad2b3bf310 ("sunxi: Add support for kernel 4.14")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Revert "Add workaround for wrong skb->mac_len values after splitting GSO"
Remove our local patch which did the same thing.
Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
Kernels 4.14.73 & 4.9.140 include the gso fixup fix, so cake
doesn't need to do it. Let's not waste cpu cycles by doing it in
cake which could be really important on cpu constrained devices.
Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
This configuration option is not set when building the
layerscape/armv8_64b target.
Fixes: 92aa21497b ("kernel: build support for NFSv4 in nfsd")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
