BCM531x5 has two pontential cpu ports, and header mode can be enabled
independently on both.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 48302
The position of the nvram header file on brcm47xx changed with kernel
version 4.1.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 46170
On two tested devices: Netgear R6250 (BCM53011 rev 2) and Luxul XWC-1000
(BCM53011 rev 3) it was possible to use port 7 and eth1 (instead of port
5 and eth0). It seems BCM53011 just like BCM53012 has 8 ports and
usually 3 of them are connected to the SoC.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 46104
On device reset the sizes for the vlan and port tables were wrongly
calculated based on the pointer size instead of the struct size. This
causes buffer overruns on 64 bit targets, resulting in panics.
Fix this by dereferencing the pointers.
Reported-by: Fedor Konstantinov <blmink@mink.su>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45938
At least on my b53 chip, the mask is 3 bits wide, and because
of this some STP states are not set properly and discarded when read.
Maybe for some other chips it makes sense to have just 2 bits width,
but I don't have other versions around to test/validate.
If that's the case then maybe we could add another STP state mask.
Signed-off-by: Alexandru Ardelean <ardeleanalex@gmail.com>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45937
This chipset has at least 8 usable ports, e.g. Netgear R8000 has ports
5, 7 and 8 connected to Ethernet interfaces:
vlan1ports=0 1 2 3 5 7 8*
vlan2ports=4 8u
Port 6 seems to be always disabled.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45676
On BCM5301X there are two different cases to handle: CPU port 8 vs. any
other one. Support for CPU port 8 was already partially implemented but
it lacked setting some extra bit for 2G speed. It also will need to be
extended to implement "SMP dual core 3 GMAC setup". That's the reason
for handling it in separated code block.
This patch also adds overriding CPU port state for port other than 8. It
requires using recently defined GMII_PORT registers.
It was tested for regressions on BCM53011 revs 2 & 3. It was also
confirmed to fix switch on some internal Broadcom board.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45402
* properly enclose macro arguments in paranthesis on use
* remove trailing white space
* convert C99 // comments
* add missing blank lines after declaration
* remove braces from single statement blocks
* split lines > 80 chars (except for one)
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45356
It will now actually enable the mib counters instead of enabling rx/tx for
the first switch port.
Reported-by: Daniel Gonzalez <dgcbueu@gmail.com>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 44788
For bcm63xx integrated switches, broadcom changed the data endianess
to match the system endianess. But this only applies to within one word,
which causes 48/64 bit values to be still split into their "litte endian"
groups.
E.g. 48 bit values (with 5 being the most significant byte) aligned
0x00 ..01 or 0123
0x04 2345 45..
will become
0x00 ..10 resp. 3210
0x04 5432 54..
Likewise for 64 bit values.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 44568
According to the thread https://forum.openwrt.org/viewtopic.php?id=48281
b53 uses GPIO 7:
[ 4.470000] b53_common: [DBG] b53_switch_reset_gpio using 7
and causes device to self-reboot. GPIO 8 was found in CFE boot log:
"Reset switch via GPIO 8 ..."
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 41526
The BCM5365 needs a shift of 7 bits and not 6 bits like the BCM5325 for
the untagged ports.
Thank you Russell for reporting this and testing the patch.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 38793
The revision is stored in a different register than it is in other
Broadcom switches.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 37995
These switches are integrated in some recent BCM53XX and BCM47XX SoCs
like the BCM53572.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 37994
The Linksys wrt310n v1 does not have a robo_reset config variable in
nvram, but GPIO Pin 8 is the pin needed for resetting the external
switch, Linksys hard coded it into their source code.
Thank you Devastator for testing.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 37988
BCM5365 (and probably other older variants) use a different phy id, so
the phy driver never attached for them.
Fix this by adding the appropriate phy id to the fixup and the phy
driver.
Reported-by: Russell Senior <russell@personaltelco.net>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 37906
b53_no_ops has no elements and b53_port_ops has one element, this makes
the code access some random memory when trying to access the mib
counter functions.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 37895
This is needed for some switches used on bcm47xx SoCs like the one on the Asus RT-N66U.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 37645
This makes it possible to use swconfig to controll the switch.
This was tested with devices using b43 and bgmac.
This was not tested on devices using tg3.
This does not support the adm switch used in some very old devices.
SVN-Revision: 37304
Setting this bit stops BCM53125 (bgmac actually) from receiving any
packets. This bit is cleared conditionally in b53_switch_reset and it
seems the same is done in bcmrobo.c which never sets that bit again.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 35723
b53_switch_detect returns value returned by b53_read8, which is 0 for
success. So fail (and return error) only if b53_switch_detect returned
something else than 0. This fixes supported and advertising being zeros
for MDIO access.
Cc: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 35534
Add swconfig switch driver for Broadcom BCM53XX switch chips. Supports
switches connected through MDIO, SPI or memory mapped registers, and
supports BCM5325, BCM539x, BCM531x5 and the BCM63XX internal switch
chips.
Tested are BCM5325 trough MDIO, BCM53115 through SPI, and BCM6328.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 35305
