The DWR-116-A1/2 Wireless Router is based on the MT7620N SoC.
Specification:
MediaTek MT7620N (580 Mhz)
32 MB of RAM
8 MB of FLASH
802.11bgn radio
5x 10/100 Mbps Ethernet (1 WAN and 4 LAN)
2x external, non-detachable antennas
UART (J1 in A1, JP1 in A2) header on PCB (57600 8n1)
6x LED (GPIO-controlled), 2x button
JBOOT bootloader
Known issues:
WAN LED is drived by uartl tx pin. I decide to use this pin as
uartlite tx pin.
Installation:
Apply factory image via http web-gui.
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
Some targets need 4K sectors for small flash chips (e.g. some
routerboards, where the entire chip is just one "erase block"), whereas
on other devices 4K sectors lead to horrible flash erase/write
performance.
Set the default limit in the generic kernel configuration to 4 MiB to
ensure that all new platforms don't use 4K sectors for bigger flash
chips. On all existing targets use 16 MiB for now to avoid regressions.
They will be changed individually in follow-up commits.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
CONFIG_SG_POOL symbol is selected only by CONFIG_SCSI, since the last
one is disabled by default then disable CONFIG_SG_POOL by default too.
And explicitly enable it only for platforms that use CONFIG_SCSI.
Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>
