ath25: update kernel from 3.18 to 4.4
Summary of changes: * moved config-3.18 to config-4.4 and patches-3.18 to patches-4.4 * removed most of the first two patches, that seem to be upstream already * changed deprecated/removed IRQF_DISABLED to zero following examples in upstream kernel patches * added config line to disable device-tree to satisfy kernel configuration * add new image generation code Build tested and run tested on an Accton MR3201A. Signed-off-by: Russell Senior <russell@personaltelco.net> Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
Russell Senior
John Crispin
parent
c7efbd7dbb
commit
f89a20a89a
18 changed files with 152 additions and 2937 deletions
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@ -12,7 +12,7 @@ BOARDNAME:=Atheros AR231x/AR5312
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FEATURES:=squashfs low_mem
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MAINTAINER:=Sergey Ryazanov <ryazanov.s.a@gmail.com>
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KERNEL_PATCHVER:=3.18
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KERNEL_PATCHVER:=4.4
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include $(INCLUDE_DIR)/target.mk
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@ -1,16 +1,20 @@
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CONFIG_ADM6996_PHY=y
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CONFIG_AR2315_WDT=y
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CONFIG_AR8216_PHY=y
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CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
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CONFIG_ARCH_BINFMT_ELF_STATE=y
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CONFIG_ARCH_CLOCKSOURCE_DATA=y
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CONFIG_ARCH_DISCARD_MEMBLOCK=y
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CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
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CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
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# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
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# CONFIG_ARCH_HAS_SG_CHAIN is not set
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CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
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CONFIG_ARCH_REQUIRE_GPIOLIB=y
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CONFIG_ARCH_SUPPORTS_UPROBES=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_USE_BUILTIN_BSWAP=y
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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CONFIG_ATH25=y
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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@ -31,18 +35,22 @@ CONFIG_CPU_R4K_CACHE_TLB=y
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CONFIG_CPU_R4K_FPU=y
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CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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CONFIG_CRYPTO_RNG2=y
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CONFIG_CRYPTO_WORKQUEUE=y
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CONFIG_CSRC_R4K=y
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CONFIG_DMA_NONCOHERENT=y
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CONFIG_EARLY_PRINTK=y
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CONFIG_ETHERNET_PACKET_MANGLE=y
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CONFIG_GENERIC_ATOMIC64=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_GENERIC_IO=y
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CONFIG_GENERIC_IRQ_CHIP=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_TIME_VSYSCALL=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_AR2315=y
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CONFIG_GPIO_AR5312=y
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@ -53,6 +61,7 @@ CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT_MAP=y
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# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
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# CONFIG_HAVE_ARCH_BITREVERSE is not set
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CONFIG_HAVE_ARCH_JUMP_LABEL=y
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CONFIG_HAVE_ARCH_KGDB=y
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CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
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@ -73,6 +82,8 @@ CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
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CONFIG_HAVE_LATENCYTOP_SUPPORT=y
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CONFIG_HAVE_MEMBLOCK=y
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CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
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CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
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@ -80,18 +91,21 @@ CONFIG_HAVE_NET_DSA=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HAVE_PERF_EVENTS=y
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CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
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CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
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CONFIG_HW_HAS_PCI=y
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CONFIG_HW_RANDOM=y
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CONFIG_HZ_PERIODIC=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IP17XX_PHY=y
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CONFIG_IRQ_CPU=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_MIPS_CPU=y
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CONFIG_IRQ_WORK=y
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CONFIG_LEDS_GPIO=y
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CONFIG_MDIO_BOARDINFO=y
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CONFIG_MIPS=y
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CONFIG_MIPS_CLOCK_VSYSCALL=y
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CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
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# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
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CONFIG_MIPS_L1_CACHE_SHIFT=5
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# CONFIG_MIPS_MACHINE is not set
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@ -110,22 +124,27 @@ CONFIG_NEED_PER_CPU_KM=y
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CONFIG_NET_AR231X=y
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CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
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# CONFIG_NO_IOPORT_MAP is not set
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CONFIG_PAGEFLAGS_EXTENDED=y
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# CONFIG_OF is not set
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CONFIG_PCI=y
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CONFIG_PCI_AR2315=y
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CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PERF_USE_VMALLOC=y
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CONFIG_PGTABLE_LEVELS=2
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CONFIG_PHYLIB=y
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# CONFIG_PREEMPT_RCU is not set
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# CONFIG_RCU_STALL_COMMON is not set
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CONFIG_SCHED_HRTICK=y
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# CONFIG_SCHED_INFO is not set
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# CONFIG_SCSI_DMA is not set
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# CONFIG_SERIAL_8250_FSL is not set
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CONFIG_SERIAL_8250_NR_UARTS=1
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CONFIG_SERIAL_8250_RUNTIME_UARTS=1
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CONFIG_SOC_AR2315=y
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CONFIG_SOC_AR5312=y
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CONFIG_SRCU=y
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# CONFIG_SWAP is not set
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CONFIG_SWCONFIG=y
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CONFIG_SYSCTL_EXCEPTION_TRACE=y
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y
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CONFIG_SYS_HAS_EARLY_PRINTK=y
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CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
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@ -7,54 +7,104 @@
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include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/image.mk
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DEVICE_VARS += KERNEL_PREFIX FILESYSTEMS
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define Image/BuildKernel
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cp $(KDIR)/vmlinux.elf $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.elf
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gzip -9n -c $(KDIR)/vmlinux > $(KDIR)/vmlinux.bin.gz
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$(STAGING_DIR_HOST)/bin/lzma e $(KDIR)/vmlinux $(KDIR)/vmlinux.bin.l7
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dd if=$(KDIR)/vmlinux.bin.l7 of=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma bs=65536 conv=sync
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$(STAGING_DIR_HOST)/bin/lzma e $(KDIR)/vmlinux $(KDIR)/vmlinux.bin.lzma
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dd if=$(KDIR)/vmlinux.bin.gz of=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux.gz bs=65536 conv=sync
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dd if=$(KDIR)/vmlinux.bin.lzma of=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma bs=65536 conv=sync
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endef
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define Image/Build/squashfs
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$(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
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$(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
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endef
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define Image/Build
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$(call Image/Build/$(1))
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dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync
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-$(STAGING_DIR_HOST)/bin/mkfwimage \
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-B XS2 -v XS2.ar2316.OpenWrt.$(REVISION) \
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-k $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma \
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-r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \
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-o $(BIN_DIR)/$(IMG_PREFIX)-ubnt2-$(1).bin
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-$(STAGING_DIR_HOST)/bin/mkfwimage \
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-B XS5 -v XS5.ar2313.OpenWrt.$(REVISION) \
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-k $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma \
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-r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \
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-o $(BIN_DIR)/$(IMG_PREFIX)-ubnt5-$(1).bin
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-$(STAGING_DIR_HOST)/bin/mkfwimage \
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-B XS2-8 -v XS2.ar2316.OpenWrt.$(REVISION) \
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-k $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma \
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-r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \
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-o $(BIN_DIR)/$(IMG_PREFIX)-ubnt2-pico2-$(1).bin
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-$(STAGING_DIR_HOST)/bin/mkmylofw -B np25g \
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-p0x020000:0x130000:ah:0x80041000:linux:$(KDIR)/vmlinux.bin.gz \
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-p0x150000:0x2a0000:::rootfs:$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \
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$(BIN_DIR)/$(IMG_PREFIX)-np25g-$(1).bin
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-$(STAGING_DIR_HOST)/bin/mkmylofw -B wpe53g \
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-p0x020000:0x130000:ah:0x80041000:linux:$(KDIR)/vmlinux.bin.gz \
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-p0x150000:0x2a0000:::rootfs:$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \
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$(BIN_DIR)/$(IMG_PREFIX)-wpe53g-$(1).bin
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-sh $(TOPDIR)/scripts/combined-image.sh \
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"$(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma" \
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"$(BIN_DIR)/$(IMG_PREFIX)-root.$(1)" \
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"$(BIN_DIR)/$(IMG_PREFIX)-combined.$(1).img"
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endef
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define Device/Default
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PROFILES = Default $$(DEVICE_NAME)
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KERNEL := lzma-kernel
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IMAGES := sysupgrade.bin
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FILESYSTEMS := squashfs
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endef
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define Build/mkfwimage
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$(STAGING_DIR_HOST)/bin/mkfwimage \
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-B $(1).OpenWrt.$(REVISION) \
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-k $(KDIR)/$(KERNEL_IMAGE) \
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-r $@ \
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-o $@.new && \
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mv $@.new $@
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endef
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define Build/combined-image
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-sh $(TOPDIR)/scripts/combined-image.sh \
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"$(KDIR)/$(KERNEL_IMAGE)" \
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"$@" \
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"$@.new" && \
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mv $@.new $@
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endef
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define Build/mkmylofw
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$(STAGING_DIR_HOST)/bin/mkmylofw -B $(1) \
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-p0x020000:0x130000:ah:0x80041000:linux:$(KDIR)/$(KERNEL_IMAGE) \
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-p0x150000:0x2a0000:::rootfs:$@ \
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$@.new && \
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mv $@.new $@
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endef
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define Build/gzip-kernel
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gzip -9n -c $(KDIR)/vmlinux > $@
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dd if=$@ of=$@.new bs=65536 conv=sync
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mv $@.new $@
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endef
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define Build/lzma-kernel
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$(STAGING_DIR_HOST)/bin/lzma e $(KDIR)/vmlinux $@.l7
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dd if=$@.l7 of=$@ bs=65536 conv=sync
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endef
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define Device/combined
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DEVICE_TITLE := Combined Image
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IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | combined-image
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endef
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TARGET_DEVICES += combined
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define Device/ubnt2-pico2
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DEVICE_TITLE := Ubiquiti XS2-8
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IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | mkfwimage XS2-8 -v XS2.ar2316
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endef
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TARGET_DEVICES += ubnt2-pico2
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define Device/ubnt2
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DEVICE_TITLE := Ubiquiti XS2
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IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | mkfwimage XS2 -v XS2.ar2316
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endef
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TARGET_DEVICES += ubnt2
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define Device/ubnt5
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DEVICE_TITLE := Ubiquiti XS5
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IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | mkfwimage XS5 -v XS5.ar2313
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endef
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TARGET_DEVICES += ubnt5
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define Device/np25g
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DEVICE_TITLE := np25g
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KERNEL := gzip-kernel
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IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | mkmylofw np25g
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endef
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#TARGET_DEVICES += np25g
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define Device/wpe53g
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DEVICE_TITLE := wpe53g
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KERNEL := gzip-kernel
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IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | mkmylofw wpe53g
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endef
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#TARGET_DEVICES += wpe53g
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$(eval $(call BuildImage))
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File diff suppressed because it is too large
Load diff
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@ -1,68 +0,0 @@
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--- /dev/null
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+++ b/arch/mips/ath25/early_printk.c
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@@ -0,0 +1,44 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
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+ */
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+
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+#include <linux/mm.h>
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+#include <linux/io.h>
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+#include <linux/serial_reg.h>
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+
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+#include "devices.h"
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+#include "ar2315_regs.h"
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+#include "ar5312_regs.h"
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+
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+static inline void prom_uart_wr(void __iomem *base, unsigned reg,
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+ unsigned char ch)
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+{
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+ __raw_writel(ch, base + 4 * reg);
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+}
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+
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+static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg)
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+{
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+ return __raw_readl(base + 4 * reg);
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+}
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+
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+void prom_putchar(unsigned char ch)
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+{
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+ static void __iomem *base;
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+
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+ if (unlikely(base == NULL)) {
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+ if (is_ar2315())
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+ base = (void __iomem *)(KSEG1ADDR(AR2315_UART0_BASE));
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+ else
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+ base = (void __iomem *)(KSEG1ADDR(AR5312_UART0_BASE));
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+ }
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+
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+ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0)
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+ ;
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+ prom_uart_wr(base, UART_TX, ch);
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+ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0)
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+ ;
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+}
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--- a/arch/mips/ath25/Makefile
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+++ b/arch/mips/ath25/Makefile
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@@ -9,5 +9,8 @@
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#
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obj-y += board.o prom.o devices.o
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+
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+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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+
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obj-$(CONFIG_SOC_AR5312) += ar5312.o
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obj-$(CONFIG_SOC_AR2315) += ar2315.o
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -106,6 +106,7 @@ config ATH25
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_32BIT_KERNEL
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+ select SYS_HAS_EARLY_PRINTK
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help
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Support for Atheros AR231x and Atheros AR531x based boards
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@ -1,613 +0,0 @@
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--- a/arch/mips/pci/Makefile
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+++ b/arch/mips/pci/Makefile
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@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
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obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
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ops-bcm63xx.o
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obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
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+obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o
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obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
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obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
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obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o
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--- /dev/null
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+++ b/arch/mips/pci/pci-ar2315.c
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@@ -0,0 +1,511 @@
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+/*
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+ * This program is free software; you can redistribute it and/or
|
||||
+ * modify it under the terms of the GNU General Public License
|
||||
+ * as published by the Free Software Foundation; either version 2
|
||||
+ * of the License, or (at your option) any later version.
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+ *
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||||
+ * This program is distributed in the hope that it will be useful,
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||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ *
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||||
+ * You should have received a copy of the GNU General Public License
|
||||
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+/**
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+ * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
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+ * and interrupt. PCI interface supports MMIO access method, but does not
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+ * seem to support I/O ports.
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+ *
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+ * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
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+ * a memory read/write command on the PCI bus. 30 LSBs of address on
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+ * the bus are taken from memory read/write request and 2 MSBs are
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+ * determined by PCI unit configuration.
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+ *
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+ * To work with the configuration space instead of memory is necessary set
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+ * the CFG_SEL bit in the PCI_MISC_CONFIG register.
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+ *
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+ * Devices on the bus can perform DMA requests via chip BAR1. PCI host
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+ * controller BARs are programmend as if an external device is programmed.
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+ * Which means that during configuration, IDSEL pin of the chip should be
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+ * asserted.
|
||||
+ *
|
||||
+ * We know (and support) only one board that uses the PCI interface -
|
||||
+ * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
|
||||
+ * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
|
||||
+ * and IDSEL pin of AR2315 is connected to AD[16] line.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/types.h>
|
||||
+#include <linux/pci.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/mm.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/bitops.h>
|
||||
+#include <linux/irq.h>
|
||||
+#include <linux/irqdomain.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <asm/paccess.h>
|
||||
+
|
||||
+/*
|
||||
+ * PCI Bus Interface Registers
|
||||
+ */
|
||||
+#define AR2315_PCI_1MS_REG 0x0008
|
||||
+
|
||||
+#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
|
||||
+
|
||||
+#define AR2315_PCI_MISC_CONFIG 0x000c
|
||||
+
|
||||
+#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
|
||||
+#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* Mem or Config cycles */
|
||||
+#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
|
||||
+#define AR2315_PCIMISC_RST_MODE 0x00000030
|
||||
+#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
|
||||
+#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
|
||||
+#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
|
||||
+#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
|
||||
+#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
|
||||
+#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
|
||||
+#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
|
||||
+#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
|
||||
+ * disable */
|
||||
+
|
||||
+#define AR2315_PCI_OUT_TSTAMP 0x0010
|
||||
+
|
||||
+#define AR2315_PCI_UNCACHE_CFG 0x0014
|
||||
+
|
||||
+#define AR2315_PCI_IN_EN 0x0100
|
||||
+
|
||||
+#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
|
||||
+#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
|
||||
+#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
|
||||
+#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
|
||||
+
|
||||
+#define AR2315_PCI_IN_DIS 0x0104
|
||||
+
|
||||
+#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
|
||||
+#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
|
||||
+#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
|
||||
+#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
|
||||
+
|
||||
+#define AR2315_PCI_IN_PTR 0x0200
|
||||
+
|
||||
+#define AR2315_PCI_OUT_EN 0x0400
|
||||
+
|
||||
+#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
|
||||
+
|
||||
+#define AR2315_PCI_OUT_DIS 0x0404
|
||||
+
|
||||
+#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
|
||||
+
|
||||
+#define AR2315_PCI_OUT_PTR 0x0408
|
||||
+
|
||||
+/* PCI interrupt status (write one to clear) */
|
||||
+#define AR2315_PCI_ISR 0x0500
|
||||
+
|
||||
+#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
|
||||
+#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
|
||||
+#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
|
||||
+#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
|
||||
+#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
|
||||
+#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
|
||||
+#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
|
||||
+#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
|
||||
+#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
|
||||
+#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
|
||||
+#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
|
||||
+#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
|
||||
+
|
||||
+/* PCI interrupt mask */
|
||||
+#define AR2315_PCI_IMR 0x0504
|
||||
+
|
||||
+/* Global PCI interrupt enable */
|
||||
+#define AR2315_PCI_IER 0x0508
|
||||
+
|
||||
+#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
|
||||
+#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
|
||||
+
|
||||
+#define AR2315_PCI_HOST_IN_EN 0x0800
|
||||
+#define AR2315_PCI_HOST_IN_DIS 0x0804
|
||||
+#define AR2315_PCI_HOST_IN_PTR 0x0810
|
||||
+#define AR2315_PCI_HOST_OUT_EN 0x0900
|
||||
+#define AR2315_PCI_HOST_OUT_DIS 0x0904
|
||||
+#define AR2315_PCI_HOST_OUT_PTR 0x0908
|
||||
+
|
||||
+/*
|
||||
+ * PCI interrupts, which share IP5
|
||||
+ * Keep ordered according to AR2315_PCI_INT_XXX bits
|
||||
+ */
|
||||
+#define AR2315_PCI_IRQ_EXT 25
|
||||
+#define AR2315_PCI_IRQ_ABORT 26
|
||||
+#define AR2315_PCI_IRQ_COUNT 27
|
||||
+
|
||||
+/* Arbitrary size of memory region to access the configuration space */
|
||||
+#define AR2315_PCI_CFG_SIZE 0x00100000
|
||||
+
|
||||
+#define AR2315_PCI_HOST_SLOT 3
|
||||
+#define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
|
||||
+
|
||||
+/* ??? access BAR */
|
||||
+#define AR2315_PCI_HOST_MBAR0 0x10000000
|
||||
+/* RAM access BAR */
|
||||
+#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
|
||||
+/* ??? access BAR */
|
||||
+#define AR2315_PCI_HOST_MBAR2 0x30000000
|
||||
+
|
||||
+struct ar2315_pci_ctrl {
|
||||
+ void __iomem *cfg_mem;
|
||||
+ void __iomem *mmr_mem;
|
||||
+ unsigned irq;
|
||||
+ unsigned irq_ext;
|
||||
+ struct irq_domain *domain;
|
||||
+ struct pci_controller pci_ctrl;
|
||||
+ struct resource mem_res;
|
||||
+ struct resource io_res;
|
||||
+};
|
||||
+
|
||||
+static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
|
||||
+{
|
||||
+ struct pci_controller *hose = bus->sysdata;
|
||||
+
|
||||
+ return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl);
|
||||
+}
|
||||
+
|
||||
+static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg)
|
||||
+{
|
||||
+ return __raw_readl(apc->mmr_mem + reg);
|
||||
+}
|
||||
+
|
||||
+static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg,
|
||||
+ u32 val)
|
||||
+{
|
||||
+ __raw_writel(val, apc->mmr_mem + reg);
|
||||
+}
|
||||
+
|
||||
+static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg,
|
||||
+ u32 mask, u32 val)
|
||||
+{
|
||||
+ u32 ret = ar2315_pci_reg_read(apc, reg);
|
||||
+
|
||||
+ ret &= ~mask;
|
||||
+ ret |= val;
|
||||
+ ar2315_pci_reg_write(apc, reg, ret);
|
||||
+}
|
||||
+
|
||||
+static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn,
|
||||
+ int where, int size, u32 *ptr, bool write)
|
||||
+{
|
||||
+ int func = PCI_FUNC(devfn);
|
||||
+ int dev = PCI_SLOT(devfn);
|
||||
+ u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
|
||||
+ u32 mask = 0xffffffff >> 8 * (4 - size);
|
||||
+ u32 sh = (where & 3) * 8;
|
||||
+ u32 value, isr;
|
||||
+
|
||||
+ /* Prevent access past the remapped area */
|
||||
+ if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+
|
||||
+ /* Clear pending errors */
|
||||
+ ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
|
||||
+ /* Select Configuration access */
|
||||
+ ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0,
|
||||
+ AR2315_PCIMISC_CFG_SEL);
|
||||
+
|
||||
+ mb(); /* PCI must see space change before we begin */
|
||||
+
|
||||
+ value = __raw_readl(apc->cfg_mem + addr);
|
||||
+
|
||||
+ isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
|
||||
+
|
||||
+ if (isr & AR2315_PCI_INT_ABORT)
|
||||
+ goto exit_err;
|
||||
+
|
||||
+ if (write) {
|
||||
+ value = (value & ~(mask << sh)) | *ptr << sh;
|
||||
+ __raw_writel(value, apc->cfg_mem + addr);
|
||||
+ isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
|
||||
+ if (isr & AR2315_PCI_INT_ABORT)
|
||||
+ goto exit_err;
|
||||
+ } else {
|
||||
+ *ptr = (value >> sh) & mask;
|
||||
+ }
|
||||
+
|
||||
+ goto exit;
|
||||
+
|
||||
+exit_err:
|
||||
+ ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
|
||||
+ if (!write)
|
||||
+ *ptr = 0xffffffff;
|
||||
+
|
||||
+exit:
|
||||
+ /* Select Memory access */
|
||||
+ ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL,
|
||||
+ 0);
|
||||
+
|
||||
+ return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
|
||||
+ PCIBIOS_SUCCESSFUL;
|
||||
+}
|
||||
+
|
||||
+static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc,
|
||||
+ unsigned devfn, int where, u32 *val)
|
||||
+{
|
||||
+ return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val,
|
||||
+ false);
|
||||
+}
|
||||
+
|
||||
+static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc,
|
||||
+ unsigned devfn, int where, u32 val)
|
||||
+{
|
||||
+ return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val,
|
||||
+ true);
|
||||
+}
|
||||
+
|
||||
+static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where,
|
||||
+ int size, u32 *value)
|
||||
+{
|
||||
+ struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
|
||||
+
|
||||
+ if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+
|
||||
+ return ar2315_pci_cfg_access(apc, devfn, where, size, value, false);
|
||||
+}
|
||||
+
|
||||
+static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where,
|
||||
+ int size, u32 value)
|
||||
+{
|
||||
+ struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
|
||||
+
|
||||
+ if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
|
||||
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
+
|
||||
+ return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true);
|
||||
+}
|
||||
+
|
||||
+static struct pci_ops ar2315_pci_ops = {
|
||||
+ .read = ar2315_pci_cfg_read,
|
||||
+ .write = ar2315_pci_cfg_write,
|
||||
+};
|
||||
+
|
||||
+static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
|
||||
+{
|
||||
+ unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
|
||||
+ int res;
|
||||
+ u32 id;
|
||||
+
|
||||
+ res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id);
|
||||
+ if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ /* Program MBARs */
|
||||
+ ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
|
||||
+ AR2315_PCI_HOST_MBAR0);
|
||||
+ ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1,
|
||||
+ AR2315_PCI_HOST_MBAR1);
|
||||
+ ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
|
||||
+ AR2315_PCI_HOST_MBAR2);
|
||||
+
|
||||
+ /* Run */
|
||||
+ ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
|
||||
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
|
||||
+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
|
||||
+ PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc)
|
||||
+{
|
||||
+ struct ar2315_pci_ctrl *apc = irq_get_handler_data(irq);
|
||||
+ u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
|
||||
+ ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
|
||||
+ unsigned pci_irq = 0;
|
||||
+
|
||||
+ if (pending)
|
||||
+ pci_irq = irq_find_mapping(apc->domain, __ffs(pending));
|
||||
+
|
||||
+ if (pci_irq)
|
||||
+ generic_handle_irq(pci_irq);
|
||||
+ else
|
||||
+ spurious_interrupt();
|
||||
+}
|
||||
+
|
||||
+static void ar2315_pci_irq_mask(struct irq_data *d)
|
||||
+{
|
||||
+ struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
|
||||
+
|
||||
+ ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0);
|
||||
+}
|
||||
+
|
||||
+static void ar2315_pci_irq_mask_ack(struct irq_data *d)
|
||||
+{
|
||||
+ struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
|
||||
+ u32 m = BIT(d->hwirq);
|
||||
+
|
||||
+ ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0);
|
||||
+ ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m);
|
||||
+}
|
||||
+
|
||||
+static void ar2315_pci_irq_unmask(struct irq_data *d)
|
||||
+{
|
||||
+ struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
|
||||
+
|
||||
+ ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq));
|
||||
+}
|
||||
+
|
||||
+static struct irq_chip ar2315_pci_irq_chip = {
|
||||
+ .name = "AR2315-PCI",
|
||||
+ .irq_mask = ar2315_pci_irq_mask,
|
||||
+ .irq_mask_ack = ar2315_pci_irq_mask_ack,
|
||||
+ .irq_unmask = ar2315_pci_irq_unmask,
|
||||
+};
|
||||
+
|
||||
+static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq,
|
||||
+ irq_hw_number_t hw)
|
||||
+{
|
||||
+ irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip, handle_level_irq);
|
||||
+ irq_set_chip_data(irq, d->host_data);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct irq_domain_ops ar2315_pci_irq_domain_ops = {
|
||||
+ .map = ar2315_pci_irq_map,
|
||||
+};
|
||||
+
|
||||
+static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc)
|
||||
+{
|
||||
+ ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
|
||||
+ ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
|
||||
+ AR2315_PCI_INT_EXT), 0);
|
||||
+
|
||||
+ apc->irq_ext = irq_create_mapping(apc->domain, AR2315_PCI_IRQ_EXT);
|
||||
+
|
||||
+ irq_set_chained_handler(apc->irq, ar2315_pci_irq_handler);
|
||||
+ irq_set_handler_data(apc->irq, apc);
|
||||
+
|
||||
+ /* Clear any pending Abort or external Interrupts
|
||||
+ * and enable interrupt processing */
|
||||
+ ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT |
|
||||
+ AR2315_PCI_INT_EXT);
|
||||
+ ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
|
||||
+}
|
||||
+
|
||||
+static int ar2315_pci_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct ar2315_pci_ctrl *apc;
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct resource *res;
|
||||
+ int irq, err;
|
||||
+
|
||||
+ apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL);
|
||||
+ if (!apc)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ irq = platform_get_irq(pdev, 0);
|
||||
+ if (irq < 0)
|
||||
+ return -EINVAL;
|
||||
+ apc->irq = irq;
|
||||
+
|
||||
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
+ "ar2315-pci-ctrl");
|
||||
+ apc->mmr_mem = devm_ioremap_resource(dev, res);
|
||||
+ if (IS_ERR(apc->mmr_mem))
|
||||
+ return PTR_ERR(apc->mmr_mem);
|
||||
+
|
||||
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
+ "ar2315-pci-ext");
|
||||
+ if (!res)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ apc->mem_res.name = "AR2315 PCI mem space";
|
||||
+ apc->mem_res.parent = res;
|
||||
+ apc->mem_res.start = res->start;
|
||||
+ apc->mem_res.end = res->end;
|
||||
+ apc->mem_res.flags = IORESOURCE_MEM;
|
||||
+
|
||||
+ /* Remap PCI config space */
|
||||
+ apc->cfg_mem = devm_ioremap_nocache(dev, res->start,
|
||||
+ AR2315_PCI_CFG_SIZE);
|
||||
+ if (!apc->cfg_mem) {
|
||||
+ dev_err(dev, "failed to remap PCI config space\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
|
||||
+ ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
|
||||
+ AR2315_PCIMISC_RST_MODE,
|
||||
+ AR2315_PCIRST_LOW);
|
||||
+ msleep(100);
|
||||
+
|
||||
+ /* Bring the PCI out of reset */
|
||||
+ ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
|
||||
+ AR2315_PCIMISC_RST_MODE,
|
||||
+ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
|
||||
+
|
||||
+ ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG,
|
||||
+ 0x1E | /* 1GB uncached */
|
||||
+ (1 << 5) | /* Enable uncached */
|
||||
+ (0x2 << 30) /* Base: 0x80000000 */);
|
||||
+ ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG);
|
||||
+
|
||||
+ msleep(500);
|
||||
+
|
||||
+ err = ar2315_pci_host_setup(apc);
|
||||
+ if (err)
|
||||
+ return err;
|
||||
+
|
||||
+ apc->domain = irq_domain_add_linear(NULL, AR2315_PCI_IRQ_COUNT,
|
||||
+ &ar2315_pci_irq_domain_ops, apc);
|
||||
+ if (!apc->domain) {
|
||||
+ dev_err(dev, "failed to add IRQ domain\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ ar2315_pci_irq_init(apc);
|
||||
+
|
||||
+ /* PCI controller does not support I/O ports */
|
||||
+ apc->io_res.name = "AR2315 IO space";
|
||||
+ apc->io_res.start = 0;
|
||||
+ apc->io_res.end = 0;
|
||||
+ apc->io_res.flags = IORESOURCE_IO,
|
||||
+
|
||||
+ apc->pci_ctrl.pci_ops = &ar2315_pci_ops;
|
||||
+ apc->pci_ctrl.mem_resource = &apc->mem_res,
|
||||
+ apc->pci_ctrl.io_resource = &apc->io_res,
|
||||
+
|
||||
+ register_pci_controller(&apc->pci_ctrl);
|
||||
+
|
||||
+ dev_info(dev, "register PCI controller\n");
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver ar2315_pci_driver = {
|
||||
+ .probe = ar2315_pci_probe,
|
||||
+ .driver = {
|
||||
+ .name = "ar2315-pci",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static int __init ar2315_pci_init(void)
|
||||
+{
|
||||
+ return platform_driver_register(&ar2315_pci_driver);
|
||||
+}
|
||||
+arch_initcall(ar2315_pci_init);
|
||||
+
|
||||
+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
+{
|
||||
+ struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(dev->bus);
|
||||
+
|
||||
+ return slot ? 0 : apc->irq_ext;
|
||||
+}
|
||||
+
|
||||
+int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
--- a/arch/mips/ath25/Kconfig
|
||||
+++ b/arch/mips/ath25/Kconfig
|
||||
@@ -7,3 +7,10 @@ config SOC_AR2315
|
||||
bool "Atheros AR2315+ SoC support"
|
||||
depends on ATH25
|
||||
default y
|
||||
+
|
||||
+config PCI_AR2315
|
||||
+ bool "Atheros AR2315 PCI controller support"
|
||||
+ depends on SOC_AR2315
|
||||
+ select HW_HAS_PCI
|
||||
+ select PCI
|
||||
+ default y
|
||||
--- a/arch/mips/ath25/ar2315.c
|
||||
+++ b/arch/mips/ath25/ar2315.c
|
||||
@@ -134,6 +134,10 @@ static void ar2315_irq_dispatch(void)
|
||||
|
||||
if (pending & CAUSEF_IP3)
|
||||
do_IRQ(AR2315_IRQ_WLAN0);
|
||||
+#ifdef CONFIG_PCI_AR2315
|
||||
+ else if (pending & CAUSEF_IP5)
|
||||
+ do_IRQ(AR2315_IRQ_LCBUS_PCI);
|
||||
+#endif
|
||||
else if (pending & CAUSEF_IP2)
|
||||
do_IRQ(AR2315_IRQ_MISC);
|
||||
else if (pending & CAUSEF_IP7)
|
||||
@@ -299,10 +303,62 @@ void __init ar2315_plat_mem_setup(void)
|
||||
_machine_restart = ar2315_restart;
|
||||
}
|
||||
|
||||
+#ifdef CONFIG_PCI_AR2315
|
||||
+static struct resource ar2315_pci_res[] = {
|
||||
+ {
|
||||
+ .name = "ar2315-pci-ctrl",
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+ .start = AR2315_PCI_BASE,
|
||||
+ .end = AR2315_PCI_BASE + AR2315_PCI_SIZE - 1,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "ar2315-pci-ext",
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+ .start = AR2315_PCI_EXT_BASE,
|
||||
+ .end = AR2315_PCI_EXT_BASE + AR2315_PCI_EXT_SIZE - 1,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "ar2315-pci",
|
||||
+ .flags = IORESOURCE_IRQ,
|
||||
+ .start = AR2315_IRQ_LCBUS_PCI,
|
||||
+ .end = AR2315_IRQ_LCBUS_PCI,
|
||||
+ },
|
||||
+};
|
||||
+#endif
|
||||
+
|
||||
void __init ar2315_arch_init(void)
|
||||
{
|
||||
unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
|
||||
AR2315_MISC_IRQ_UART0);
|
||||
|
||||
ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
|
||||
+
|
||||
+#ifdef CONFIG_PCI_AR2315
|
||||
+ if (ath25_soc == ATH25_SOC_AR2315) {
|
||||
+ /* Reset PCI DMA logic */
|
||||
+ ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
|
||||
+ msleep(20);
|
||||
+ ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0);
|
||||
+ msleep(20);
|
||||
+
|
||||
+ /* Configure endians */
|
||||
+ ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB |
|
||||
+ AR2315_CONFIG_PCIAHB_BRIDGE);
|
||||
+
|
||||
+ /* Configure as PCI host with DMA */
|
||||
+ ar2315_rst_reg_write(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
|
||||
+ (AR2315_PCICLK_IN_FREQ_DIV_6 <<
|
||||
+ AR2315_PCICLK_DIV_S));
|
||||
+ ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
|
||||
+ ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK |
|
||||
+ AR2315_IF_MASK, AR2315_IF_PCI |
|
||||
+ AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
|
||||
+ (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
|
||||
+ AR2315_IF_PCI_CLK_SHIFT));
|
||||
+
|
||||
+ platform_device_register_simple("ar2315-pci", -1,
|
||||
+ ar2315_pci_res,
|
||||
+ ARRAY_SIZE(ar2315_pci_res));
|
||||
+ }
|
||||
+#endif
|
||||
}
|
||||
|
|
@ -52,9 +52,9 @@
|
|||
if (!ath25_board.radio)
|
||||
--- a/drivers/gpio/Kconfig
|
||||
+++ b/drivers/gpio/Kconfig
|
||||
@@ -112,6 +112,13 @@ config GPIO_MAX730X
|
||||
|
||||
comment "Memory mapped GPIO drivers:"
|
||||
@@ -141,6 +141,13 @@ config GPIO_BRCMSTB
|
||||
help
|
||||
Say yes here to enable GPIO support for Broadcom STB (BCM7XXX) SoCs.
|
||||
|
||||
+config GPIO_AR5312
|
||||
+ bool "AR5312 SoC GPIO support"
|
||||
|
|
@ -68,14 +68,14 @@
|
|||
depends on ARCH_CLPS711X || COMPILE_TEST
|
||||
--- a/drivers/gpio/Makefile
|
||||
+++ b/drivers/gpio/Makefile
|
||||
@@ -17,6 +17,7 @@ obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o
|
||||
obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
|
||||
obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o
|
||||
@@ -21,6 +21,7 @@ obj-$(CONFIG_GPIO_ADP5588) += gpio-adp55
|
||||
obj-$(CONFIG_GPIO_ALTERA) += gpio-altera.o
|
||||
obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
|
||||
obj-$(CONFIG_GPIO_AMDPT) += gpio-amdpt.o
|
||||
+obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o
|
||||
obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
|
||||
obj-$(CONFIG_ATH79) += gpio-ath79.o
|
||||
obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
|
||||
obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/gpio/gpio-ar5312.c
|
||||
@@ -0,0 +1,121 @@
|
||||
|
|
@ -202,7 +202,7 @@
|
|||
+subsys_initcall(ar5312_gpio_init);
|
||||
--- a/arch/mips/Kconfig
|
||||
+++ b/arch/mips/Kconfig
|
||||
@@ -107,6 +107,7 @@ config ATH25
|
||||
@@ -117,6 +117,7 @@ config ATH25
|
||||
select SYS_SUPPORTS_BIG_ENDIAN
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
|
|
@ -75,9 +75,9 @@
|
|||
* workaround. Attempt to jump to the mips reset location -
|
||||
--- a/drivers/gpio/Kconfig
|
||||
+++ b/drivers/gpio/Kconfig
|
||||
@@ -112,6 +112,13 @@ config GPIO_MAX730X
|
||||
|
||||
comment "Memory mapped GPIO drivers:"
|
||||
@@ -141,6 +141,13 @@ config GPIO_BRCMSTB
|
||||
help
|
||||
Say yes here to enable GPIO support for Broadcom STB (BCM7XXX) SoCs.
|
||||
|
||||
+config GPIO_AR2315
|
||||
+ bool "AR2315 SoC GPIO support"
|
||||
|
|
@ -91,14 +91,14 @@
|
|||
default y if SOC_AR5312
|
||||
--- a/drivers/gpio/Makefile
|
||||
+++ b/drivers/gpio/Makefile
|
||||
@@ -17,6 +17,7 @@ obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o
|
||||
obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
|
||||
obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o
|
||||
@@ -21,6 +21,7 @@ obj-$(CONFIG_GPIO_ADP5588) += gpio-adp55
|
||||
obj-$(CONFIG_GPIO_ALTERA) += gpio-altera.o
|
||||
obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o
|
||||
obj-$(CONFIG_GPIO_AMDPT) += gpio-amdpt.o
|
||||
+obj-$(CONFIG_GPIO_AR2315) += gpio-ar2315.o
|
||||
obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o
|
||||
obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o
|
||||
obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
|
||||
obj-$(CONFIG_ATH79) += gpio-ath79.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/gpio/gpio-ar2315.c
|
||||
@@ -0,0 +1,233 @@
|
||||
|
|
@ -162,7 +162,7 @@
|
|||
+ ar2315_gpio_reg_write(reg, (ar2315_gpio_reg_read(reg) & ~mask) | val);
|
||||
+}
|
||||
+
|
||||
+static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
|
||||
+static void ar2315_gpio_irq_handler(struct irq_desc *desc)
|
||||
+{
|
||||
+ u32 pend;
|
||||
+ int bit = -1;
|
||||
|
|
@ -14,9 +14,9 @@
|
|||
- depends on PCI
|
||||
+ depends on (PCI || ATH25)
|
||||
---help---
|
||||
If you have a network (Ethernet) card belonging to this class, say Y
|
||||
and read the Ethernet-HOWTO, available from
|
||||
@@ -80,4 +80,10 @@ config ALX
|
||||
If you have a network (Ethernet) card belonging to this class, say Y.
|
||||
|
||||
@@ -78,4 +78,10 @@ config ALX
|
||||
To compile this driver as a module, choose M here. The module
|
||||
will be called alx.
|
||||
|
||||
|
|
@ -709,7 +709,7 @@
|
|||
+ ar231x_reset_reg(dev);
|
||||
+
|
||||
+ /* Get the IRQ */
|
||||
+ ecode = request_irq(dev->irq, &ar231x_interrupt, IRQF_DISABLED,
|
||||
+ ecode = request_irq(dev->irq, &ar231x_interrupt, 0,
|
||||
+ dev->name, dev);
|
||||
+ if (ecode) {
|
||||
+ printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
|
||||
|
|
@ -20,7 +20,7 @@
|
|||
+obj-$(CONFIG_MTD_AR2315) += ar2315.o
|
||||
obj-$(CONFIG_MTD_BCM47XXSFLASH) += bcm47xxsflash.o
|
||||
obj-$(CONFIG_MTD_ST_SPI_FSM) += st_spi_fsm.o
|
||||
|
||||
obj-$(CONFIG_MTD_POWERNV_FLASH) += powernv_flash.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/mtd/devices/ar2315.c
|
||||
@@ -0,0 +1,459 @@
|
||||
|
|
@ -174,7 +174,7 @@
|
|||
+ return PTR_ERR(wdt_base);
|
||||
+
|
||||
+ ret = devm_request_irq(&dev->dev, irq_res->start, ar2315_wdt_interrupt,
|
||||
+ IRQF_DISABLED, DRIVER_NAME, dev);
|
||||
+ 0, DRIVER_NAME, dev);
|
||||
+ if (ret) {
|
||||
+ dev_err(&dev->dev, "failed to register inetrrupt\n");
|
||||
+ goto out;
|
||||
|
|
@ -212,7 +212,7 @@
|
|||
+MODULE_ALIAS("platform:" DRIVER_NAME);
|
||||
--- a/drivers/watchdog/Kconfig
|
||||
+++ b/drivers/watchdog/Kconfig
|
||||
@@ -1257,6 +1257,13 @@ config RALINK_WDT
|
||||
@@ -1345,6 +1345,13 @@ config RALINK_WDT
|
||||
help
|
||||
Hardware driver for the Ralink SoC Watchdog Timer.
|
||||
|
||||
|
|
@ -228,7 +228,7 @@
|
|||
# POWERPC Architecture
|
||||
--- a/drivers/watchdog/Makefile
|
||||
+++ b/drivers/watchdog/Makefile
|
||||
@@ -138,6 +138,7 @@ obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o
|
||||
@@ -143,6 +143,7 @@ obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
|
||||
obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o
|
||||
obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
|
||||
obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
|
||||
16
target/linux/ath25/profiles/00-default.mk
Normal file
16
target/linux/ath25/profiles/00-default.mk
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
#
|
||||
# Copyright (C) 2011 OpenWrt.org
|
||||
#
|
||||
# This is free software, licensed under the GNU General Public License v2.
|
||||
# See /LICENSE for more information.
|
||||
#
|
||||
|
||||
define Profile/Default
|
||||
NAME:=Default Profile
|
||||
PRIORITY:=1
|
||||
endef
|
||||
|
||||
define Profile/Default/Description
|
||||
Default package set compatible with most boards.
|
||||
endef
|
||||
$(eval $(call Profile,Default))
|
||||
Loading…
Reference in a new issue