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ath79: dev-eth: fix QCA9561 set phy interface mode and mask

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QCA9563 and QCA9561 are two series of Qualcomm SoC Dragonfly. The only different
is QCA9563 w/o internal switch. It has one GMAC with SGMII interface. But they
have the same device ID(0x1150). So they share the same codes.

Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>

SVN-Revision: 46971
This commit is contained in:
John Crispin 2015-09-16 08:33:04 +00:00
parent fa09d76521
commit f6607a4bec
1 changed files with 7 additions and 2 deletions
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9
target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
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@ -633,7 +633,6 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
case ATH79_SOC_AR9330:
case ATH79_SOC_AR9331:
case ATH79_SOC_QCA9533:
case ATH79_SOC_QCA9561:
case ATH79_SOC_TP9343:
pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
break;
@ -667,6 +666,11 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
}
break;
case ATH79_SOC_QCA9561:
if (!pdata->phy_if_mode)
pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
break;
default:
BUG();
}
@ -1035,7 +1039,8 @@ void __init ath79_register_eth(unsigned int id)
AR933X_RESET_GE0_MDIO;
pdata->set_speed = ath79_set_speed_dummy;
pdata->phy_mask = BIT(4);
if (!pdata->phy_mask)
pdata->phy_mask = BIT(4);
} else {
pdata->reset_bit = AR933X_RESET_GE1_MAC |
AR933X_RESET_GE1_MDIO;