mediatek: update patches

* fixes NAND
* adds latest ethernet patches

Signed-off-by: John Crispin <john@phrozen.org>

target/linux/mediatek/Makefile

@@ -5,7 +5,7 @@ include $(TOPDIR)/rules.mk
 ARCH:=arm
 BOARD:=mediatek
 BOARDNAME:=Mediatek Ralink ARM
-FEATURES:=squashfs
+FEATURES:=squashfs jffs2
 CPU_TYPE:=cortex-a7
 MAINTAINER:=John Crispin <john@phrozen.org>
 

target/linux/mediatek/base-files/etc/board.d/02_network

@@ -10,6 +10,8 @@ mediatek_setup_interfaces()
 	local board="$1"
 
 	case $board in
+	eMMC | \
+	NAND | \
 	mt7623_evb)
 		ucidef_set_interfaces_lan_wan "eth0" "eth1"
 		ucidef_add_switch "switch0" \

target/linux/mediatek/config-4.4

@@ -296,9 +296,10 @@ CONFIG_MODULES_USE_ELF_REL=y
 CONFIG_MTD_BLOCK2MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_MT81xx_NOR=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_MTKSDG1=y
+CONFIG_MTD_NAND_MTK=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTK_INFRACFG=y
 CONFIG_MTK_PMIC_WRAP=y
@@ -406,6 +407,10 @@ CONFIG_PREEMPT_COUNT=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_RCU=y
 CONFIG_PRINTK_TIME=y
+CONFIG_PWM=y
+CONFIG_PWM_MEDIATEK=y
+# CONFIG_PWM_MTK_DISP is not set
+CONFIG_PWM_SYSFS=y
 CONFIG_RATIONAL=y
 CONFIG_RCU_CPU_STALL_TIMEOUT=21
 # CONFIG_RCU_EXPERT is not set

target/linux/mediatek/files/arch/arm/boot/dts/_mt7623.dtsi

@@ -0,0 +1,615 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: John Crispin <blogic@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt2701-clk.h>
+#include <dt-bindings/power/mt2701-power.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/reset-controller/mt2701-resets.h>
+#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
+#include "skeleton64.dtsi"
+
+
+/ {
+	compatible = "mediatek,mt7623";
+	interrupt-parent = <&sysirq>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "mediatek,mt6589-smp";
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x0>;
+			clocks = <&infracfg CLK_INFRA_CPUSEL>,
+				 <&apmixedsys CLK_APMIXED_MAINPLL>;
+			clock-names = "cpu", "intermediate";
+			operating-points = <
+				598000 1150000
+				747500 1150000
+				1040000 1150000
+				1196000 1200000
+				1300000 1300000
+			>;
+		};
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x1>;
+			clocks = <&infracfg CLK_INFRA_CPUSEL>,
+				 <&apmixedsys CLK_APMIXED_MAINPLL>;
+			clock-names = "cpu", "intermediate";
+			operating-points = <
+				598000 1150000
+				747500 1150000
+				1040000 1150000
+				1196000 1200000
+				1300000 1300000
+			>;
+		};
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x2>;
+			clocks = <&infracfg CLK_INFRA_CPUSEL>,
+				 <&apmixedsys CLK_APMIXED_MAINPLL>;
+			clock-names = "cpu", "intermediate";
+			operating-points = <
+				598000 1150000
+				747500 1150000
+				1040000 1150000
+				1196000 1200000
+				1300000 1300000
+			>;
+		};
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x3>;
+			clocks = <&infracfg CLK_INFRA_CPUSEL>,
+				 <&apmixedsys CLK_APMIXED_MAINPLL>;
+			clock-names = "cpu", "intermediate";
+			operating-points = <
+				598000 1150000
+				747500 1150000
+				1040000 1150000
+				1196000 1200000
+				1300000 1300000
+			>;
+		};
+	};
+
+	system_clk: dummy13m {
+		compatible = "fixed-clock";
+		clock-frequency = <13000000>;
+		#clock-cells = <0>;
+	};
+
+	rtc_clk: dummy32k {
+		compatible = "fixed-clock";
+		clock-frequency = <32000>;
+		#clock-cells = <0>;
+		clock-output-names = "clk32k";
+	};
+
+	clk26m: dummy26m {
+		compatible = "fixed-clock";
+		clock-frequency = <26000000>;
+		#clock-cells = <0>;
+		clock-output-names = "clk26m";
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		clock-frequency = <13000000>;
+		arm,cpu-registers-not-fw-configured;
+	};
+
+	topckgen: power-controller@10000000 {
+		compatible = "mediatek,mt7623-topckgen",
+			     "mediatek,mt2701-topckgen",
+			     "syscon";
+		reg = <0 0x10000000 0 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	infracfg: power-controller@10001000 {
+		compatible = "mediatek,mt7623-infracfg",
+			     "mediatek,mt2701-infracfg",
+			     "syscon";
+		reg = <0 0x10001000 0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	pericfg: pericfg@10003000 {
+		compatible = "mediatek,mt7623-pericfg",
+			     "mediatek,mt2701-pericfg",
+			     "syscon";
+		reg = <0 0x10003000 0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	pio: pinctrl@10005000 {
+		compatible = "mediatek,mt7623-pinctrl";
+		reg = <0 0x1000b000 0 0x1000>;
+		mediatek,pctl-regmap = <&syscfg_pctl_a>;
+		pins-are-numbered;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <2>;
+		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	syscfg_pctl_a: syscfg@10005000 {
+		compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
+		reg = <0 0x10005000 0 0x1000>;
+	};
+
+	scpsys: scpsys@10006000 {
+		#power-domain-cells = <1>;
+		compatible = "mediatek,mt7623-scpsys",
+			     "mediatek,mt2701-scpsys";
+		reg = <0 0x10006000 0 0x1000>;
+		infracfg = <&infracfg>;
+		clocks = <&clk26m>,
+			 <&topckgen CLK_TOP_MM_SEL>;
+		clock-names = "mfg", "mm";
+	};
+
+	watchdog: watchdog@10007000 {
+		compatible = "mediatek,mt7623-wdt",
+			     "mediatek,mt6589-wdt";
+		reg = <0 0x10007000 0 0x100>;
+	};
+
+	timer: timer@10008000 {
+		compatible = "mediatek,mt7623-timer",
+			     "mediatek,mt6577-timer";
+		reg = <0 0x10008000 0 0x80>;
+		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&system_clk>, <&rtc_clk>;
+		clock-names = "system-clk", "rtc-clk";
+	};
+
+	pwrap: pwrap@1000d000 {
+		compatible = "mediatek,mt7623-pwrap",
+			     "mediatek,mt2701-pwrap";
+		reg = <0 0x1000d000 0 0x1000>;
+		reg-names = "pwrap";
+		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+		resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
+		reset-names = "pwrap";
+		clocks = <&infracfg CLK_INFRA_PMICSPI>,
+			 <&infracfg CLK_INFRA_PMICWRAP>;
+		clock-names = "spi", "wrap";
+	};
+
+	sysirq: interrupt-controller@10200100 {
+		compatible = "mediatek,mt7623-sysirq",
+			     "mediatek,mt6577-sysirq";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+		reg = <0 0x10200100 0 0x1c>;
+	};
+
+	apmixedsys: apmixedsys@10209000 {
+		compatible = "mediatek,mt7623-apmixedsys",
+			     "mediatek,mt2701-apmixedsys";
+		reg = <0 0x10209000 0 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	gic: interrupt-controller@10211000 {
+		compatible = "arm,cortex-a7-gic";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+		reg = <0 0x10211000 0 0x1000>,
+		      <0 0x10212000 0 0x1000>,
+		      <0 0x10214000 0 0x2000>,
+		      <0 0x10216000 0 0x2000>;
+	};
+
+	i2c0: i2c@11007000 {
+		compatible = "mediatek,mt7623-i2c",
+			     "mediatek,mt6577-i2c";
+		reg = <0 0x11007000 0 0x70>,
+		      <0 0x11000200 0 0x80>;
+		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
+		clock-div = <16>;
+		clocks = <&pericfg CLK_PERI_I2C0>,
+			 <&pericfg CLK_PERI_AP_DMA>;
+		clock-names = "main", "dma";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@11008000 {
+		compatible = "mediatek,mt7623-i2c",
+			     "mediatek,mt6577-i2c";
+		reg = <0 0x11008000 0 0x70>,
+		      <0 0x11000280 0 0x80>;
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
+		clock-div = <16>;
+		clocks = <&pericfg CLK_PERI_I2C1>,
+			 <&pericfg CLK_PERI_AP_DMA>;
+		clock-names = "main", "dma";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@11009000 {
+		compatible = "mediatek,mt7623-i2c",
+			     "mediatek,mt6577-i2c";
+		reg = <0 0x11009000 0 0x70>,
+		      <0 0x11000300 0 0x80>;
+		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
+		clock-div = <16>;
+		clocks = <&pericfg CLK_PERI_I2C2>,
+			 <&pericfg CLK_PERI_AP_DMA>;
+		clock-names = "main", "dma";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	uart0: serial@11002000 {
+		compatible = "mediatek,mt7623-uart",
+			     "mediatek,mt6577-uart";
+		reg = <0 0x11002000 0 0x400>;
+		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_UART0_SEL>,
+			 <&pericfg CLK_PERI_UART0>;
+		clock-names = "baud", "bus";
+		status = "disabled";
+	};
+
+	uart1: serial@11003000 {
+		compatible = "mediatek,mt7623-uart",
+			     "mediatek,mt6577-uart";
+		reg = <0 0x11003000 0 0x400>;
+		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_UART1_SEL>,
+			 <&pericfg CLK_PERI_UART1>;
+		clock-names = "baud", "bus";
+		status = "disabled";
+	};
+
+	uart2: serial@11004000 {
+		compatible = "mediatek,mt7623-uart",
+			     "mediatek,mt6577-uart";
+		reg = <0 0x11004000 0 0x400>;
+		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_UART2_SEL>,
+			 <&pericfg CLK_PERI_UART2>;
+		clock-names = "baud", "bus";
+		status = "disabled";
+	};
+
+	uart3: serial@11005000 {
+		compatible = "mediatek,mt7623-uart",
+			     "mediatek,mt6577-uart";
+		reg = <0 0x11005000 0 0x400>;
+		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_UART3_SEL>,
+			 <&pericfg CLK_PERI_UART3>;
+		clock-names = "baud", "bus";
+		status = "disabled";
+	};
+
+	pwm: pwm@11006000 {
+		compatible = "mediatek,mt7623-pwm";
+	
+		reg = <0 0x11006000 0 0x1000>;
+		
+		resets = <&pericfg MT2701_PERI_PWM_SW_RST>;
+		reset-names = "pwm";
+
+		#pwm-cells = <2>;
+		clocks = <&topckgen CLK_TOP_PWM_SEL>,
+			 <&pericfg CLK_PERI_PWM>,
+			 <&pericfg CLK_PERI_PWM1>,
+			 <&pericfg CLK_PERI_PWM2>,
+			 <&pericfg CLK_PERI_PWM3>,
+			 <&pericfg CLK_PERI_PWM4>,
+			 <&pericfg CLK_PERI_PWM5>;
+		clock-names = "top", "main", "pwm1", "pwm2",
+			      "pwm3", "pwm4", "pwm5";
+	
+		status = "disabled";
+	};
+
+	spi: spi@1100a000 {
+		compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
+		reg = <0 0x1100a000 0 0x1000>;
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_SPI0>;
+		clock-names = "main";
+
+		status = "disabled";
+	};
+
+	nandc: nfi@1100d000 {
+		compatible = "mediatek,mt2701-nfc";
+		reg = <0 0x1100d000 0 0x1000>;
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_NFI>,
+			 <&pericfg CLK_PERI_NFI_PAD>;
+		clock-names = "nfi_clk", "pad_clk";
+		status = "disabled";
+		ecc-engine = <&bch>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	bch: ecc@1100e000 {
+		compatible = "mediatek,mt2701-ecc";
+		reg = <0 0x1100e000 0 0x1000>;
+		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_NFI_ECC>;
+		clock-names = "nfiecc_clk";
+		status = "disabled";
+	};
+
+	mmc0: mmc@11230000 {
+		compatible = "mediatek,mt7623-mmc",
+			     "mediatek,mt8135-mmc";
+		reg = <0 0x11230000 0 0x1000>;
+		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_MSDC30_0>,
+			 <&topckgen CLK_TOP_MSDC30_0_SEL>;
+		clock-names = "source", "hclk";
+		status = "disabled";
+	};
+
+	mmc1: mmc@11240000 {
+		compatible = "mediatek,mt7623-mmc",
+			     "mediatek,mt8135-mmc";
+		reg = <0 0x11240000 0 0x1000>;
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&pericfg CLK_PERI_MSDC30_1>,
+			 <&topckgen CLK_TOP_MSDC30_1_SEL>;
+		clock-names = "source", "hclk";
+		status = "disabled";
+	};
+
+	usb1: usb@1a1c0000 {
+		compatible = "mediatek,mt2701-xhci",
+			     "mediatek,mt8173-xhci";
+		reg = <0 0x1a1c0000 0 0x1000>,
+		      <0 0x1a1c4700 0 0x0100>;
+		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
+			 <&topckgen CLK_TOP_ETHIF_SEL>;
+		clock-names = "sys_ck", "ethif";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+		phys = <&phy_port0 PHY_TYPE_USB3>;
+		status = "disabled";
+	};
+
+	u3phy1: usb-phy@1a1c4000 {
+		compatible = "mediatek,mt2701-u3phy",
+			     "mediatek,mt8173-u3phy";
+		reg = <0 0x1a1c4000 0 0x0700>;
+		clocks = <&clk26m>;
+		clock-names = "u3phya_ref";
+		#phy-cells = <1>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+
+		phy_port0: phy_port0: port@1a1c4800 {
+			reg = <0 0x1a1c4800 0 0x800>;
+			#phy-cells = <1>;
+			status = "okay";
+		};
+	};
+
+	usb2: usb@1a240000 {
+		compatible = "mediatek,mt2701-xhci",
+			     "mediatek,mt8173-xhci";
+		reg = <0 0x1a240000 0 0x1000>,
+		      <0 0x1a244700 0 0x0100>;
+		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
+		clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
+			 <&topckgen CLK_TOP_ETHIF_SEL>;
+		clock-names = "sys_ck", "ethif";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+		phys = <&u3phy2 0>;
+		status = "disabled";
+	};
+
+	u3phy2: usb-phy@1a244000 {
+		compatible = "mediatek,mt2701-u3phy",
+			     "mediatek,mt8173-u3phy";
+		reg = <0 0x1a244000 0 0x0700>,
+		      <0 0x1a244800 0 0x0800>;
+		clocks = <&clk26m>;
+		clock-names = "u3phya_ref";
+		#phy-cells = <1>;
+		status = "disabled";
+	};
+
+	hifsys: clock-controller@1a000000 {
+		compatible = "mediatek,mt7623-hifsys",
+			     "mediatek,mt2701-hifsys",
+			     "syscon";
+		reg = <0 0x1a000000 0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	pcie: pcie@1a140000 {
+		compatible = "mediatek,mt7623-pcie";
+		device_type = "pci";
+		reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
+		      <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
+		      <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
+		      <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
+		reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
+		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "pcie0", "pcie1", "pcie2";
+		clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
+		clock-names = "pcie";
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+		resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
+			 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
+			 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
+		reset-names = "pcie0", "pcie1", "pcie2";
+
+		mediatek,hifsys = <&hifsys>;
+
+		bus-range = <0x00 0xff>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
+			  0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
+
+		status = "disabled";
+
+		pcie@1,0 {
+			device_type = "pci";
+			reg = <0x0800 0 0 0 0>;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+		};
+
+		pcie@2,0{
+			device_type = "pci";
+			reg = <0x1000 0 0 0 0>;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+		};
+
+		pcie@3,0{
+			device_type = "pci";
+			reg = <0x1800 0 0 0 0>;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+		};
+	};
+
+	ethsys: syscon@1b000000 {
+		compatible = "mediatek,mt2701-ethsys", "syscon";
+		reg = <0 0x1b000000 0 0x1000>;
+		#reset-cells = <1>;
+		#clock-cells = <1>;
+	};
+
+	eth: ethernet@1b100000 {
+		compatible = "mediatek,mt7623-eth";
+		reg = <0 0x1b100000 0 0x20000>;
+	
+		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+			 <&ethsys CLK_ETHSYS_ESW>,
+			 <&ethsys CLK_ETHSYS_GP2>,
+			 <&ethsys CLK_ETHSYS_GP1>;
+		clock-names = "ethif", "esw", "gp2", "gp1";
+		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
+			      GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
+			      GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
+		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+
+		resets = <&ethsys 6>;
+		reset-names = "eth";
+
+		mediatek,ethsys = <&ethsys>;
+		mediatek,pctl = <&syscfg_pctl_a>;
+
+		mediatek,switch = <&gsw>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+	
+		status = "disabled";
+
+		gmac1: mac@0 {
+			compatible = "mediatek,eth-mac";
+			reg = <0>;
+
+			status = "disabled";
+			
+			phy-mode = "rgmii";
+			
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+				pause;
+			};
+		};
+
+		gmac2: mac@1 {
+			compatible = "mediatek,eth-mac";
+			reg = <1>;
+
+			status = "disabled";
+		};
+	
+		mdio-bus {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			phy5: ethernet-phy@5 {
+				reg = <5>;
+				phy-mode = "rgmii-rxid";
+			};
+
+			phy1f: ethernet-phy@1f {
+				reg = <0x1f>;
+				phy-mode = "rgmii";
+			};
+		};
+	};
+
+	gsw: switch@1b100000 {
+		compatible = "mediatek,mt7623-gsw";
+		interrupt-parent = <&pio>;
+		interrupts = <168 IRQ_TYPE_EDGE_RISING>;
+		resets = <&ethsys 2>;
+		reset-names = "eth";
+		clocks = <&apmixedsys CLK_APMIXED_TRGPLL>;
+		clock-names = "trgpll";
+		mt7530-supply = <&mt6323_vpa_reg>;
+		mediatek,pctl-regmap = <&syscfg_pctl_a>;
+		mediatek,ethsys = <&ethsys>;
+		status = "disabled";
+	};
+};

target/linux/mediatek/files/arch/arm/boot/dts/mt7623-NAND.dts

@@ -14,11 +14,11 @@
 
 /dts-v1/;
 
-#include "mt7623.dtsi"
+#include "_mt7623.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 
 / {
-	model = "MediaTek MT7623 evaluation board";
+	model = "MediaTek MT7623 NAND evaluation board";
 	compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
 
 	chosen {
@@ -341,6 +341,16 @@
 			output-low;
 		};
 	};
+
+	pwm_pins: pwm {
+		pins_pwm1 {
+			pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>;
+		};
+
+		pins_pwm2 {
+			pinmux = <MT7623_PIN_205_PWM2_FUNC_PWM2>;
+		};
+	};
 };
 
 &nandc {
@@ -416,6 +426,14 @@
 &gmac2 {
 	mac-address = [00 11 22 33 44 55];
 	status = "okay";
+
+	phy-mode = "rgmii";
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+		pause;
+	};
 };
 
 &gsw {
@@ -424,3 +442,9 @@
 	mediatek,reset-pin = <&pio 15 0>;
 	status = "okay";
 };
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
+	status = "okay";
+};

target/linux/mediatek/files/arch/arm/boot/dts/mt7623-eMMC.dts

@@ -14,7 +14,7 @@
 
 /dts-v1/;
 
-#include "mt7623.dtsi"
+#include "_mt7623.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -436,6 +436,16 @@
 			output-low;
 		};
 	};
+
+	pwm_pins: pwm {
+		pins_pwm1 {
+			pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>;
+		};
+
+		pins_pwm2 {
+			pinmux = <MT7623_PIN_205_PWM2_FUNC_PWM2>;
+		};
+	};
 };
 
 &usb1 {
@@ -464,6 +474,7 @@
 &gmac2 {
 	mac-address = [00 11 22 33 44 55];
 	status = "okay";
+	phy-handle = <&phy5>;
 };
 
 &gsw {
@@ -472,3 +483,9 @@
 	mediatek,reset-pin = <&pio 15 0>;
 	status = "okay";
 };
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
+	status = "okay";
+};

target/linux/mediatek/image/Makefile

@@ -17,7 +17,7 @@ ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
 endif
 	mkdir -p "$(KDIR_TMP)/sysupgrade-$(1)/"
 	echo "BOARD=$(1)" > "$(KDIR_TMP)/sysupgrade-$(1)/CONTROL"
-	$(CP) "$(KDIR)/root.squashfs" "$(KDIR_TMP)/sysupgrade-$(1)/root"
+	$(CP) "$(KDIR)/root.$(2)" "$(KDIR_TMP)/sysupgrade-$(1)/root"
 	$(CP) "$(KDIR)/uImage-$(1)" "$(KDIR_TMP)/sysupgrade-$(1)/kernel"
 	(cd "$(KDIR_TMP)"; $(TAR) cvf \
 		"$(BIN_DIR)/$(IMG_PREFIX)-$(1)-sysupgrade.tar" sysupgrade-$(1) \
@@ -29,8 +29,13 @@ define Image/Build/squashfs
 	$(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
 	$(CP) $(KDIR)/root.squashfs $(BIN_DIR)/$(IMG_PREFIX)-root.squashfs
 
-	$(call Image/Build/SysupgradeCombined,eMMC)
+	$(call Image/Build/SysupgradeCombined,eMMC,squashfs)
-	$(call Image/Build/SysupgradeCombined,NAND)
+endef
+
+define Image/Build/jffs2-128k
+	$(CP) $(KDIR)/root.jffs2-128k $(BIN_DIR)/$(IMG_PREFIX)-root.jffs2
+
+	$(call Image/Build/SysupgradeCombined,NAND,jffs2-128k)
 endef
 
 define Image/Build

target/linux/mediatek/patches-4.4/0001-NET-multi-phy-support.patch

@@ -1,7 +1,7 @@
-From c30a296646a42302065ba452abe95b0b4b550883 Mon Sep 17 00:00:00 2001
+From 1e021917e634b173d466bf0dd3d2ae84e51a77ff Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 27 Jul 2014 09:38:50 +0100
-Subject: [PATCH 01/91] NET: multi phy support
+Subject: [PATCH 001/102] NET: multi phy support
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
@@ -9,9 +9,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  include/linux/phy.h   |    1 +
  2 files changed, 7 insertions(+), 3 deletions(-)
 
+diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
+index 47cd306d..f69d12f 100644
 --- a/drivers/net/phy/phy.c
 +++ b/drivers/net/phy/phy.c
-@@ -888,7 +888,8 @@ void phy_state_machine(struct work_struc
+@@ -844,7 +844,8 @@ void phy_state_machine(struct work_struct *work)
  		/* If the link is down, give up on negotiation for now */
  		if (!phydev->link) {
  			phydev->state = PHY_NOLINK;
@@ -21,7 +23,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  			phydev->adjust_link(phydev->attached_dev);
  			break;
  		}
-@@ -971,7 +972,8 @@ void phy_state_machine(struct work_struc
+@@ -927,7 +928,8 @@ void phy_state_machine(struct work_struct *work)
  			netif_carrier_on(phydev->attached_dev);
  		} else {
  			phydev->state = PHY_NOLINK;
@@ -31,7 +33,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		}
  
  		phydev->adjust_link(phydev->attached_dev);
-@@ -983,7 +985,8 @@ void phy_state_machine(struct work_struc
+@@ -939,7 +941,8 @@ void phy_state_machine(struct work_struct *work)
  	case PHY_HALTED:
  		if (phydev->link) {
  			phydev->link = 0;
@@ -41,6 +43,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  			phydev->adjust_link(phydev->attached_dev);
  			do_suspend = true;
  		}
+diff --git a/include/linux/phy.h b/include/linux/phy.h
+index 05fde31..276ab8a 100644
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
 @@ -377,6 +377,7 @@ struct phy_device {
@@ -51,3 +55,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	enum phy_state state;
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0002-soc-mediatek-Separate-scpsys-driver-common-code.patch

@@ -1,7 +1,7 @@
-From 2c93328ed05061a50e3bd4111379dbcf6946d3ac Mon Sep 17 00:00:00 2001
+From 1892fcf687116720d07135c83d489a23ec56a166 Mon Sep 17 00:00:00 2001
 From: James Liao <jamesjj.liao@mediatek.com>
 Date: Wed, 30 Dec 2015 14:41:43 +0800
-Subject: [PATCH 02/91] soc: mediatek: Separate scpsys driver common code
+Subject: [PATCH 002/102] soc: mediatek: Separate scpsys driver common code
 
 Separate scpsys driver common code to mtk-scpsys.c, and move MT8173
 platform code to mtk-scpsys-mt8173.c.
@@ -17,6 +17,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  create mode 100644 drivers/soc/mediatek/mtk-scpsys-mt8173.c
  create mode 100644 drivers/soc/mediatek/mtk-scpsys.h
 
+diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
+index 0a4ea80..eca6fb7 100644
 --- a/drivers/soc/mediatek/Kconfig
 +++ b/drivers/soc/mediatek/Kconfig
 @@ -22,11 +22,20 @@ config MTK_PMIC_WRAP
@@ -42,6 +44,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +	  driver.
 +	  The System Control Processor System (SCPSYS) has several power
 +	  management related tasks in the system.
+diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
+index 12998b0..3b22baa 100644
 --- a/drivers/soc/mediatek/Makefile
 +++ b/drivers/soc/mediatek/Makefile
 @@ -1,3 +1,4 @@
@@ -49,6 +53,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
 +obj-$(CONFIG_MTK_SCPSYS_MT8173) += mtk-scpsys-mt8173.o
+diff --git a/drivers/soc/mediatek/mtk-scpsys-mt8173.c b/drivers/soc/mediatek/mtk-scpsys-mt8173.c
+new file mode 100644
+index 0000000..3c7b569
 --- /dev/null
 +++ b/drivers/soc/mediatek/mtk-scpsys-mt8173.c
 @@ -0,0 +1,179 @@
@@ -231,6 +238,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +};
 +
 +module_platform_driver_probe(scpsys_drv, scpsys_probe);
+diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
+index 4d4203c..a0943c5 100644
 --- a/drivers/soc/mediatek/mtk-scpsys.c
 +++ b/drivers/soc/mediatek/mtk-scpsys.c
 @@ -11,28 +11,14 @@
@@ -248,7 +257,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 -#include <linux/regmap.h>
  #include <linux/soc/mediatek/infracfg.h>
 -#include <dt-bindings/power/mt8173-power.h>
- 
+-
 -#define SPM_VDE_PWR_CON			0x0210
 -#define SPM_MFG_PWR_CON			0x0214
 -#define SPM_VEN_PWR_CON			0x0230
@@ -259,6 +268,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 -#define SPM_MFG_2D_PWR_CON		0x02c0
 -#define SPM_MFG_ASYNC_PWR_CON		0x02c4
 -#define SPM_USB_PWR_CON			0x02cc
++
 +#include "mtk-scpsys.h"
 +
  #define SPM_PWR_STATUS			0x060c
@@ -418,7 +428,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  static int scpsys_domain_is_on(struct scp_domain *scpd)
  {
  	struct scp *scp = scpd->scp;
-@@ -398,63 +237,89 @@ static bool scpsys_active_wakeup(struct
+@@ -398,63 +237,89 @@ static bool scpsys_active_wakeup(struct device *dev)
  	return scpd->active_wakeup;
  }
  
@@ -508,13 +518,13 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +		return ERR_PTR(-ENOMEM);
 +
 +	pd_data = &scp->pd_data;
- 
++
--	for (i = 0; i < NUM_DOMAINS; i++) {
 +	pd_data->domains = devm_kzalloc(&pdev->dev,
 +			sizeof(*pd_data->domains) * num, GFP_KERNEL);
 +	if (!pd_data->domains)
 +		return ERR_PTR(-ENOMEM);
-+
+ 
+-	for (i = 0; i < NUM_DOMAINS; i++) {
 +	pd_data->num_domains = num;
 +
 +	init_clks(pdev, clk);
@@ -539,7 +549,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  		pd_data->domains[i] = genpd;
  		scpd->scp = scp;
  
-@@ -464,13 +329,25 @@ static int __init scpsys_probe(struct pl
+@@ -464,13 +329,25 @@ static int __init scpsys_probe(struct platform_device *pdev)
  		scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;
  		scpd->bus_prot_mask = data->bus_prot_mask;
  		scpd->active_wakeup = data->active_wakeup;
@@ -567,7 +577,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  
  		/*
  		 * Initially turn on all domains to make the domains usable
-@@ -489,37 +366,9 @@ static int __init scpsys_probe(struct pl
+@@ -489,37 +366,9 @@ static int __init scpsys_probe(struct platform_device *pdev)
  	 * valid.
  	 */
  
@@ -606,6 +616,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 -};
 -
 -module_platform_driver_probe(scpsys_drv, scpsys_probe);
+diff --git a/drivers/soc/mediatek/mtk-scpsys.h b/drivers/soc/mediatek/mtk-scpsys.h
+new file mode 100644
+index 0000000..466728d
 --- /dev/null
 +++ b/drivers/soc/mediatek/mtk-scpsys.h
 @@ -0,0 +1,54 @@
@@ -663,3 +676,6 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +				struct scp *scp, int num);
 +
 +#endif /* __DRV_SOC_MTK_H */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0003-soc-mediatek-Init-MT8173-scpsys-driver-earlier.patch

@@ -1,7 +1,7 @@
-From c359272f86805259c5801385d60fdeea9d629cf9 Mon Sep 17 00:00:00 2001
+From 6f87948c3a58f02f6a64eadda719317016739d5e Mon Sep 17 00:00:00 2001
 From: James Liao <jamesjj.liao@mediatek.com>
 Date: Wed, 30 Dec 2015 14:41:44 +0800
-Subject: [PATCH 03/91] soc: mediatek: Init MT8173 scpsys driver earlier
+Subject: [PATCH 003/102] soc: mediatek: Init MT8173 scpsys driver earlier
 
 Some power domain comsumers may init before module_init.
 So the power domain provider (scpsys) need to be initialized
@@ -12,9 +12,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  drivers/soc/mediatek/mtk-scpsys-mt8173.c |   13 ++++++++++++-
  1 file changed, 12 insertions(+), 1 deletion(-)
 
+diff --git a/drivers/soc/mediatek/mtk-scpsys-mt8173.c b/drivers/soc/mediatek/mtk-scpsys-mt8173.c
+index 3c7b569..827e696 100644
 --- a/drivers/soc/mediatek/mtk-scpsys-mt8173.c
 +++ b/drivers/soc/mediatek/mtk-scpsys-mt8173.c
-@@ -176,4 +176,15 @@ static struct platform_driver scpsys_drv
+@@ -176,4 +176,15 @@ static struct platform_driver scpsys_drv = {
  	},
  };
  
@@ -31,3 +33,6 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +
 +subsys_initcall(scpsys_drv_init);
 +module_exit(scpsys_drv_exit);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0004-soc-mediatek-Add-MT2701-power-dt-bindings.patch

@@ -1,7 +1,7 @@
-From f371844374fff273f817d6c43f679606417af59e Mon Sep 17 00:00:00 2001
+From 7c5b29de78f1b15c5bde40a6ca4510fc09588457 Mon Sep 17 00:00:00 2001
 From: Shunli Wang <shunli.wang@mediatek.com>
 Date: Wed, 30 Dec 2015 14:41:45 +0800
-Subject: [PATCH 04/91] soc: mediatek: Add MT2701 power dt-bindings
+Subject: [PATCH 004/102] soc: mediatek: Add MT2701 power dt-bindings
 
 Add power dt-bindings for MT2701.
 
@@ -12,6 +12,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  1 file changed, 27 insertions(+)
  create mode 100644 include/dt-bindings/power/mt2701-power.h
 
+diff --git a/include/dt-bindings/power/mt2701-power.h b/include/dt-bindings/power/mt2701-power.h
+new file mode 100644
+index 0000000..64cc826
 --- /dev/null
 +++ b/include/dt-bindings/power/mt2701-power.h
 @@ -0,0 +1,27 @@
@@ -42,3 +45,6 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +#define MT2701_POWER_DOMAIN_IFR_MSC	8
 +
 +#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0005-soc-mediatek-Add-MT2701-MT7623-scpsys-driver.patch

@@ -1,7 +1,7 @@
-From c6711565985f359d7d3c05f01f081e4c216902de Mon Sep 17 00:00:00 2001
+From 8aa49d107d8a22fd6cbf37174614baf32d0976e2 Mon Sep 17 00:00:00 2001
 From: Shunli Wang <shunli.wang@mediatek.com>
 Date: Wed, 30 Dec 2015 14:41:46 +0800
-Subject: [PATCH 05/91] soc: mediatek: Add MT2701/MT7623 scpsys driver
+Subject: [PATCH 005/102] soc: mediatek: Add MT2701/MT7623 scpsys driver
 
 Add scpsys driver for MT2701 and MT7623.
 
@@ -14,6 +14,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  3 files changed, 173 insertions(+)
  create mode 100644 drivers/soc/mediatek/mtk-scpsys-mt2701.c
 
+diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
+index eca6fb7..92cf838 100644
 --- a/drivers/soc/mediatek/Kconfig
 +++ b/drivers/soc/mediatek/Kconfig
 @@ -39,3 +39,14 @@ config MTK_SCPSYS_MT8173
@@ -31,13 +33,18 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +	  domain driver.
 +	  The System Control Processor System (SCPSYS) has several power
 +	  management related tasks in the system.
+diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
+index 3b22baa..822986d 100644
 --- a/drivers/soc/mediatek/Makefile
 +++ b/drivers/soc/mediatek/Makefile
-@@ -2,3 +2,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infrac
+@@ -2,3 +2,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
  obj-$(CONFIG_MTK_SCPSYS_MT8173) += mtk-scpsys-mt8173.o
 +obj-$(CONFIG_MTK_SCPSYS_MT2701) += mtk-scpsys-mt2701.o
+diff --git a/drivers/soc/mediatek/mtk-scpsys-mt2701.c b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
+new file mode 100644
+index 0000000..339d5b8
 --- /dev/null
 +++ b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
 @@ -0,0 +1,161 @@
@@ -202,3 +209,6 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +
 +MODULE_DESCRIPTION("MediaTek MT2701 scpsys driver");
 +MODULE_LICENSE("GPL v2");
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0006-clk-mediatek-Refine-the-makefile-to-support-multiple.patch

@@ -1,8 +1,8 @@
-From 0c39bcd17fa6ce723f56ad3756b4bb36c4690342 Mon Sep 17 00:00:00 2001
+From 69d4e250847f82a5896c41bcb5f1e793c5a8fbac Mon Sep 17 00:00:00 2001
 From: James Liao <jamesjj.liao@mediatek.com>
 Date: Tue, 5 Jan 2016 14:30:17 +0800
-Subject: [PATCH 06/91] clk: mediatek: Refine the makefile to support multiple
+Subject: [PATCH 006/102] clk: mediatek: Refine the makefile to support
- clock drivers
+ multiple clock drivers
 
 Add a Kconfig to define clock configuration for each SoC, and
 modify the Makefile to build drivers that only selected in config.
@@ -16,6 +16,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  3 files changed, 27 insertions(+), 3 deletions(-)
  create mode 100644 drivers/clk/mediatek/Kconfig
 
+diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
+index c3e3a02..b7a37dc 100644
 --- a/drivers/clk/Kconfig
 +++ b/drivers/clk/Kconfig
 @@ -198,3 +198,4 @@ source "drivers/clk/mvebu/Kconfig"
@@ -23,6 +25,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  source "drivers/clk/samsung/Kconfig"
  source "drivers/clk/tegra/Kconfig"
 +source "drivers/clk/mediatek/Kconfig"
+diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
+new file mode 100644
+index 0000000..dc224e6
 --- /dev/null
 +++ b/drivers/clk/mediatek/Kconfig
 @@ -0,0 +1,23 @@
@@ -49,6 +54,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +	default ARCH_MEDIATEK
 +	---help---
 +	  This driver supports Mediatek MT8173 clocks.
+diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
+index 95fdfac..32e7222 100644
 --- a/drivers/clk/mediatek/Makefile
 +++ b/drivers/clk/mediatek/Makefile
 @@ -1,4 +1,4 @@
@@ -59,3 +66,6 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 -obj-y += clk-mt8173.o
 +obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
 +obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0007-dt-bindings-ARM-Mediatek-Document-bindings-for-MT270.patch

@@ -1,7 +1,7 @@
-From d7e96f87f66c571e9f4171ecd89c656fbd2de89b Mon Sep 17 00:00:00 2001
+From 7c98b20fa68a2a64bca69822eb7be4fa9b668fab Mon Sep 17 00:00:00 2001
 From: James Liao <jamesjj.liao@mediatek.com>
 Date: Tue, 5 Jan 2016 14:30:18 +0800
-Subject: [PATCH 07/91] dt-bindings: ARM: Mediatek: Document bindings for
+Subject: [PATCH 007/102] dt-bindings: ARM: Mediatek: Document bindings for
  MT2701
 
 This patch adds the binding documentation for apmixedsys, bdpsys,
@@ -25,9 +25,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
 
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+index 936166f..a701e19 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
-@@ -6,6 +6,7 @@ The Mediatek apmixedsys controller provi
+@@ -6,6 +6,7 @@ The Mediatek apmixedsys controller provides the PLLs to the system.
  Required Properties:
  
  - compatible: Should be:
@@ -35,6 +37,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  	- "mediatek,mt8135-apmixedsys"
  	- "mediatek,mt8173-apmixedsys"
  - #clock-cells: Must be 1
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
+new file mode 100644
+index 0000000..4137196
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
 @@ -0,0 +1,22 @@
@@ -60,6 +65,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +	reg = <0 0x1c000000 0 0x1000>;
 +	#clock-cells = <1>;
 +};
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+new file mode 100644
+index 0000000..768f3a5
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
 @@ -0,0 +1,22 @@
@@ -85,6 +93,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +	reg = <0 0x1b000000 0 0x1000>;
 +	#clock-cells = <1>;
 +};
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
+new file mode 100644
+index 0000000..b7a39b6
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
 @@ -0,0 +1,22 @@
@@ -110,9 +121,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +	reg = <0 0x1a000000 0 0x1000>;
 +	#clock-cells = <1>;
 +};
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
+index b1f2ce1..9bda7f7 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
-@@ -6,6 +6,7 @@ The Mediatek imgsys controller provides
+@@ -6,6 +6,7 @@ The Mediatek imgsys controller provides various clocks to the system.
  Required Properties:
  
  - compatible: Should be:
@@ -120,6 +133,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  	- "mediatek,mt8173-imgsys", "syscon"
  - #clock-cells: Must be 1
  
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+index f6cd3e4..2f11a69 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
 @@ -7,6 +7,7 @@ outputs to the system.
@@ -130,9 +145,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  	- "mediatek,mt8135-infracfg", "syscon"
  	- "mediatek,mt8173-infracfg", "syscon"
  - #clock-cells: Must be 1
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+index 4385946..c9d9d43 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
-@@ -6,6 +6,7 @@ The Mediatek mmsys controller provides v
+@@ -6,6 +6,7 @@ The Mediatek mmsys controller provides various clocks to the system.
  Required Properties:
  
  - compatible: Should be:
@@ -140,6 +157,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  	- "mediatek,mt8173-mmsys", "syscon"
  - #clock-cells: Must be 1
  
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
+index f25b854..d3454cd 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
 @@ -7,6 +7,7 @@ outputs to the system.
@@ -150,9 +169,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  	- "mediatek,mt8135-pericfg", "syscon"
  	- "mediatek,mt8173-pericfg", "syscon"
  - #clock-cells: Must be 1
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+index f9e9179..602e5bc 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
-@@ -6,6 +6,7 @@ The Mediatek topckgen controller provide
+@@ -6,6 +6,7 @@ The Mediatek topckgen controller provides various clocks to the system.
  Required Properties:
  
  - compatible: Should be:
@@ -160,9 +181,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  	- "mediatek,mt8135-topckgen"
  	- "mediatek,mt8173-topckgen"
  - #clock-cells: Must be 1
+diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
+index 1faacf1..f5b1e7d 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
-@@ -6,6 +6,7 @@ The Mediatek vdecsys controller provides
+@@ -6,6 +6,7 @@ The Mediatek vdecsys controller provides various clocks to the system.
  Required Properties:
  
  - compatible: Should be:
@@ -170,3 +193,6 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  	- "mediatek,mt8173-vdecsys", "syscon"
  - #clock-cells: Must be 1
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0008-clk-mediatek-Add-dt-bindings-for-MT2701-clocks.patch

@@ -1,7 +1,7 @@
-From 2fcbc15da2f13164e0851b9c7fae290249f0b44d Mon Sep 17 00:00:00 2001
+From 190696e3995be38fa01490e4ab88ea2c859829c9 Mon Sep 17 00:00:00 2001
 From: Shunli Wang <shunli.wang@mediatek.com>
 Date: Tue, 5 Jan 2016 14:30:19 +0800
-Subject: [PATCH 08/91] clk: mediatek: Add dt-bindings for MT2701 clocks
+Subject: [PATCH 008/102] clk: mediatek: Add dt-bindings for MT2701 clocks
 
 Add MT2701 clock dt-bindings, include topckgen, apmixedsys,
 infracfg, pericfg and subsystem clocks.
@@ -13,6 +13,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  1 file changed, 481 insertions(+)
  create mode 100644 include/dt-bindings/clock/mt2701-clk.h
 
+diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
+new file mode 100644
+index 0000000..50972d1
 --- /dev/null
 +++ b/include/dt-bindings/clock/mt2701-clk.h
 @@ -0,0 +1,481 @@
@@ -497,3 +500,6 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +#define CLK_BDP_NR				50
 +
 +#endif /* _DT_BINDINGS_CLK_MT2701_H */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0009-clk-mediatek-Add-MT2701-clock-support.patch

@@ -1,7 +1,7 @@
-From f2c07eaa2df52f9acac9ffc3457d3d81079dd723 Mon Sep 17 00:00:00 2001
+From a4c507d052390b42d7e8c59241e3c336796f730f Mon Sep 17 00:00:00 2001
 From: Shunli Wang <shunli.wang@mediatek.com>
 Date: Tue, 5 Jan 2016 14:30:20 +0800
-Subject: [PATCH 09/91] clk: mediatek: Add MT2701 clock support
+Subject: [PATCH 009/102] clk: mediatek: Add MT2701 clock support
 
 Add MT2701 clock support, include topckgen, apmixedsys,
 infracfg, pericfg and subsystem clocks.
@@ -19,6 +19,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  7 files changed, 1334 insertions(+), 3 deletions(-)
  create mode 100644 drivers/clk/mediatek/clk-mt2701.c
 
+diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
+index dc224e6..6c7cdc0 100644
 --- a/drivers/clk/mediatek/Kconfig
 +++ b/drivers/clk/mediatek/Kconfig
 @@ -6,6 +6,14 @@ config COMMON_CLK_MEDIATEK
@@ -36,6 +38,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  config COMMON_CLK_MT8135
  	bool "Clock driver for Mediatek MT8135"
  	depends on COMMON_CLK
+diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
+index 32e7222..5b2b91b 100644
 --- a/drivers/clk/mediatek/Makefile
 +++ b/drivers/clk/mediatek/Makefile
 @@ -1,4 +1,5 @@
@@ -44,9 +48,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
  obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
  obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
+diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
+index 576bdb7..38badb4 100644
 --- a/drivers/clk/mediatek/clk-gate.c
 +++ b/drivers/clk/mediatek/clk-gate.c
-@@ -61,6 +61,26 @@ static void mtk_cg_clr_bit(struct clk_hw
+@@ -61,6 +61,26 @@ static void mtk_cg_clr_bit(struct clk_hw *hw)
  	regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
  }
  
@@ -73,7 +79,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  static int mtk_cg_enable(struct clk_hw *hw)
  {
  	mtk_cg_clr_bit(hw);
-@@ -85,6 +105,30 @@ static void mtk_cg_disable_inv(struct cl
+@@ -85,6 +105,30 @@ static void mtk_cg_disable_inv(struct clk_hw *hw)
  	mtk_cg_clr_bit(hw);
  }
  
@@ -104,7 +110,7 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  const struct clk_ops mtk_clk_gate_ops_setclr = {
  	.is_enabled	= mtk_cg_bit_is_cleared,
  	.enable		= mtk_cg_enable,
-@@ -97,6 +141,18 @@ const struct clk_ops mtk_clk_gate_ops_se
+@@ -97,6 +141,18 @@ const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
  	.disable	= mtk_cg_disable_inv,
  };
  
@@ -123,9 +129,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  struct clk * __init mtk_clk_register_gate(
  		const char *name,
  		const char *parent_name,
+diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
+index 11e25c9..7f7ef34 100644
 --- a/drivers/clk/mediatek/clk-gate.h
 +++ b/drivers/clk/mediatek/clk-gate.h
-@@ -36,6 +36,8 @@ static inline struct mtk_clk_gate *to_cl
+@@ -36,6 +36,8 @@ static inline struct mtk_clk_gate *to_clk_gate(struct clk_hw *hw)
  
  extern const struct clk_ops mtk_clk_gate_ops_setclr;
  extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
@@ -134,6 +142,9 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  
  struct clk *mtk_clk_register_gate(
  		const char *name,
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+new file mode 100644
+index 0000000..2f521f4
 --- /dev/null
 +++ b/drivers/clk/mediatek/clk-mt2701.c
 @@ -0,0 +1,1210 @@
@@ -1347,9 +1358,11 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +}
 +CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt2701-apmixedsys",
 +							mtk_apmixedsys_init);
+diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
+index cf08db6..be19a41 100644
 --- a/drivers/clk/mediatek/clk-mtk.c
 +++ b/drivers/clk/mediatek/clk-mtk.c
-@@ -242,3 +242,28 @@ void __init mtk_clk_register_composites(
+@@ -242,3 +242,28 @@ void __init mtk_clk_register_composites(const struct mtk_composite *mcs,
  			clk_data->clks[mc->id] = clk;
  	}
  }
@@ -1378,6 +1391,8 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
 +			clk_data->clks[mcd->id] = clk;
 +	}
 +}
+diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
+index 32d2e45..60701e8 100644
 --- a/drivers/clk/mediatek/clk-mtk.h
 +++ b/drivers/clk/mediatek/clk-mtk.h
 @@ -110,7 +110,8 @@ struct mtk_composite {
@@ -1429,3 +1444,6 @@ Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  
  struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0010-reset-mediatek-mt2701-reset-controller-dt-binding-fi.patch

@@ -1,7 +1,7 @@
-From 8d134cbe750b59d15c591622d81e2e9daa09f0c4 Mon Sep 17 00:00:00 2001
+From 8bf0f2a1e8ff082de3f650211abd985ef68abe1b Mon Sep 17 00:00:00 2001
 From: Shunli Wang <shunli.wang@mediatek.com>
 Date: Tue, 5 Jan 2016 14:30:21 +0800
-Subject: [PATCH 10/91] reset: mediatek: mt2701 reset controller dt-binding
+Subject: [PATCH 010/102] reset: mediatek: mt2701 reset controller dt-binding
  file
 
 Dt-binding file about reset controller is used to provide
@@ -14,6 +14,9 @@ Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
  1 file changed, 74 insertions(+)
  create mode 100644 include/dt-bindings/reset-controller/mt2701-resets.h
 
+diff --git a/include/dt-bindings/reset-controller/mt2701-resets.h b/include/dt-bindings/reset-controller/mt2701-resets.h
+new file mode 100644
+index 0000000..00efeb0
 --- /dev/null
 +++ b/include/dt-bindings/reset-controller/mt2701-resets.h
 @@ -0,0 +1,74 @@
@@ -91,3 +94,6 @@ Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
 +#define MT2701_TOPRGU_BDP_DISP_RST		13
 +
 +#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0011-reset-mediatek-mt2701-reset-driver.patch

@@ -1,7 +1,7 @@
-From b86d3303db25a8296e4c3de46ee1470f60f71b0c Mon Sep 17 00:00:00 2001
+From 3ba0020ea70ffb5503eff1823be7fa5ceda38286 Mon Sep 17 00:00:00 2001
 From: Shunli Wang <shunli.wang@mediatek.com>
 Date: Tue, 5 Jan 2016 14:30:22 +0800
-Subject: [PATCH 11/91] reset: mediatek: mt2701 reset driver
+Subject: [PATCH 011/102] reset: mediatek: mt2701 reset driver
 
 In infrasys and perifsys, there are many reset
 control bits for kinds of modules. These bits are
@@ -14,9 +14,11 @@ Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
  drivers/clk/mediatek/clk-mt2701.c |    4 ++++
  1 file changed, 4 insertions(+)
 
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+index 2f521f4..39472e4 100644
 --- a/drivers/clk/mediatek/clk-mt2701.c
 +++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -665,6 +665,8 @@ static void __init mtk_infrasys_init(str
+@@ -665,6 +665,8 @@ static void __init mtk_infrasys_init(struct device_node *node)
  	if (r)
  		pr_err("%s(): could not register clock provider: %d\n",
  			__func__, r);
@@ -25,7 +27,7 @@ Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
  }
  CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt2701-infracfg", mtk_infrasys_init);
  
-@@ -782,6 +784,8 @@ static void __init mtk_pericfg_init(stru
+@@ -782,6 +784,8 @@ static void __init mtk_pericfg_init(struct device_node *node)
  	if (r)
  		pr_err("%s(): could not register clock provider: %d\n",
  			__func__, r);
@@ -34,3 +36,6 @@ Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
  }
  CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt2701-pericfg", mtk_pericfg_init);
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0012-ARM-mediatek-Add-MT2701-config-options-for-mediatek-.patch

@@ -1,8 +1,8 @@
-From 3b5df542d52b13a1b20d25311fa4c4029a3b83af Mon Sep 17 00:00:00 2001
+From 32fa899c6ab79953e4f470fb23c38bcc40edc5c8 Mon Sep 17 00:00:00 2001
 From: Erin Lo <erin.lo@mediatek.com>
 Date: Mon, 28 Dec 2015 15:09:02 +0800
-Subject: [PATCH 12/91] ARM: mediatek: Add MT2701 config options for mediatek
+Subject: [PATCH 012/102] ARM: mediatek: Add MT2701 config options for
- SoCs.
+ mediatek SoCs.
 
 The upcoming MTK pinctrl driver have a big pin table for each SoC
 and we don't want to bloat the kernel binary if we don't need it.
@@ -14,6 +14,8 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  arch/arm/mach-mediatek/Kconfig |    4 ++++
  1 file changed, 4 insertions(+)
 
+diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
+index aeece17..37dd438 100644
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
 @@ -9,6 +9,10 @@ menuconfig ARCH_MEDIATEK
@@ -27,3 +29,6 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  config MACH_MT6589
  	bool "MediaTek MT6589 SoCs support"
  	default ARCH_MEDIATEK
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0013-dt-bindings-mediatek-Modify-pinctrl-bindings-for-mt2.patch

@@ -1,7 +1,7 @@
-From 1a254735cad9db5c8605c972b0f16b3929dc0d6e Mon Sep 17 00:00:00 2001
+From afcbed6f51e8c3a9195952b27c8aad047c314ed0 Mon Sep 17 00:00:00 2001
 From: Biao Huang <biao.huang@mediatek.com>
 Date: Mon, 28 Dec 2015 15:09:03 +0800
-Subject: [PATCH 13/91] dt-bindings: mediatek: Modify pinctrl bindings for
+Subject: [PATCH 013/102] dt-bindings: mediatek: Modify pinctrl bindings for
  mt2701
 
 Signed-off-by: Biao Huang <biao.huang@mediatek.com>
@@ -11,9 +11,11 @@ Reviewed-by: Mathias Brugger <matthias.bgg@gmail.com>
  Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt |    9 +++++----
  1 file changed, 5 insertions(+), 4 deletions(-)
 
+diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
+index 0480bc3..9ffb0b2 100644
 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
 +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
-@@ -4,10 +4,11 @@ The Mediatek's Pin controller is used to
+@@ -4,10 +4,11 @@ The Mediatek's Pin controller is used to control SoC pins.
  
  Required properties:
  - compatible: value should be one of the following.
@@ -29,3 +31,6 @@ Reviewed-by: Mathias Brugger <matthias.bgg@gmail.com>
  - pins-are-numbered: Specify the subnodes are using numbered pinmux to
    specify pins.
  - gpio-controller : Marks the device node as a gpio controller.
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0014-pinctrl-dt-bindings-Add-pinfunc-header-file-for-mt27.patch

@@ -1,7 +1,7 @@
-From 416720ba33d4fd7d3166c17be7c13651cc08d408 Mon Sep 17 00:00:00 2001
+From 124894a4d1635915ff95c447767677b60fd27e9c Mon Sep 17 00:00:00 2001
 From: Biao Huang <biao.huang@mediatek.com>
 Date: Mon, 28 Dec 2015 15:09:04 +0800
-Subject: [PATCH 14/91] pinctrl: dt bindings: Add pinfunc header file for
+Subject: [PATCH 014/102] pinctrl: dt bindings: Add pinfunc header file for
  mt2701
 
 Add pinfunc header file, mt2701 related dts will include it
@@ -21,6 +21,9 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2701.c
  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
 
+diff --git a/arch/arm/boot/dts/mt2701-pinfunc.h b/arch/arm/boot/dts/mt2701-pinfunc.h
+new file mode 100644
+index 0000000..e24ebc8
 --- /dev/null
 +++ b/arch/arm/boot/dts/mt2701-pinfunc.h
 @@ -0,0 +1,735 @@
@@ -759,6 +762,8 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
 +#define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)
 +
 +#endif /* __DTS_MT2701_PINFUNC_H */
+diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
+index 02f6f92..13e9939 100644
 --- a/drivers/pinctrl/mediatek/Kconfig
 +++ b/drivers/pinctrl/mediatek/Kconfig
 @@ -9,6 +9,12 @@ config PINCTRL_MTK_COMMON
@@ -774,6 +779,8 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  config PINCTRL_MT8135
  	bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135
  	depends on OF
+diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
+index eb923d6..da30314 100644
 --- a/drivers/pinctrl/mediatek/Makefile
 +++ b/drivers/pinctrl/mediatek/Makefile
 @@ -2,6 +2,7 @@
@@ -784,6 +791,9 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  obj-$(CONFIG_PINCTRL_MT8135)		+= pinctrl-mt8135.o
  obj-$(CONFIG_PINCTRL_MT8127)		+= pinctrl-mt8127.o
  obj-$(CONFIG_PINCTRL_MT8173)		+= pinctrl-mt8173.o
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
+new file mode 100644
+index 0000000..4861b5d
 --- /dev/null
 +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
 @@ -0,0 +1,586 @@
@@ -1373,6 +1383,8 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
 +}
 +
 +arch_initcall(mtk_pinctrl_init);
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+index 5c71727..05ba7a8 100644
 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
 @@ -47,6 +47,8 @@
@@ -1384,7 +1396,7 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  };
  
  /*
-@@ -81,6 +83,9 @@ static int mtk_pmx_gpio_set_direction(st
+@@ -81,6 +83,9 @@ static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
  	reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
  	bit = BIT(offset & 0xf);
  
@@ -1394,7 +1406,7 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  	if (input)
  		/* Different SoC has different alignment offset. */
  		reg_addr = CLR_ADDR(reg_addr, pctl);
-@@ -347,6 +352,7 @@ static int mtk_pconf_parse_conf(struct p
+@@ -347,6 +352,7 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
  		ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
  		break;
  	case PIN_CONFIG_INPUT_ENABLE:
@@ -1402,7 +1414,7 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  		ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
  		break;
  	case PIN_CONFIG_OUTPUT:
-@@ -354,6 +360,7 @@ static int mtk_pconf_parse_conf(struct p
+@@ -354,6 +360,7 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
  		ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
  		break;
  	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
@@ -1410,7 +1422,7 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  		ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
  		break;
  	case PIN_CONFIG_DRIVE_STRENGTH:
-@@ -667,9 +674,14 @@ static int mtk_pmx_set_mode(struct pinct
+@@ -667,9 +674,14 @@ static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
  	unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
  	struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  
@@ -1425,7 +1437,7 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  	bit = pin % MAX_GPIO_MODE_PER_REG;
  	mask <<= (GPIO_MODE_BITS * bit);
  	val = (mode << (GPIO_MODE_BITS * bit));
-@@ -746,6 +758,10 @@ static int mtk_gpio_get_direction(struct
+@@ -746,6 +758,10 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  
  	reg_addr =  mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
  	bit = BIT(offset & 0xf);
@@ -1436,6 +1448,8 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  	regmap_read(pctl->regmap1, reg_addr, &read_val);
  	return !(read_val & bit);
  }
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+index 55a5343..8543bc4 100644
 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
 @@ -209,7 +209,14 @@ struct mtk_eint_offsets {
@@ -1464,6 +1478,9 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
  	unsigned int dir_offset;
  	unsigned int ies_offset;
  	unsigned int smt_offset;
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
+new file mode 100644
+index 0000000..f906420
 --- /dev/null
 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
 @@ -0,0 +1,2323 @@
@@ -3790,3 +3807,6 @@ Acked-by: Linus Walleij <linus.walleij@linaro.org>
 +};
 +
 +#endif /* __PINCTRL_MTK_MT2701_H */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0015-dt-bindings-mediatek-Modify-pinctrl-bindings-for-mt7.patch

@@ -1,7 +1,7 @@
-From ddc72b659b3642d0496dee4e1ee39416ca008053 Mon Sep 17 00:00:00 2001
+From 3800e5c33e5becbb56c6694008d1f3435fd78707 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Thu, 7 Jan 2016 23:42:06 +0100
-Subject: [PATCH 15/91] dt-bindings: mediatek: Modify pinctrl bindings for
+Subject: [PATCH 015/102] dt-bindings: mediatek: Modify pinctrl bindings for
  mt7623
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
@@ -11,6 +11,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  2 files changed, 522 insertions(+)
  create mode 100644 include/dt-bindings/pinctrl/mt7623-pinfunc.h
 
+diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
+index 9ffb0b2..17631d0 100644
 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
 +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
 @@ -6,6 +6,7 @@ Required properties:
@@ -21,6 +23,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
  	"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
  	"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
+diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
+new file mode 100644
+index 0000000..891b173
 --- /dev/null
 +++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
 @@ -0,0 +1,521 @@
@@ -545,3 +550,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +
 +#endif /* __DTS_MT7623_PINFUNC_H */
 +
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0016-pinctrl-dt-bindings-Add-pinctrl-file-for-mt7623.patch

@@ -1,7 +1,7 @@
-From 1255eaacd6cc9d1fa6bb33185380efed22008baf Mon Sep 17 00:00:00 2001
+From 641ccb565a934ffaa30b828f2361e6f57325c70a Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sat, 27 Jun 2015 13:13:05 +0200
-Subject: [PATCH 16/91] pinctrl: dt bindings: Add pinctrl file for mt7623
+Subject: [PATCH 016/102] pinctrl: dt bindings: Add pinctrl file for mt7623
 
 Add the driver and header files required to make pinctrl work on MediaTek
 MT7623.
@@ -17,6 +17,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7623.c
  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
 
+diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
+index 13e9939..78654a8 100644
 --- a/drivers/pinctrl/mediatek/Kconfig
 +++ b/drivers/pinctrl/mediatek/Kconfig
 @@ -15,6 +15,12 @@ config PINCTRL_MT2701
@@ -32,9 +34,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  config PINCTRL_MT8135
  	bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135
  	depends on OF
+diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
+index da30314..1be2f3f 100644
 --- a/drivers/pinctrl/mediatek/Makefile
 +++ b/drivers/pinctrl/mediatek/Makefile
-@@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_MTK_COMMON)	+= pinc
+@@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_MTK_COMMON)	+= pinctrl-mtk-common.o
  
  # SoC Drivers
  obj-$(CONFIG_PINCTRL_MT2701)		+= pinctrl-mt2701.o
@@ -42,6 +46,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  obj-$(CONFIG_PINCTRL_MT8135)		+= pinctrl-mt8135.o
  obj-$(CONFIG_PINCTRL_MT8127)		+= pinctrl-mt8127.o
  obj-$(CONFIG_PINCTRL_MT8173)		+= pinctrl-mt8173.o
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
+new file mode 100644
+index 0000000..bf0d05b
 --- /dev/null
 +++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
 @@ -0,0 +1,380 @@
@@ -425,6 +432,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +}
 +
 +arch_initcall(mtk_pinctrl_init);
+diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
+new file mode 100644
+index 0000000..fb63c01
 --- /dev/null
 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
 @@ -0,0 +1,1937 @@
@@ -2365,6 +2375,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +};
 +
 +#endif /* __PINCTRL_MTK_MT7623_H */
+diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
+index 891b173..eeb2380 100644
 --- a/include/dt-bindings/pinctrl/mt7623-pinfunc.h
 +++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
 @@ -505,6 +505,9 @@
@@ -2377,3 +2389,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  #define MT7623_PIN_274_G2_RXDV_FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
  #define MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0017-clk-add-hifsys-reset.patch

@@ -1,7 +1,7 @@
-From 294cf90337d70ad74edf147180bbeef837298bd0 Mon Sep 17 00:00:00 2001
+From f7121d2b19ddad33a09408a2c5923bfd95da8533 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 6 Jan 2016 20:06:49 +0100
-Subject: [PATCH 17/91] clk: add hifsys reset
+Subject: [PATCH 017/102] clk: add hifsys reset
 
 Hi,
 
@@ -18,9 +18,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  include/dt-bindings/reset-controller/mt2701-resets.h |    9 +++++++++
  2 files changed, 11 insertions(+)
 
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+index 39472e4..0e40bb8 100644
 --- a/drivers/clk/mediatek/clk-mt2701.c
 +++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -1000,6 +1000,8 @@ static void __init mtk_hifsys_init(struc
+@@ -1000,6 +1000,8 @@ static void __init mtk_hifsys_init(struct device_node *node)
  	if (r)
  		pr_err("%s(): could not register clock provider: %d\n",
  			__func__, r);
@@ -29,6 +31,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  }
  CLK_OF_DECLARE(mtk_hifsys, "mediatek,mt2701-hifsys", mtk_hifsys_init);
  
+diff --git a/include/dt-bindings/reset-controller/mt2701-resets.h b/include/dt-bindings/reset-controller/mt2701-resets.h
+index 00efeb0..aaf0305 100644
 --- a/include/dt-bindings/reset-controller/mt2701-resets.h
 +++ b/include/dt-bindings/reset-controller/mt2701-resets.h
 @@ -71,4 +71,13 @@
@@ -45,3 +49,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#define MT2701_HIFSYS_PCIE2_RST			26
 +
  #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0018-dt-bindings-Add-a-binding-for-Mediatek-xHCI-host-con.patch

@@ -1,7 +1,7 @@
-From 84d37aeef94deae3ce87e677f6016a5d980429e8 Mon Sep 17 00:00:00 2001
+From ba126a519da8a036dae0032e9d5a89e47570e5fb Mon Sep 17 00:00:00 2001
 From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
 Date: Tue, 17 Nov 2015 17:18:39 +0800
-Subject: [PATCH 18/91] dt-bindings: Add a binding for Mediatek xHCI host
+Subject: [PATCH 018/102] dt-bindings: Add a binding for Mediatek xHCI host
  controller
 
 add a DT binding documentation of xHCI host controller for the
@@ -13,6 +13,9 @@ Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
  1 file changed, 51 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/usb/mt8173-xhci.txt
 
+diff --git a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
+new file mode 100644
+index 0000000..a78f20b
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt
 @@ -0,0 +1,51 @@
@@ -67,3 +70,6 @@ Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
 +	mediatek,syscon-wakeup = <&pericfg>;
 +	mediatek,wakeup-src = <1>;
 +};
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0019-xhci-mediatek-support-MTK-xHCI-host-controller.patch

@@ -1,7 +1,7 @@
-From 651d8fff94718c7e48b8a40d7774878eb8ed62ee Mon Sep 17 00:00:00 2001
+From 8b8185586a13ebbd760e80bbe5f22f9417b50fd2 Mon Sep 17 00:00:00 2001
 From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
 Date: Tue, 17 Nov 2015 17:18:40 +0800
-Subject: [PATCH 19/91] xhci: mediatek: support MTK xHCI host controller
+Subject: [PATCH 019/102] xhci: mediatek: support MTK xHCI host controller
 
 There some vendor quirks for MTK xhci host controller:
 1. It defines some extra SW scheduling parameters for HW
@@ -31,6 +31,8 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  create mode 100644 drivers/usb/host/xhci-mtk.c
  create mode 100644 drivers/usb/host/xhci-mtk.h
 
+diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
+index 3bb0887..daa563f 100644
 --- a/drivers/usb/host/Kconfig
 +++ b/drivers/usb/host/Kconfig
 @@ -41,6 +41,15 @@ config USB_XHCI_PLATFORM
@@ -49,6 +51,8 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  config USB_XHCI_MVEBU
  	tristate "xHCI support for Marvell Armada 375/38x"
  	select USB_XHCI_PLATFORM
+diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
+index e7558ab..65a06b4 100644
 --- a/drivers/usb/host/Makefile
 +++ b/drivers/usb/host/Makefile
 @@ -13,6 +13,9 @@ fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
@@ -69,6 +73,9 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  obj-$(CONFIG_USB_SL811_HCD)	+= sl811-hcd.o
  obj-$(CONFIG_USB_SL811_CS)	+= sl811_cs.o
  obj-$(CONFIG_USB_U132_HCD)	+= u132-hcd.o
+diff --git a/drivers/usb/host/xhci-mtk-sch.c b/drivers/usb/host/xhci-mtk-sch.c
+new file mode 100644
+index 0000000..c30de7c
 --- /dev/null
 +++ b/drivers/usb/host/xhci-mtk-sch.c
 @@ -0,0 +1,415 @@
@@ -487,6 +494,9 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
 +	}
 +}
 +EXPORT_SYMBOL_GPL(xhci_mtk_drop_ep_quirk);
+diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
+new file mode 100644
+index 0000000..c9ab6a4
 --- /dev/null
 +++ b/drivers/usb/host/xhci-mtk.c
 @@ -0,0 +1,763 @@
@@ -1253,6 +1263,9 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
 +MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
 +MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
 +MODULE_LICENSE("GPL v2");
+diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
+new file mode 100644
+index 0000000..7da677c
 --- /dev/null
 +++ b/drivers/usb/host/xhci-mtk.h
 @@ -0,0 +1,162 @@
@@ -1418,6 +1431,8 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
 +#endif
 +
 +#endif		/* _XHCI_MTK_H_ */
+diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
+index eeaa6c6..f1c21c4 100644
 --- a/drivers/usb/host/xhci-ring.c
 +++ b/drivers/usb/host/xhci-ring.c
 @@ -68,6 +68,7 @@
@@ -1428,7 +1443,7 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  
  /*
   * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
-@@ -3065,17 +3066,22 @@ static u32 xhci_td_remainder(struct xhci
+@@ -3075,17 +3076,22 @@ static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
  {
  	u32 maxp, total_packet_count;
  
@@ -1455,7 +1470,7 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  	/* Queueing functions don't count the current TRB into transferred */
  	return (total_packet_count - ((transferred + trb_buff_len) / maxp));
  }
-@@ -3463,7 +3469,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
+@@ -3473,7 +3479,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
  		field |= 0x1;
  
  	/* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
@@ -1464,6 +1479,8 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  		if (urb->transfer_buffer_length > 0) {
  			if (setup->bRequestType & USB_DIR_IN)
  				field |= TRB_TX_TYPE(TRB_DATA_IN);
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 3f91270..15fedb2 100644
 --- a/drivers/usb/host/xhci.c
 +++ b/drivers/usb/host/xhci.c
 @@ -31,6 +31,7 @@
@@ -1474,7 +1491,7 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  
  #define DRIVER_AUTHOR "Sarah Sharp"
  #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
-@@ -635,7 +636,11 @@ int xhci_run(struct usb_hcd *hcd)
+@@ -634,7 +635,11 @@ int xhci_run(struct usb_hcd *hcd)
  			"// Set the interrupt modulation register");
  	temp = readl(&xhci->ir_set->irq_control);
  	temp &= ~ER_IRQ_INTERVAL_MASK;
@@ -1487,7 +1504,7 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  	writel(temp, &xhci->ir_set->irq_control);
  
  	/* Set the HCD state before we enable the irqs */
-@@ -1701,6 +1706,9 @@ int xhci_drop_endpoint(struct usb_hcd *h
+@@ -1698,6 +1703,9 @@ int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
  
  	xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
  
@@ -1497,7 +1514,7 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  	xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
  			(unsigned int) ep->desc.bEndpointAddress,
  			udev->slot_id,
-@@ -1796,6 +1804,15 @@ int xhci_add_endpoint(struct usb_hcd *hc
+@@ -1793,6 +1801,15 @@ int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
  		return -ENOMEM;
  	}
  
@@ -1513,9 +1530,11 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  	ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
  	new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
  
+diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
+index 0b94512..40cf36e 100644
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
-@@ -1631,6 +1631,7 @@ struct xhci_hcd {
+@@ -1630,6 +1630,7 @@ struct xhci_hcd {
  /* For controllers with a broken beyond repair streams implementation */
  #define XHCI_BROKEN_STREAMS	(1 << 19)
  #define XHCI_PME_STUCK_QUIRK	(1 << 20)
@@ -1523,3 +1542,6 @@ Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  	unsigned int		num_active_eps;
  	unsigned int		limit_active_eps;
  	/* There are two roothubs to keep track of bus suspend info for */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0020-arm64-dts-mediatek-add-xHCI-usb-phy-for-mt8173.patch

@@ -1,7 +1,7 @@
-From 31a22fbd0d3b187be61c4c5d22b19c95abb327c3 Mon Sep 17 00:00:00 2001
+From 645465d4c6dd46c5e6c9ac25cd42608b4201fde0 Mon Sep 17 00:00:00 2001
 From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
 Date: Tue, 17 Nov 2015 17:18:41 +0800
-Subject: [PATCH 20/91] arm64: dts: mediatek: add xHCI & usb phy for mt8173
+Subject: [PATCH 020/102] arm64: dts: mediatek: add xHCI & usb phy for mt8173
 
 add xHCI and phy drivers for MT8173-EVB
 
@@ -11,6 +11,8 @@ Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
  arch/arm64/boot/dts/mediatek/mt8173.dtsi    |   42 +++++++++++++++++++++++++++
  2 files changed, 58 insertions(+)
 
+diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+index 811cb76..9b1482a 100644
 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
 +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
 @@ -13,6 +13,7 @@
@@ -47,6 +49,8 @@ Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
 +	vbus-supply = <&usb_p1_vbus>;
 +	mediatek,wakeup-src = <1>;
 +};
+diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+index 4dd5f93..c1fd275 100644
 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
 +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
 @@ -14,6 +14,7 @@
@@ -105,3 +109,6 @@ Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
  		mmsys: clock-controller@14000000 {
  			compatible = "mediatek,mt8173-mmsys", "syscon";
  			reg = <0 0x14000000 0 0x1000>;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0021-Document-DT-Add-bindings-for-mediatek-MT7623-SoC-Pla.patch

@@ -1,7 +1,7 @@
-From 162deec293400cb132161606629654acaec7cb4b Mon Sep 17 00:00:00 2001
+From e111a35542ac14712026fe1a55236f76c7fc9048 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 5 Jan 2016 12:13:54 +0100
-Subject: [PATCH 21/91] Document: DT: Add bindings for mediatek MT7623 SoC
+Subject: [PATCH 021/102] Document: DT: Add bindings for mediatek MT7623 SoC
  Platform
 
 This adds a DT binding documentation for the MT7623 SoC from Mediatek.
@@ -13,6 +13,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt |    1 +
  3 files changed, 6 insertions(+)
 
+diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
+index 618a9199..40e9d32 100644
 --- a/Documentation/devicetree/bindings/arm/mediatek.txt
 +++ b/Documentation/devicetree/bindings/arm/mediatek.txt
 @@ -10,6 +10,7 @@ compatible: Must contain one of
@@ -33,6 +35,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  - MTK mt8127 tablet moose EVB:
      Required root node properties:
        - compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
+diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
+index 2d47add..474f0cf 100644
 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
 +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
 @@ -2,6 +2,7 @@
@@ -43,6 +47,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
    * "mediatek,mt8135-uart" for MT8135 compatible UARTS
    * "mediatek,mt8127-uart" for MT8127 compatible UARTS
    * "mediatek,mt8173-uart" for MT8173 compatible UARTS
+diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+index 64083bc..6bacda1b3 100644
 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
 +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
 @@ -5,6 +5,7 @@ Required properties:
@@ -53,3 +59,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	* "mediatek,mt8127-timer" for MT8127 compatible timers
  	* "mediatek,mt8135-timer" for MT8135 compatible timers
  	* "mediatek,mt8173-timer" for MT8173 compatible timers
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0022-soc-mediatek-add-compat-string-for-mt7623-to-scpsys.patch

@@ -1,16 +1,19 @@
-From fa5d94d6b4b314f751b1c32bb5a87a80b866d05e Mon Sep 17 00:00:00 2001
+From f232c3b36355974bf3442de3a4726d2e499ed3fe Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 5 Jan 2016 16:52:31 +0100
-Subject: [PATCH 22/91] soc: mediatek: add compat string for mt7623 to scpsys
+Subject: [PATCH 022/102] soc: mediatek: add compat string for mt7623 to
+ scpsys
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
  drivers/soc/mediatek/mtk-scpsys-mt2701.c |    2 ++
  1 file changed, 2 insertions(+)
 
+diff --git a/drivers/soc/mediatek/mtk-scpsys-mt2701.c b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
+index 339d5b8..3a31946 100644
 --- a/drivers/soc/mediatek/mtk-scpsys-mt2701.c
 +++ b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
-@@ -136,6 +136,8 @@ static const struct of_device_id of_scps
+@@ -136,6 +136,8 @@ static const struct of_device_id of_scpsys_match_tbl[] = {
  	{
  		.compatible = "mediatek,mt2701-scpsys",
  	}, {
@@ -19,3 +22,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		/* sentinel */
  	}
  };
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0023-ARM-dts-mediatek-add-MT7623-basic-support.patch

@@ -1,21 +1,23 @@
-From 83ef9fb21a896ac03c3a78bc3ae0b21f3b0a43a3 Mon Sep 17 00:00:00 2001
+From 51d5ca9e151eb323bd965e72ad1e1dc93fcf7b13 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 5 Jan 2016 12:16:17 +0100
-Subject: [PATCH 23/91] ARM: dts: mediatek: add MT7623 basic support
+Subject: [PATCH 023/102] ARM: dts: mediatek: add MT7623 basic support
 
 This adds basic chip support for Mediatek MT7623.
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
  arch/arm/boot/dts/Makefile        |    1 +
- arch/arm/boot/dts/mt7623-evb.dts  |  474 +++++++++++++++++++++++++++++
+ arch/arm/boot/dts/mt7623-evb.dts  |  421 ++++++++++++++++++++++++++
- arch/arm/boot/dts/mt7623.dtsi     |  593 +++++++++++++++++++++++++++++++++++++
+ arch/arm/boot/dts/mt7623.dtsi     |  601 +++++++++++++++++++++++++++++++++++++
  arch/arm/mach-mediatek/Kconfig    |    4 +
  arch/arm/mach-mediatek/mediatek.c |    1 +
- 5 files changed, 1073 insertions(+)
+ 5 files changed, 1028 insertions(+)
  create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
  create mode 100644 arch/arm/boot/dts/mt7623.dtsi
 
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 30bbc37..2bce370 100644
 --- a/arch/arm/boot/dts/Makefile
 +++ b/arch/arm/boot/dts/Makefile
 @@ -774,6 +774,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
@@ -26,9 +28,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	mt8127-moose.dtb \
  	mt8135-evbp1.dtb
  dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
+diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
+new file mode 100644
+index 0000000..5ad1448
 --- /dev/null
 +++ b/arch/arm/boot/dts/mt7623-evb.dts
-@@ -0,0 +1,474 @@
+@@ -0,0 +1,421 @@
 +/*
 + * Copyright (c) 2016 MediaTek Inc.
 + * Author: John Crispin <blogic@openwrt.org>
@@ -318,127 +323,32 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	status = "okay";
 +};
 +
-+&mmc0 {
-+	status = "okay";
-+	pinctrl-names = "default", "state_uhs";
-+	pinctrl-0 = <&mmc0_pins_default>;
-+	pinctrl-1 = <&mmc0_pins_uhs>;
-+	bus-width = <8>;
-+	max-frequency = <50000000>;
-+	cap-mmc-highspeed;
-+	vmmc-supply = <&mt6323_vemc3v3_reg>;
-+	vqmmc-supply = <&mt6323_vio18_reg>;
-+	non-removable;
-+};
-+
-+&mmc1 {
-+	status = "okay";
-+	pinctrl-names = "default", "state_uhs";
-+	pinctrl-0 = <&mmc1_pins_default>;
-+	pinctrl-1 = <&mmc1_pins_uhs>;
-+	bus-width = <4>;
-+	max-frequency = <50000000>;
-+	cap-sd-highspeed;
-+	sd-uhs-sdr25;
-+//	cd-gpios = <&pio 132 0>;
-+	vmmc-supply = <&mt6323_vmch_reg>;
-+	vqmmc-supply = <&mt6323_vmc_reg>;
-+};
-+
 +&pio {
-+	mmc0_pins_default: mmc0default {
++	nand_pins_default: nanddefault {
-+		pins_cmd_dat {
++		pins_dat {
-+			pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
++			pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
-+				 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
++				 <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
-+				 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
++				 <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
-+				 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
++				 <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
-+				 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
++				 <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
-+				 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
++				 <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
-+				 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
++				 <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
-+				 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
++				 <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
-+				 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
++				 <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
-+			input-enable;
++				input-enable;
-+			bias-pull-up;
++				drive-strength = <MTK_DRIVE_8mA>;
++				bias-pull-up;
 +		};
 +
-+		pins_clk {
++		pins_we {
-+			pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
++			pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
-+			bias-pull-down;
++			drive-strength = <MTK_DRIVE_8mA>;
-+		};
-+
-+		pins_rst {
-+			pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
-+			bias-pull-up;
-+		};
-+	};
-+
-+	mmc0_pins_uhs: mmc0 {
-+		pins_cmd_dat {
-+			pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
-+				 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
-+				 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
-+				 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
-+				 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
-+				 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
-+				 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
-+				 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
-+				 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
-+			input-enable;
-+			drive-strength = <MTK_DRIVE_2mA>;
-+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
-+		};
-+
-+		pins_clk {
-+			pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
-+			drive-strength = <MTK_DRIVE_2mA>;
-+			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
-+		};
-+
-+		pins_rst {
-+			pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
-+			bias-pull-up;
-+		};
-+	};
-+
-+	mmc1_pins_default: mmc1default {
-+		pins_cmd_dat {
-+			pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
-+				 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
-+				 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
-+				 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
-+				 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
-+			input-enable;
-+			drive-strength = <MTK_DRIVE_4mA>;
 +			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
 +		};
 +
-+		pins_clk {
++		pins_ale {
-+			pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
++			pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
-+			bias-pull-down;
++			drive-strength = <MTK_DRIVE_8mA>;
-+			drive-strength = <MTK_DRIVE_4mA>;
-+		};
-+
-+//		pins_insert {
-+//			pinmux = <MT8173_PIN_132_I2S0_DATA1_FUNC_GPIO132>;
-+//			bias-pull-up;
-+//		};
-+	};
-+
-+	mmc1_pins_uhs: mmc1 {
-+		pins_cmd_dat {
-+			pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
-+				 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
-+				 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
-+				 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
-+				 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
-+			input-enable;
-+			drive-strength = <MTK_DRIVE_4mA>;
-+			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
-+		};
-+
-+		pins_clk {
-+			pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
-+			drive-strength = <MTK_DRIVE_4mA>;
 +			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 +		};
 +	};
@@ -469,6 +379,48 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	};
 +};
 +
++&nandc {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&nand_pins_default>;
++	nand@0 {
++		reg = <0>;
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			partition@C0000 {
++				label = "uboot-env";
++				reg = <0xC0000 0x40000>;
++			};
++
++			partition@100000 {
++				label = "factory";
++				reg = <0x100000 0x40000>;
++			};
++
++			partition@140000 {
++				label = "kernel";
++				reg = <0x140000 0x2000000>;
++			};
++
++			partition@2140000 {
++				label = "recovery";
++				reg = <0x2140000 0x2000000>;
++			};
++
++			partition@4140000 {
++				label = "rootfs";
++				reg = <0x4140000 0x1000000>;
++			};
++		};
++	};
++};
++&bch {
++	status = "okay";
++};
++
 +&usb1 {
 +	vusb33-supply = <&mt6323_vusb_reg>;
 +	vbus-supply = <&usb_p1_vbus>;
@@ -503,9 +455,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	mediatek,reset-pin = <&pio 15 0>;
 +	status = "okay";
 +};
+diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
+new file mode 100644
+index 0000000..cbbdf16
 --- /dev/null
 +++ b/arch/arm/boot/dts/mt7623.dtsi
-@@ -0,0 +1,593 @@
+@@ -0,0 +1,601 @@
 +/*
 + * Copyright (c) 2016 MediaTek Inc.
 + * Author: John Crispin <blogic@openwrt.org>
@@ -846,6 +801,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +		compatible = "mediatek,mt2701-nfc";
 +		reg = <0 0x1100d000 0 0x1000>;
 +		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
++		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 +		clocks = <&pericfg CLK_PERI_NFI>,
 +			 <&pericfg CLK_PERI_NFI_PAD>;
 +		clock-names = "nfi_clk", "pad_clk";
@@ -1065,8 +1021,15 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +			compatible = "mediatek,eth-mac";
 +			reg = <1>;
 +
-+			phy-handle = <&phy5>;
 +			status = "disabled";
++			
++			phy-mode = "rgmii";
++			
++			fixed-link {
++				speed = <1000>;
++				full-duplex;
++				pause;
++			};
 +		};
 +	
 +		mdio-bus {
@@ -1099,6 +1062,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +		status = "disabled";
 +	};
 +};
+diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
+index 37dd438..7fb605e 100644
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
 @@ -21,6 +21,10 @@ config MACH_MT6592
@@ -1112,9 +1077,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  config MACH_MT8127
  	bool "MediaTek MT8127 SoCs support"
  	default ARCH_MEDIATEK
+diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
+index d019a08..bcfca37 100644
 --- a/arch/arm/mach-mediatek/mediatek.c
 +++ b/arch/arm/mach-mediatek/mediatek.c
-@@ -46,6 +46,7 @@ static void __init mediatek_timer_init(v
+@@ -46,6 +46,7 @@ static void __init mediatek_timer_init(void)
  static const char * const mediatek_board_dt_compat[] = {
  	"mediatek,mt6589",
  	"mediatek,mt6592",
@@ -1122,3 +1089,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	"mediatek,mt8127",
  	"mediatek,mt8135",
  	NULL,
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0024-dt-bindings-add-MediaTek-PCIe-binding-documentation.patch

@@ -1,7 +1,7 @@
-From 427a938858630fe4cec1b3829624676a4106d236 Mon Sep 17 00:00:00 2001
+From 05be818061b9f2a0fa5ad0cde6881917ff14a2f2 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 6 Jan 2016 21:55:10 +0100
-Subject: [PATCH 24/91] dt-bindings: add MediaTek PCIe binding documentation
+Subject: [PATCH 024/102] dt-bindings: add MediaTek PCIe binding documentation
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
@@ -9,6 +9,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  1 file changed, 140 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt
 
+diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+new file mode 100644
+index 0000000..8fea3ed
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
 @@ -0,0 +1,140 @@
@@ -152,3 +155,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +			status = "okay";
 +		};
 +	};
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0025-PCI-mediatek-add-support-for-PCIe-found-on-MT7623-MT.patch

@@ -1,7 +1,7 @@
-From 5571cc63036daf0e0a05f07b0137fee86d58acb0 Mon Sep 17 00:00:00 2001
+From 8ab1d4e0a9a68e03f472dee1c036a01d0198c20c Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 5 Jan 2016 20:20:04 +0100
-Subject: [PATCH 25/91] PCI: mediatek: add support for PCIe found on
+Subject: [PATCH 025/102] PCI: mediatek: add support for PCIe found on
  MT7623/MT2701
 
 Add PCIe controller support on MediaTek MT2701/MT7623. The driver supports
@@ -17,6 +17,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  4 files changed, 654 insertions(+)
  create mode 100644 drivers/pci/host/pcie-mediatek.c
 
+diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
+index 7fb605e..a7fef77 100644
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
 @@ -24,6 +24,7 @@ config MACH_MT6592
@@ -27,9 +29,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  config MACH_MT8127
  	bool "MediaTek MT8127 SoCs support"
+diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
+index f131ba9..912f0e1 100644
 --- a/drivers/pci/host/Kconfig
 +++ b/drivers/pci/host/Kconfig
-@@ -173,4 +173,15 @@ config PCI_HISI
+@@ -172,4 +172,15 @@ config PCI_HISI
  	help
  	  Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC
  
@@ -45,13 +49,18 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	  PCIe include one Host/PCI bridge and 3 PCIe MAC.
 +
  endmenu
+diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
+index 9d4d3c6..3b53374 100644
 --- a/drivers/pci/host/Makefile
 +++ b/drivers/pci/host/Makefile
-@@ -20,3 +20,4 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-ip
+@@ -20,3 +20,4 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
  obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
  obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
  obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
 +obj-$(CONFIG_PCIE_MTK) += pcie-mediatek.o
+diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
+new file mode 100644
+index 0000000..ef03952
 --- /dev/null
 +++ b/drivers/pci/host/pcie-mediatek.c
 @@ -0,0 +1,641 @@
@@ -696,3 +705,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +}
 +
 +module_init(mtk_pcie_init);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0026-scpsys-various-fixes.patch

@@ -1,7 +1,7 @@
-From a366216a08408949eca2d7823273da6826d3c483 Mon Sep 17 00:00:00 2001
+From 59aafd667d2880c90776931b6102b8252214d93c Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 21 Feb 2016 13:52:12 +0100
-Subject: [PATCH 26/91] scpsys: various fixes
+Subject: [PATCH 026/102] scpsys: various fixes
 
 ---
  drivers/clk/mediatek/clk-mt2701.c        |    2 ++
@@ -9,9 +9,11 @@ Subject: [PATCH 26/91] scpsys: various fixes
  include/dt-bindings/power/mt2701-power.h |    4 ++--
  3 files changed, 4 insertions(+), 10 deletions(-)
 
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+index 0e40bb8..812b347 100644
 --- a/drivers/clk/mediatek/clk-mt2701.c
 +++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -1043,6 +1043,8 @@ static void __init mtk_ethsys_init(struc
+@@ -1043,6 +1043,8 @@ static void __init mtk_ethsys_init(struct device_node *node)
  	if (r)
  		pr_err("%s(): could not register clock provider: %d\n",
  			__func__, r);
@@ -20,9 +22,11 @@ Subject: [PATCH 26/91] scpsys: various fixes
  }
  CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt2701-ethsys", mtk_ethsys_init);
  
+diff --git a/drivers/soc/mediatek/mtk-scpsys-mt2701.c b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
+index 3a31946..19489bc 100644
 --- a/drivers/soc/mediatek/mtk-scpsys-mt2701.c
 +++ b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
-@@ -61,14 +61,6 @@ static const struct scp_domain_data scp_
+@@ -61,14 +61,6 @@ static const struct scp_domain_data scp_domain_data[] = {
  		.bus_prot_mask = MT2701_TOP_AXI_PROT_EN_DISP,
  		.active_wakeup = true,
  	},
@@ -37,6 +41,8 @@ Subject: [PATCH 26/91] scpsys: various fixes
  	[MT2701_POWER_DOMAIN_VDEC] = {
  		.name = "vdec",
  		.sta_mask = VDE_PWR_STA_MASK,
+diff --git a/include/dt-bindings/power/mt2701-power.h b/include/dt-bindings/power/mt2701-power.h
+index 64cc826..c168597 100644
 --- a/include/dt-bindings/power/mt2701-power.h
 +++ b/include/dt-bindings/power/mt2701-power.h
 @@ -16,12 +16,12 @@
@@ -54,3 +60,6 @@ Subject: [PATCH 26/91] scpsys: various fixes
 +#define MT2701_POWER_DOMAIN_IFR_MSC	2
  
  #endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0027-soc-mediatek-PMIC-wrap-Clear-the-vldclr-if-state-mac.patch

@@ -1,7 +1,7 @@
-From 4d02177361d13355d98a38830c69bb9add3c109c Mon Sep 17 00:00:00 2001
+From 55231d8299d3dccde8588ed2e86c2bc0ef2e12ce Mon Sep 17 00:00:00 2001
 From: Henry Chen <henryc.chen@mediatek.com>
 Date: Mon, 4 Jan 2016 20:02:52 +0800
-Subject: [PATCH 27/91] soc: mediatek: PMIC wrap: Clear the vldclr if state
+Subject: [PATCH 027/102] soc: mediatek: PMIC wrap: Clear the vldclr if state
  machine stay on FSM_VLDCLR state.
 
 Sometimes PMIC is too busy to send data in time to cause pmic wrap timeout,
@@ -20,9 +20,11 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   22 ++++++++++++++++++++--
  1 file changed, 20 insertions(+), 2 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 105597a..696071b 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
-@@ -412,6 +412,20 @@ static bool pwrap_is_fsm_vldclr(struct p
+@@ -412,6 +412,20 @@ static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
  	return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
  }
  
@@ -43,7 +45,7 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
  {
  	return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
-@@ -445,8 +459,10 @@ static int pwrap_write(struct pmic_wrapp
+@@ -445,8 +459,10 @@ static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
  	int ret;
  
  	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
@@ -55,7 +57,7 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  
  	pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
  			PWRAP_WACS2_CMD);
-@@ -459,8 +475,10 @@ static int pwrap_read(struct pmic_wrappe
+@@ -459,8 +475,10 @@ static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
  	int ret;
  
  	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
@@ -67,3 +69,6 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  
  	pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0028-ARM-mediatek-add-MT7623-smp-bringup-code.patch

@@ -1,7 +1,7 @@
-From e4a5c39f75a11ecb78d1243b19b929af54f888fa Mon Sep 17 00:00:00 2001
+From d088a94afc768683a881b627b6737442158e7db6 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 5 Jan 2016 17:24:28 +0100
-Subject: [PATCH 28/91] ARM: mediatek: add MT7623 smp bringup code
+Subject: [PATCH 028/102] ARM: mediatek: add MT7623 smp bringup code
 
 Add support for booting secondary CPUs on MT7623.
 
@@ -11,9 +11,11 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  arch/arm/mach-mediatek/platsmp.c |    7 +++++++
  1 file changed, 7 insertions(+)
 
+diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
+index 8141f3f..8151400 100644
 --- a/arch/arm/mach-mediatek/platsmp.c
 +++ b/arch/arm/mach-mediatek/platsmp.c
-@@ -44,6 +44,12 @@ static const struct mtk_smp_boot_info mt
+@@ -44,6 +44,12 @@ static const struct mtk_smp_boot_info mtk_mt6589_boot = {
  	{ 0x38, 0x3c, 0x40 },
  };
  
@@ -26,7 +28,7 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {
  	{ .compatible   = "mediatek,mt8135", .data = &mtk_mt8135_tz_boot },
  	{ .compatible   = "mediatek,mt8127", .data = &mtk_mt8135_tz_boot },
-@@ -51,6 +57,7 @@ static const struct of_device_id mtk_tz_
+@@ -51,6 +57,7 @@ static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {
  
  static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
  	{ .compatible   = "mediatek,mt6589", .data = &mtk_mt6589_boot },
@@ -34,3 +36,6 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  };
  
  static void __iomem *mtk_smp_base;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0029-soc-mediatek-PMIC-wrap-clear-the-STAUPD_TRIG-bit-of-.patch

@@ -1,8 +1,8 @@
-From b4a6293df00036129d26a7f06bfb220ba5a73c42 Mon Sep 17 00:00:00 2001
+From b92861fbc79b3a7a9bc1c51e2dbfa2c191cc27ea Mon Sep 17 00:00:00 2001
 From: Henry Chen <henryc.chen@mediatek.com>
 Date: Thu, 21 Jan 2016 19:04:00 +0800
-Subject: [PATCH 29/91] soc: mediatek: PMIC wrap: clear the STAUPD_TRIG bit of
+Subject: [PATCH 029/102] soc: mediatek: PMIC wrap: clear the STAUPD_TRIG bit
- WDT_SRC_EN
+ of WDT_SRC_EN
 
 Since STAUPD interrupts aren't handled on mt8173, disable watchdog timeout
 monitor of STAUPD to avoid WDT_INT triggered by STAUPD.
@@ -14,6 +14,8 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   19 +++++++++++++++++--
  1 file changed, 17 insertions(+), 2 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 696071b..0d9b19a 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -60,6 +60,15 @@
@@ -32,7 +34,7 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  /* macro for slave device wrapper registers */
  #define PWRAP_DEW_BASE			0xbc00
  #define PWRAP_DEW_EVENT_OUT_EN		(PWRAP_DEW_BASE + 0x0)
-@@ -822,7 +831,7 @@ MODULE_DEVICE_TABLE(of, of_pwrap_match_t
+@@ -822,7 +831,7 @@ MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
  
  static int pwrap_probe(struct platform_device *pdev)
  {
@@ -41,7 +43,7 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  	struct pmic_wrapper *wrp;
  	struct device_node *np = pdev->dev.of_node;
  	const struct of_device_id *of_id =
-@@ -912,7 +921,13 @@ static int pwrap_probe(struct platform_d
+@@ -912,7 +921,13 @@ static int pwrap_probe(struct platform_device *pdev)
  
  	/* Initialize watchdog, may not be done by the bootloader */
  	pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
@@ -56,3 +58,6 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  	pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
  	pwrap_writel(wrp, ~((1 << 31) | (1 << 1)), PWRAP_INT_EN);
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0030-ARM-mediatek-add-mt2701-smp-bringup-code.patch

@@ -1,7 +1,7 @@
-From 0befbd007b72ba2b14c65558d3bb72ea885496f6 Mon Sep 17 00:00:00 2001
+From f88ec31c6ba3a006d0be87ff1d99145f8cc85bee Mon Sep 17 00:00:00 2001
 From: Louis Yu <louis.yu@mediatek.com>
 Date: Thu, 7 Jan 2016 20:09:43 +0800
-Subject: [PATCH 30/91] ARM: mediatek: add mt2701 smp bringup code
+Subject: [PATCH 030/102] ARM: mediatek: add mt2701 smp bringup code
 
 Add support for booting secondary CPUs on mt2701.
 
@@ -11,9 +11,11 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  arch/arm/mach-mediatek/platsmp.c |    1 +
  1 file changed, 1 insertion(+)
 
+diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
+index 8151400..2078f92d5 100644
 --- a/arch/arm/mach-mediatek/platsmp.c
 +++ b/arch/arm/mach-mediatek/platsmp.c
-@@ -53,6 +53,7 @@ static const struct mtk_smp_boot_info mt
+@@ -53,6 +53,7 @@ static const struct mtk_smp_boot_info mtk_mt7623_boot = {
  static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {
  	{ .compatible   = "mediatek,mt8135", .data = &mtk_mt8135_tz_boot },
  	{ .compatible   = "mediatek,mt8127", .data = &mtk_mt8135_tz_boot },
@@ -21,3 +23,6 @@ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
  };
  
  static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0031-dt-bindings-ARM-Mediatek-add-MT2701-7623-string-to-t.patch

@@ -1,8 +1,8 @@
-From 9367fb14e1be8dd174f8d63ec83f7ee2d90ae733 Mon Sep 17 00:00:00 2001
+From 15f4d895578f02cbaed10b0f5f6853b873aba10b Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 13:12:19 +0100
-Subject: [PATCH 31/91] dt-bindings: ARM: Mediatek: add MT2701/7623 string to
+Subject: [PATCH 031/102] dt-bindings: ARM: Mediatek: add MT2701/7623 string
- the PMIC wrapper doc
+ to the PMIC wrapper doc
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 Acked-by: Rob Herring <robh@kernel.org>
@@ -11,6 +11,8 @@ Cc: devicetree@vger.kernel.org
  Documentation/devicetree/bindings/soc/mediatek/pwrap.txt |    1 +
  1 file changed, 1 insertion(+)
 
+diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
+index ddeb5b6..107700d 100644
 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
 +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
 @@ -18,6 +18,7 @@ IP Pairing
@@ -21,3 +23,6 @@ Cc: devicetree@vger.kernel.org
  	"mediatek,mt8135-pwrap" for MT8135 SoCs
  	"mediatek,mt8173-pwrap" for MT8173 SoCs
  - interrupts: IRQ for pwrap in SOC
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0032-soc-mediatek-PMIC-wrap-don-t-duplicate-the-wrapper-d.patch

@@ -1,8 +1,8 @@
-From 7b7d59b4219c30e1b9601300348f1431fdab7081 Mon Sep 17 00:00:00 2001
+From 64e8091be39c3f0a7bf4651bd2045b8c86429d55 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 06:42:01 +0100
-Subject: [PATCH 32/91] soc: mediatek: PMIC wrap: don't duplicate the wrapper
+Subject: [PATCH 032/102] soc: mediatek: PMIC wrap: don't duplicate the
- data
+ wrapper data
 
 As we add support for more devices struct pmic_wrapper_type will grow and
 we do not really want to start duplicating all the elements in
@@ -13,6 +13,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   22 ++++++++--------------
  1 file changed, 8 insertions(+), 14 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 0d9b19a..340c4b5 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -376,9 +376,7 @@ struct pmic_wrapper {
@@ -53,7 +55,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  }
  
  static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
-@@ -697,7 +695,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -697,7 +695,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  
  	pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
  
@@ -62,7 +64,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
  
-@@ -742,7 +740,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -742,7 +740,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  	pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
  	pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
  	pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
@@ -71,7 +73,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	if (pwrap_is_mt8135(wrp))
  		pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
-@@ -836,7 +834,6 @@ static int pwrap_probe(struct platform_d
+@@ -836,7 +834,6 @@ static int pwrap_probe(struct platform_device *pdev)
  	struct device_node *np = pdev->dev.of_node;
  	const struct of_device_id *of_id =
  		of_match_device(of_pwrap_match_tbl, &pdev->dev);
@@ -79,7 +81,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	struct resource *res;
  
  	wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
-@@ -845,10 +842,7 @@ static int pwrap_probe(struct platform_d
+@@ -845,10 +842,7 @@ static int pwrap_probe(struct platform_device *pdev)
  
  	platform_set_drvdata(pdev, wrp);
  
@@ -91,3 +93,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	wrp->dev = &pdev->dev;
  
  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0033-soc-mediatek-PMIC-wrap-add-wrapper-callbacks-for-ini.patch

@@ -1,7 +1,7 @@
-From 35d879d80437cc6ed811538903e115dbcda777ac Mon Sep 17 00:00:00 2001
+From 756b919b7874cc241a276b4fc5bbec5b3fb4bca8 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 05:27:17 +0100
-Subject: [PATCH 33/91] soc: mediatek: PMIC wrap: add wrapper callbacks for
+Subject: [PATCH 033/102] soc: mediatek: PMIC wrap: add wrapper callbacks for
  init_reg_clock
 
 Split init_reg_clock up into SoC specific callbacks. The patch also
@@ -12,6 +12,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   70 ++++++++++++++++++----------------
  1 file changed, 38 insertions(+), 32 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 340c4b5..b22b664 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -354,24 +354,6 @@ enum pwrap_type {
@@ -53,7 +55,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static inline int pwrap_is_mt8135(struct pmic_wrapper *wrp)
  {
  	return wrp->master->type == PWRAP_MT8135;
-@@ -578,20 +567,23 @@ static int pwrap_init_sidly(struct pmic_
+@@ -578,20 +567,23 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp)
  	return 0;
  }
  
@@ -90,7 +92,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	return 0;
  }
-@@ -699,7 +691,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -699,7 +691,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  
  	pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
  
@@ -99,7 +101,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	if (ret)
  		return ret;
  
-@@ -814,6 +806,20 @@ static const struct regmap_config pwrap_
+@@ -814,6 +806,20 @@ static const struct regmap_config pwrap_regmap_config = {
  	.max_register = 0xffff,
  };
  
@@ -120,3 +122,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static struct of_device_id of_pwrap_match_tbl[] = {
  	{
  		.compatible = "mediatek,mt8135-pwrap",
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0034-soc-mediatek-PMIC-wrap-split-SoC-specific-init-into-.patch

@@ -1,8 +1,8 @@
-From d82889cec95358b917fcf29fc3214980deb138b9 Mon Sep 17 00:00:00 2001
+From a1bbd630710d5da89a9c347c84d7badd30e7e68a Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 10:12:00 +0100
-Subject: [PATCH 34/91] soc: mediatek: PMIC wrap: split SoC specific init into
+Subject: [PATCH 034/102] soc: mediatek: PMIC wrap: split SoC specific init
- callback
+ into callback
 
 This patch moves the SoC specific wrapper init code into separate callback
 to avoid pwrap_init() getting too large. This is done by adding a new
@@ -16,6 +16,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   67 +++++++++++++++++++++-------------
  1 file changed, 42 insertions(+), 25 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index b22b664..22c89e9 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -372,6 +372,7 @@ struct pmic_wrapper_type {
@@ -26,7 +28,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  };
  
  static inline int pwrap_is_mt8135(struct pmic_wrapper *wrp)
-@@ -665,6 +666,41 @@ static int pwrap_init_cipher(struct pmic
+@@ -665,6 +666,41 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  	return 0;
  }
  
@@ -68,7 +70,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static int pwrap_init(struct pmic_wrapper *wrp)
  {
  	int ret;
-@@ -743,31 +779,10 @@ static int pwrap_init(struct pmic_wrappe
+@@ -743,31 +779,10 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  	pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
  	pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
  
@@ -104,7 +106,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	}
  
  	/* Setup the init done registers */
-@@ -811,6 +826,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -811,6 +826,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
  	.type = PWRAP_MT8135,
  	.arb_en_all = 0x1ff,
  	.init_reg_clock = pwrap_mt8135_init_reg_clock,
@@ -112,7 +114,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  };
  
  static struct pmic_wrapper_type pwrap_mt8173 = {
-@@ -818,6 +834,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -818,6 +834,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
  	.type = PWRAP_MT8173,
  	.arb_en_all = 0x3f,
  	.init_reg_clock = pwrap_mt8173_init_reg_clock,
@@ -120,3 +122,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  };
  
  static struct of_device_id of_pwrap_match_tbl[] = {
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0035-soc-mediatek-PMIC-wrap-WRAP_INT_EN-needs-a-different.patch

@@ -1,7 +1,7 @@
-From 613acba0068461948e6b5283df03d7c1e1583a40 Mon Sep 17 00:00:00 2001
+From 274fd9ba57170de88bbdf522cbd6c290c2e51fb8 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 10:14:39 +0100
-Subject: [PATCH 35/91] soc: mediatek: PMIC wrap: WRAP_INT_EN needs a
+Subject: [PATCH 035/102] soc: mediatek: PMIC wrap: WRAP_INT_EN needs a
  different bitmask for MT2701/7623
 
 MT2701 and MT7623 use a different bitmask for PWRAP_INT_EN.
@@ -11,6 +11,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |    5 ++++-
  1 file changed, 4 insertions(+), 1 deletion(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 22c89e9..9df1135 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -371,6 +371,7 @@ struct pmic_wrapper_type {
@@ -21,7 +23,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	int (*init_reg_clock)(struct pmic_wrapper *wrp);
  	int (*init_soc_specific)(struct pmic_wrapper *wrp);
  };
-@@ -825,6 +826,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -825,6 +826,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
  	.regs = mt8135_regs,
  	.type = PWRAP_MT8135,
  	.arb_en_all = 0x1ff,
@@ -29,7 +31,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	.init_reg_clock = pwrap_mt8135_init_reg_clock,
  	.init_soc_specific = pwrap_mt8135_init_soc_specific,
  };
-@@ -833,6 +835,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -833,6 +835,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
  	.regs = mt8173_regs,
  	.type = PWRAP_MT8173,
  	.arb_en_all = 0x3f,
@@ -37,7 +39,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	.init_reg_clock = pwrap_mt8173_init_reg_clock,
  	.init_soc_specific = pwrap_mt8173_init_soc_specific,
  };
-@@ -946,7 +949,7 @@ static int pwrap_probe(struct platform_d
+@@ -946,7 +949,7 @@ static int pwrap_probe(struct platform_device *pdev)
  			PWRAP_WDT_SRC_MASK_NO_STAUPD : PWRAP_WDT_SRC_MASK_ALL;
  	pwrap_writel(wrp, wdt_src, PWRAP_WDT_SRC_EN);
  	pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
@@ -46,3 +48,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	irq = platform_get_irq(pdev, 0);
  	ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, IRQF_TRIGGER_HIGH,
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0036-soc-mediatek-PMIC-wrap-SPI_WRITE-needs-a-different-b.patch

@@ -1,8 +1,8 @@
-From 1186088ab86b7286e1920dcbfbbbf2627a0daeda Mon Sep 17 00:00:00 2001
+From 511e697282c6425950b95373ac8dc59a42fd2485 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 10:21:42 +0100
-Subject: [PATCH 36/91] soc: mediatek: PMIC wrap: SPI_WRITE needs a different
+Subject: [PATCH 036/102] soc: mediatek: PMIC wrap: SPI_WRITE needs a
- bitmask for MT2701/7623
+ different bitmask for MT2701/7623
 
 Different SoCs will use different bitmask for the SPI_WRITE command. This
 patch defines the bitmask in the pmic_wrapper_type struct. This allows us
@@ -13,6 +13,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   11 +++++++----
  1 file changed, 7 insertions(+), 4 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 9df1135..8ce1bad 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -372,6 +372,7 @@ struct pmic_wrapper_type {
@@ -23,7 +25,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	int (*init_reg_clock)(struct pmic_wrapper *wrp);
  	int (*init_soc_specific)(struct pmic_wrapper *wrp);
  };
-@@ -511,15 +512,15 @@ static int pwrap_reset_spislave(struct p
+@@ -511,15 +512,15 @@ static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
  	pwrap_writel(wrp, 1, PWRAP_MAN_EN);
  	pwrap_writel(wrp, 0, PWRAP_DIO_EN);
  
@@ -43,7 +45,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  				PWRAP_MAN_CMD);
  
  	ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
-@@ -827,6 +828,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -827,6 +828,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
  	.type = PWRAP_MT8135,
  	.arb_en_all = 0x1ff,
  	.int_en_all = ~(BIT(31) | BIT(1)),
@@ -51,7 +53,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	.init_reg_clock = pwrap_mt8135_init_reg_clock,
  	.init_soc_specific = pwrap_mt8135_init_soc_specific,
  };
-@@ -836,6 +838,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -836,6 +838,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
  	.type = PWRAP_MT8173,
  	.arb_en_all = 0x3f,
  	.int_en_all = ~(BIT(31) | BIT(1)),
@@ -59,3 +61,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	.init_reg_clock = pwrap_mt8173_init_reg_clock,
  	.init_soc_specific = pwrap_mt8173_init_soc_specific,
  };
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0037-soc-mediatek-PMIC-wrap-move-wdt_src-into-the-pmic_wr.patch

@@ -1,7 +1,7 @@
-From 95f72db32afd545b88eaa04802736f1f84242a9f Mon Sep 17 00:00:00 2001
+From 6aecbc79322efd3068c6140f74a68654fbe5b5f6 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 10:48:35 +0100
-Subject: [PATCH 37/91] soc: mediatek: PMIC wrap: move wdt_src into the
+Subject: [PATCH 037/102] soc: mediatek: PMIC wrap: move wdt_src into the
  pmic_wrapper_type struct
 
 Different SoCs will use different bitmask for the wdt_src. This patch
@@ -13,6 +13,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |    9 +++++----
  1 file changed, 5 insertions(+), 4 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 8ce1bad..aa54df3 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -373,6 +373,7 @@ struct pmic_wrapper_type {
@@ -23,7 +25,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	int (*init_reg_clock)(struct pmic_wrapper *wrp);
  	int (*init_soc_specific)(struct pmic_wrapper *wrp);
  };
-@@ -829,6 +830,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -829,6 +830,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
  	.arb_en_all = 0x1ff,
  	.int_en_all = ~(BIT(31) | BIT(1)),
  	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
@@ -31,7 +33,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	.init_reg_clock = pwrap_mt8135_init_reg_clock,
  	.init_soc_specific = pwrap_mt8135_init_soc_specific,
  };
-@@ -839,6 +841,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -839,6 +841,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
  	.arb_en_all = 0x3f,
  	.int_en_all = ~(BIT(31) | BIT(1)),
  	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
@@ -39,7 +41,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	.init_reg_clock = pwrap_mt8173_init_reg_clock,
  	.init_soc_specific = pwrap_mt8173_init_soc_specific,
  };
-@@ -858,7 +861,7 @@ MODULE_DEVICE_TABLE(of, of_pwrap_match_t
+@@ -858,7 +861,7 @@ MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
  
  static int pwrap_probe(struct platform_device *pdev)
  {
@@ -48,7 +50,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	struct pmic_wrapper *wrp;
  	struct device_node *np = pdev->dev.of_node;
  	const struct of_device_id *of_id =
-@@ -948,9 +951,7 @@ static int pwrap_probe(struct platform_d
+@@ -948,9 +951,7 @@ static int pwrap_probe(struct platform_device *pdev)
  	 * Since STAUPD was not used on mt8173 platform,
  	 * so STAUPD of WDT_SRC which should be turned off
  	 */
@@ -59,3 +61,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
  	pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0038-soc-mediatek-PMIC-wrap-remove-pwrap_is_mt8135-and-pw.patch

@@ -1,8 +1,8 @@
-From bb19fd13b1ed629873ea144b22c4764aa4baa5ef Mon Sep 17 00:00:00 2001
+From da09b34ad22e8f065a02af114668f7d86357244a Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 10:54:18 +0100
-Subject: [PATCH 38/91] soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and
+Subject: [PATCH 038/102] soc: mediatek: PMIC wrap: remove pwrap_is_mt8135()
- pwrap_is_mt8173()
+ and pwrap_is_mt8173()
 
 With more SoCs being added the list of helper functions like these would
 grow. To mitigate this problem we remove the existing helpers and change
@@ -18,6 +18,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   28 ++++++++++++----------------
  1 file changed, 12 insertions(+), 16 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index aa54df3..a2bacda 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -374,20 +374,11 @@ struct pmic_wrapper_type {
@@ -42,7 +44,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
  {
  	return readl(wrp->base + wrp->master->regs[reg]);
-@@ -619,11 +610,14 @@ static int pwrap_init_cipher(struct pmic
+@@ -619,11 +610,14 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  	pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
  	pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
  
@@ -59,7 +61,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	}
  
  	/* Config cipher mode @PMIC */
-@@ -713,7 +707,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -713,7 +707,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  	if (wrp->rstc_bridge)
  		reset_control_reset(wrp->rstc_bridge);
  
@@ -68,7 +70,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		/* Enable DCM */
  		pwrap_writel(wrp, 3, PWRAP_DCM_EN);
  		pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
-@@ -773,7 +767,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -773,7 +767,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  	pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
  	pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
  
@@ -77,7 +79,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
  
  	pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
-@@ -793,7 +787,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -793,7 +787,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  	pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
  	pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
  
@@ -86,7 +88,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
  		writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
  	}
-@@ -831,6 +825,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -831,6 +825,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
  	.int_en_all = ~(BIT(31) | BIT(1)),
  	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
  	.wdt_src = PWRAP_WDT_SRC_MASK_ALL,
@@ -94,7 +96,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	.init_reg_clock = pwrap_mt8135_init_reg_clock,
  	.init_soc_specific = pwrap_mt8135_init_soc_specific,
  };
-@@ -842,6 +837,7 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -842,6 +837,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
  	.int_en_all = ~(BIT(31) | BIT(1)),
  	.spi_w = PWRAP_MAN_CMD_SPI_WRITE,
  	.wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
@@ -102,7 +104,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	.init_reg_clock = pwrap_mt8173_init_reg_clock,
  	.init_soc_specific = pwrap_mt8173_init_soc_specific,
  };
-@@ -889,7 +885,7 @@ static int pwrap_probe(struct platform_d
+@@ -889,7 +885,7 @@ static int pwrap_probe(struct platform_device *pdev)
  		return ret;
  	}
  
@@ -111,3 +113,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  				"pwrap-bridge");
  		wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0039-soc-mediatek-PMIC-wrap-add-a-slave-specific-struct.patch

@@ -1,7 +1,8 @@
-From daa4d054bb0557799c8b324d7aa5f0a3a4a7b078 Mon Sep 17 00:00:00 2001
+From 21bdcd324f769545b1765fe391d939a1edd07cbb Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 09:55:08 +0100
-Subject: [PATCH 39/91] soc: mediatek: PMIC wrap: add a slave specific struct
+Subject: [PATCH 039/102] soc: mediatek: PMIC wrap: add a slave specific
+ struct
 
 This patch adds a new struct pwrap_slv_type that we use to store the slave
 specific data. The patch adds 2 new helper functions to access the dew
@@ -12,6 +13,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |  159 ++++++++++++++++++++++++----------
  1 file changed, 112 insertions(+), 47 deletions(-)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index a2bacda..bcc841e 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -69,33 +69,54 @@
@@ -123,7 +126,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	struct clk *clk_spi;
  	struct clk *clk_wrap;
  	struct reset_control *rstc;
-@@ -544,7 +575,8 @@ static int pwrap_init_sidly(struct pmic_
+@@ -544,7 +575,8 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp)
  
  	for (i = 0; i < 4; i++) {
  		pwrap_writel(wrp, i, PWRAP_SIDLY);
@@ -133,7 +136,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		if (rdata == PWRAP_DEW_READ_TEST_VAL) {
  			dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
  			pass |= 1 << i;
-@@ -593,7 +625,8 @@ static bool pwrap_is_pmic_cipher_ready(s
+@@ -593,7 +625,8 @@ static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
  	u32 rdata;
  	int ret;
  
@@ -143,7 +146,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	if (ret)
  		return 0;
  
-@@ -621,12 +654,12 @@ static int pwrap_init_cipher(struct pmic
+@@ -621,12 +654,12 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  	}
  
  	/* Config cipher mode @PMIC */
@@ -162,7 +165,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	/* wait for cipher data ready@AP */
  	ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
-@@ -643,7 +676,7 @@ static int pwrap_init_cipher(struct pmic
+@@ -643,7 +676,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  	}
  
  	/* wait for cipher mode idle */
@@ -171,7 +174,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
  	if (ret) {
  		dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
-@@ -653,9 +686,11 @@ static int pwrap_init_cipher(struct pmic
+@@ -653,9 +686,11 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  	pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
  
  	/* Write Test */
@@ -186,7 +189,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
  		return -EFAULT;
  	}
-@@ -677,8 +712,10 @@ static int pwrap_mt8135_init_soc_specifi
+@@ -677,8 +712,10 @@ static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
  	writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
  
  	/* enable PMIC event out and sources */
@@ -199,7 +202,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		dev_err(wrp->dev, "enable dewrap fail\n");
  		return -EFAULT;
  	}
-@@ -689,8 +726,10 @@ static int pwrap_mt8135_init_soc_specifi
+@@ -689,8 +726,10 @@ static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
  static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
  {
  	/* PMIC_DEWRAP enables */
@@ -212,7 +215,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		dev_err(wrp->dev, "enable dewrap fail\n");
  		return -EFAULT;
  	}
-@@ -734,7 +773,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -734,7 +773,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  		return ret;
  
  	/* Enable dual IO mode */
@@ -221,7 +224,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	/* Check IDLE & INIT_DONE in advance */
  	ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
-@@ -746,7 +785,7 @@ static int pwrap_init(struct pmic_wrappe
+@@ -746,7 +785,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  	pwrap_writel(wrp, 1, PWRAP_DIO_EN);
  
  	/* Read Test */
@@ -230,7 +233,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	if (rdata != PWRAP_DEW_READ_TEST_VAL) {
  		dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
  				PWRAP_DEW_READ_TEST_VAL, rdata);
-@@ -759,12 +798,13 @@ static int pwrap_init(struct pmic_wrappe
+@@ -759,12 +798,13 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  		return ret;
  
  	/* Signature checking - using CRC */
@@ -246,7 +249,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
  
  	if (wrp->master->type == PWRAP_MT8135)
-@@ -818,6 +858,21 @@ static const struct regmap_config pwrap_
+@@ -818,6 +858,21 @@ static const struct regmap_config pwrap_regmap_config = {
  	.max_register = 0xffff,
  };
  
@@ -268,7 +271,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static struct pmic_wrapper_type pwrap_mt8135 = {
  	.regs = mt8135_regs,
  	.type = PWRAP_MT8135,
-@@ -862,8 +917,17 @@ static int pwrap_probe(struct platform_d
+@@ -862,8 +917,17 @@ static int pwrap_probe(struct platform_device *pdev)
  	struct device_node *np = pdev->dev.of_node;
  	const struct of_device_id *of_id =
  		of_match_device(of_pwrap_match_tbl, &pdev->dev);
@@ -286,7 +289,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
  	if (!wrp)
  		return -ENOMEM;
-@@ -871,6 +935,7 @@ static int pwrap_probe(struct platform_d
+@@ -871,6 +935,7 @@ static int pwrap_probe(struct platform_device *pdev)
  	platform_set_drvdata(pdev, wrp);
  
  	wrp->master = of_id->data;
@@ -294,3 +297,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	wrp->dev = &pdev->dev;
  
  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0040-soc-mediatek-PMIC-wrap-add-mt6323-slave-support.patch

@@ -1,7 +1,7 @@
-From 15143b59a26a06e890e2ba3c9944b3f751ce39bd Mon Sep 17 00:00:00 2001
+From 4418ba9a0bb105f00259d10ceb16f9e27199e9b0 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 11:40:43 +0100
-Subject: [PATCH 40/91] soc: mediatek: PMIC wrap: add mt6323 slave support
+Subject: [PATCH 040/102] soc: mediatek: PMIC wrap: add mt6323 slave support
 
 Add support for MT6323 slaves. This PMIC can be found on MT2701 and MT7623
 EVB. The only function that we need to touch is pwrap_init_cipher().
@@ -11,6 +11,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |   43 ++++++++++++++++++++++++++++++++++
  1 file changed, 43 insertions(+)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index bcc841e..0e4ebb8 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -93,6 +93,27 @@ enum dew_regs {
@@ -49,7 +51,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	PMIC_MT6397,
  };
  
-@@ -661,6 +683,19 @@ static int pwrap_init_cipher(struct pmic
+@@ -661,6 +683,19 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  	pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 0x1);
  	pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], 0x1);
  
@@ -69,7 +71,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	/* wait for cipher data ready@AP */
  	ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
  	if (ret) {
-@@ -858,6 +893,11 @@ static const struct regmap_config pwrap_
+@@ -858,6 +893,11 @@ static const struct regmap_config pwrap_regmap_config = {
  	.max_register = 0xffff,
  };
  
@@ -81,7 +83,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static const struct pwrap_slv_type pmic_mt6397 = {
  	.dew_regs = mt6397_regs,
  	.type = PMIC_MT6397,
-@@ -865,6 +905,9 @@ static const struct pwrap_slv_type pmic_
+@@ -865,6 +905,9 @@ static const struct pwrap_slv_type pmic_mt6397 = {
  
  static const struct of_device_id of_slave_match_tbl[] = {
  	{
@@ -91,3 +93,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		.compatible = "mediatek,mt6397",
  		.data = &pmic_mt6397,
  	}, {
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0041-soc-mediatek-PMIC-wrap-add-MT2701-7623-support.patch

@@ -1,7 +1,7 @@
-From 2f5df30a7b913069c8fce22dc702e0d7c76ef361 Mon Sep 17 00:00:00 2001
+From 7736d97fe2c6c71c9009a1b45a94de06bfc94a37 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 20 Jan 2016 12:09:14 +0100
-Subject: [PATCH 41/91] soc: mediatek: PMIC wrap: add MT2701/7623 support
+Subject: [PATCH 041/102] soc: mediatek: PMIC wrap: add MT2701/7623 support
 
 Add the registers, callbacks and data structures required to make the
 wrapper work on MT2701 and MT7623.
@@ -11,6 +11,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/soc/mediatek/mtk-pmic-wrap.c |  154 ++++++++++++++++++++++++++++++++++
  1 file changed, 154 insertions(+)
 
+diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
+index 0e4ebb8..3c3e56d 100644
 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
 @@ -52,6 +52,7 @@
@@ -136,7 +138,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	PWRAP_MT8135,
  	PWRAP_MT8173,
  };
-@@ -637,6 +732,31 @@ static int pwrap_mt8173_init_reg_clock(s
+@@ -637,6 +732,31 @@ static int pwrap_mt8173_init_reg_clock(struct pmic_wrapper *wrp)
  	return 0;
  }
  
@@ -168,7 +170,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
  {
  	return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
-@@ -670,6 +790,7 @@ static int pwrap_init_cipher(struct pmic
+@@ -670,6 +790,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  		pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
  		pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
  		break;
@@ -176,7 +178,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	case PWRAP_MT8173:
  		pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
  		break;
-@@ -772,6 +893,24 @@ static int pwrap_mt8173_init_soc_specifi
+@@ -772,6 +893,24 @@ static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
  	return 0;
  }
  
@@ -201,7 +203,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static int pwrap_init(struct pmic_wrapper *wrp)
  {
  	int ret;
-@@ -916,6 +1055,18 @@ static const struct of_device_id of_slav
+@@ -916,6 +1055,18 @@ static const struct of_device_id of_slave_match_tbl[] = {
  };
  MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
  
@@ -220,7 +222,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static struct pmic_wrapper_type pwrap_mt8135 = {
  	.regs = mt8135_regs,
  	.type = PWRAP_MT8135,
-@@ -942,6 +1093,9 @@ static struct pmic_wrapper_type pwrap_mt
+@@ -942,6 +1093,9 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
  
  static struct of_device_id of_pwrap_match_tbl[] = {
  	{
@@ -230,3 +232,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		.compatible = "mediatek,mt8135-pwrap",
  		.data = &pwrap_mt8135,
  	}, {
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0042-dt-bindings-mfd-Add-bindings-for-the-MediaTek-MT6323.patch

@@ -1,8 +1,8 @@
-From edc6e6a2f10f7b7fc94dc6147c86520e5a439d16 Mon Sep 17 00:00:00 2001
+From c14dc2993a272c706650502ec579ceabe5f2355e Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 10 Jan 2016 17:12:37 +0100
-Subject: [PATCH 42/91] dt-bindings: mfd: Add bindings for the MediaTek MT6323
+Subject: [PATCH 042/102] dt-bindings: mfd: Add bindings for the MediaTek
- PMIC
+ MT6323 PMIC
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 Acked-by: Rob Herring <robh@kernel.org>
@@ -11,6 +11,8 @@ Cc: devicetree@vger.kernel.org
  Documentation/devicetree/bindings/mfd/mt6397.txt |   10 ++++++----
  1 file changed, 6 insertions(+), 4 deletions(-)
 
+diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt
+index 15043e6..949c85f 100644
 --- a/Documentation/devicetree/bindings/mfd/mt6397.txt
 +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
 @@ -1,6 +1,6 @@
@@ -22,7 +24,7 @@ Cc: devicetree@vger.kernel.org
  - Regulator
  - RTC
  - Audio codec
-@@ -8,14 +8,14 @@ MT6397 is a multifunction device with th
+@@ -8,14 +8,14 @@ MT6397 is a multifunction device with the following sub modules:
  - Clock
  
  It is interfaced to host controller using SPI interface by a proprietary hardware
@@ -48,3 +50,6 @@ Cc: devicetree@vger.kernel.org
  - codec
  	Required properties:
  		- compatible: "mediatek,mt6397-codec"
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0043-mfd-mt6397-int_con-and-int_status-may-vary-in-locati.patch

@@ -1,7 +1,7 @@
-From f97549172878651725a719a4fc4b610613fe5843 Mon Sep 17 00:00:00 2001
+From 8269ed007349714e9ef0e3408a68159d763145dd Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Fri, 8 Jan 2016 08:33:17 +0100
-Subject: [PATCH 43/91] mfd: mt6397: int_con and int_status may vary in
+Subject: [PATCH 043/102] mfd: mt6397: int_con and int_status may vary in
  location
 
 MT6323 has the INT_CON and INT_STATUS located at a different position.
@@ -13,9 +13,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  include/linux/mfd/mt6397/core.h |    2 ++
  2 files changed, 19 insertions(+), 10 deletions(-)
 
+diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
+index 1749c1c..75ad0fe 100644
 --- a/drivers/mfd/mt6397-core.c
 +++ b/drivers/mfd/mt6397-core.c
-@@ -69,8 +69,10 @@ static void mt6397_irq_sync_unlock(struc
+@@ -69,8 +69,10 @@ static void mt6397_irq_sync_unlock(struct irq_data *data)
  {
  	struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
  
@@ -28,7 +30,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	mutex_unlock(&mt6397->irqlock);
  }
-@@ -147,8 +149,8 @@ static irqreturn_t mt6397_irq_thread(int
+@@ -147,8 +149,8 @@ static irqreturn_t mt6397_irq_thread(int irq, void *data)
  {
  	struct mt6397_chip *mt6397 = data;
  
@@ -39,7 +41,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	return IRQ_HANDLED;
  }
-@@ -177,8 +179,8 @@ static int mt6397_irq_init(struct mt6397
+@@ -177,8 +179,8 @@ static int mt6397_irq_init(struct mt6397_chip *mt6397)
  	mutex_init(&mt6397->irqlock);
  
  	/* Mask all interrupt sources */
@@ -50,7 +52,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
  		MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
-@@ -203,8 +205,8 @@ static int mt6397_irq_suspend(struct dev
+@@ -203,8 +205,8 @@ static int mt6397_irq_suspend(struct device *dev)
  {
  	struct mt6397_chip *chip = dev_get_drvdata(dev);
  
@@ -61,7 +63,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	enable_irq_wake(chip->irq);
  
-@@ -215,8 +217,8 @@ static int mt6397_irq_resume(struct devi
+@@ -215,8 +217,8 @@ static int mt6397_irq_resume(struct device *dev)
  {
  	struct mt6397_chip *chip = dev_get_drvdata(dev);
  
@@ -72,7 +74,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	disable_irq_wake(chip->irq);
  
-@@ -237,6 +239,11 @@ static int mt6397_probe(struct platform_
+@@ -237,6 +239,11 @@ static int mt6397_probe(struct platform_device *pdev)
  		return -ENOMEM;
  
  	mt6397->dev = &pdev->dev;
@@ -84,6 +86,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	/*
  	 * mt6397 MFD is child device of soc pmic wrapper.
  	 * Regmap is set from its parent.
+diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
+index 45b8e8a..d678f52 100644
 --- a/include/linux/mfd/mt6397/core.h
 +++ b/include/linux/mfd/mt6397/core.h
 @@ -60,6 +60,8 @@ struct mt6397_chip {
@@ -95,3 +99,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  };
  
  #endif /* __MFD_MT6397_CORE_H__ */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0044-mfd-mt6397-add-support-for-different-Slave-types.patch

@@ -1,13 +1,15 @@
-From 5fbdf1ebc267561781ce812793cd35e63fa39614 Mon Sep 17 00:00:00 2001
+From c6c447480e51301faa2254c7316ab075e20c4b0c Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Fri, 8 Jan 2016 08:41:52 +0100
-Subject: [PATCH 44/91] mfd: mt6397: add support for different Slave types
+Subject: [PATCH 044/102] mfd: mt6397: add support for different Slave types
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
  drivers/mfd/mt6397-core.c |   58 ++++++++++++++++++++++++++++++++-------------
  1 file changed, 41 insertions(+), 17 deletions(-)
 
+diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
+index 75ad0fe..aa91606 100644
 --- a/drivers/mfd/mt6397-core.c
 +++ b/drivers/mfd/mt6397-core.c
 @@ -24,6 +24,9 @@
@@ -20,7 +22,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static const struct resource mt6397_rtc_resources[] = {
  	{
  		.start = MT6397_RTC_BASE,
-@@ -232,39 +235,60 @@ static SIMPLE_DEV_PM_OPS(mt6397_pm_ops,
+@@ -232,39 +235,60 @@ static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
  static int mt6397_probe(struct platform_device *pdev)
  {
  	int ret;
@@ -98,3 +100,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	return ret;
  }
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0045-mfd-mt6397-add-MT6323-support-to-MT6397-driver.patch

@@ -1,7 +1,7 @@
-From 2a1c7879d8c3eac4313abc011adbefbc50fd5f92 Mon Sep 17 00:00:00 2001
+From 0ae7153c9f00361c3e6dac9da0c2d994557953f5 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Fri, 8 Jan 2016 04:09:43 +0100
-Subject: [PATCH 45/91] mfd: mt6397: add MT6323 support to MT6397 driver
+Subject: [PATCH 045/102] mfd: mt6397: add MT6323 support to MT6397 driver
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
@@ -12,6 +12,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  create mode 100644 include/linux/mfd/mt6323/core.h
  create mode 100644 include/linux/mfd/mt6323/registers.h
 
+diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
+index aa91606..8234cd3 100644
 --- a/drivers/mfd/mt6397-core.c
 +++ b/drivers/mfd/mt6397-core.c
 @@ -19,11 +19,14 @@
@@ -29,7 +31,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  #define MT6391_CID_CODE		0x91
  #define MT6397_CID_CODE		0x97
  
-@@ -40,6 +43,13 @@ static const struct resource mt6397_rtc_
+@@ -40,6 +43,13 @@ static const struct resource mt6397_rtc_resources[] = {
  	},
  };
  
@@ -43,7 +45,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static const struct mfd_cell mt6397_devs[] = {
  	{
  		.name = "mt6397-rtc",
-@@ -261,6 +271,15 @@ static int mt6397_probe(struct platform_
+@@ -261,6 +271,15 @@ static int mt6397_probe(struct platform_device *pdev)
  	}
  
  	switch (id & 0xff) {
@@ -59,7 +61,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	case MT6397_CID_CODE:
  	case MT6391_CID_CODE:
  		pmic->int_con[0] = MT6397_INT_CON0;
-@@ -302,6 +321,7 @@ static int mt6397_remove(struct platform
+@@ -302,6 +321,7 @@ static int mt6397_remove(struct platform_device *pdev)
  
  static const struct of_device_id mt6397_of_match[] = {
  	{ .compatible = "mediatek,mt6397" },
@@ -67,6 +69,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	{ }
  };
  MODULE_DEVICE_TABLE(of, mt6397_of_match);
+diff --git a/include/linux/mfd/mt6323/core.h b/include/linux/mfd/mt6323/core.h
+new file mode 100644
+index 0000000..06d0ec3
 --- /dev/null
 +++ b/include/linux/mfd/mt6323/core.h
 @@ -0,0 +1,36 @@
@@ -106,6 +111,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +};
 +
 +#endif /* __MFD_MT6323_CORE_H__ */
+diff --git a/include/linux/mfd/mt6323/registers.h b/include/linux/mfd/mt6323/registers.h
+new file mode 100644
+index 0000000..160f3c0
 --- /dev/null
 +++ b/include/linux/mfd/mt6323/registers.h
 @@ -0,0 +1,408 @@
@@ -517,3 +525,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#define MT6323_ACCDET_CON16       0x079A
 +
 +#endif /* __MFD_MT6323_REGISTERS_H__ */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0046-regulator-Add-document-for-MT6323-regulator.patch

@@ -1,7 +1,7 @@
-From 34177561c62ed881c862f9ece652ca1ca5994796 Mon Sep 17 00:00:00 2001
+From f536a600e0e20fd57475415ce5b3d909441d53b6 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 10 Jan 2016 17:31:46 +0100
-Subject: [PATCH 46/91] regulator: Add document for MT6323 regulator
+Subject: [PATCH 046/102] regulator: Add document for MT6323 regulator
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 Cc: devicetree@vger.kernel.org
@@ -10,6 +10,9 @@ Cc: devicetree@vger.kernel.org
  1 file changed, 239 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
 
+diff --git a/Documentation/devicetree/bindings/regulator/mt6323-regulator.txt b/Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
+new file mode 100644
+index 0000000..9fd95e7
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
 @@ -0,0 +1,239 @@
@@ -252,3 +255,6 @@ Cc: devicetree@vger.kernel.org
 +			};
 +		};
 +	};
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0047-regulator-mt6323-Add-support-for-MT6323-regulator.patch

@@ -1,7 +1,7 @@
-From 2a33aa927dece6ac6d10caff48897c8ac6a66c1b Mon Sep 17 00:00:00 2001
+From 94c08223cd696d872cda7d9aa4e817956d0a0b84 Mon Sep 17 00:00:00 2001
 From: Chen Zhong <chen.zhong@mediatek.com>
 Date: Fri, 8 Jan 2016 04:17:37 +0100
-Subject: [PATCH 47/91] regulator: mt6323: Add support for MT6323 regulator
+Subject: [PATCH 047/102] regulator: mt6323: Add support for MT6323 regulator
 
 The MT6323 is a regulator found on boards based on MediaTek MT7623 and
 probably other SoCs. It is a so called pmic and connects as a slave to
@@ -18,9 +18,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  create mode 100644 drivers/regulator/mt6323-regulator.c
  create mode 100644 include/linux/regulator/mt6323-regulator.h
 
+diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
+index 8df0b0e..4aec931 100644
 --- a/drivers/regulator/Kconfig
 +++ b/drivers/regulator/Kconfig
-@@ -453,6 +453,15 @@ config REGULATOR_MT6311
+@@ -452,6 +452,15 @@ config REGULATOR_MT6311
  	  This driver supports the control of different power rails of device
  	  through regulator interface.
  
@@ -36,9 +38,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  config REGULATOR_MT6397
  	tristate "MediaTek MT6397 PMIC"
  	depends on MFD_MT6397
+diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
+index 0f81749..b42a84e 100644
 --- a/drivers/regulator/Makefile
 +++ b/drivers/regulator/Makefile
-@@ -60,6 +60,7 @@ obj-$(CONFIG_REGULATOR_MC13783) += mc137
+@@ -60,6 +60,7 @@ obj-$(CONFIG_REGULATOR_MC13783) += mc13783-regulator.o
  obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o
  obj-$(CONFIG_REGULATOR_MC13XXX_CORE) +=  mc13xxx-regulator-core.o
  obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o
@@ -46,6 +50,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  obj-$(CONFIG_REGULATOR_MT6397)	+= mt6397-regulator.o
  obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o
  obj-$(CONFIG_REGULATOR_QCOM_SMD_RPM) += qcom_smd-regulator.o
+diff --git a/drivers/regulator/mt6323-regulator.c b/drivers/regulator/mt6323-regulator.c
+new file mode 100644
+index 0000000..28ebbda
 --- /dev/null
 +++ b/drivers/regulator/mt6323-regulator.c
 @@ -0,0 +1,432 @@
@@ -481,6 +488,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +MODULE_AUTHOR("Chen Zhong <chen.zhong@mediatek.com>");
 +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6397 PMIC");
 +MODULE_LICENSE("GPL v2");
+diff --git a/include/linux/regulator/mt6323-regulator.h b/include/linux/regulator/mt6323-regulator.h
+new file mode 100644
+index 0000000..67011cd
 --- /dev/null
 +++ b/include/linux/regulator/mt6323-regulator.h
 @@ -0,0 +1,52 @@
@@ -536,3 +546,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#define MT6323_MAX_REGULATOR	MT6323_ID_RG_MAX
 +
 +#endif /* __LINUX_REGULATOR_MT6323_H */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0048-net-next-mediatek-document-MediaTek-SoC-ethernet-bin.patch

@@ -1,7 +1,7 @@
-From caa2186644606dad07a603905ebabb8068828ebf Mon Sep 17 00:00:00 2001
+From 6efc8d9081b70dcf71d7e8efd7b51d48ee2541be Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 2 Mar 2016 07:18:52 +0100
-Subject: [PATCH 48/91] net-next: mediatek: document MediaTek SoC ethernet
+Subject: [PATCH 048/102] net-next: mediatek: document MediaTek SoC ethernet
  binding
 
 This adds the binding documentation for the MediaTek Ethernet
@@ -15,6 +15,9 @@ Cc: devicetree@vger.kernel.org
  1 file changed, 77 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/net/mediatek-net.txt
 
+diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
+new file mode 100644
+index 0000000..5ca7929
 --- /dev/null
 +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
 @@ -0,0 +1,77 @@
@@ -95,3 +98,6 @@ Cc: devicetree@vger.kernel.org
 +		};
 +	};
 +};
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0049-net-next-mediatek-add-support-for-MT7623-ethernet.patch

@@ -1,7 +1,7 @@
-From 412449bacdb46b548fd08af19148019e2e979294 Mon Sep 17 00:00:00 2001
+From 8cc84aa65121135d7b120ce71b4f10f81230c818 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 2 Mar 2016 04:27:10 +0100
-Subject: [PATCH 49/91] net-next: mediatek: add support for MT7623 ethernet
+Subject: [PATCH 049/102] net-next: mediatek: add support for MT7623 ethernet
 
 Add ethernet support for MediaTek SoCs from the MT7623 family. These have
 dual GMAC. Depending on the exact version, there might be a built-in
@@ -26,6 +26,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  create mode 100644 drivers/net/ethernet/mediatek/mtk_eth_soc.c
  create mode 100644 drivers/net/ethernet/mediatek/mtk_eth_soc.h
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+new file mode 100644
+index 0000000..ba3afa5
 --- /dev/null
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 @@ -0,0 +1,1807 @@
@@ -1836,6 +1839,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +MODULE_LICENSE("GPL");
 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 +MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+new file mode 100644
+index 0000000..48a5292
 --- /dev/null
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 @@ -0,0 +1,421 @@
@@ -2260,3 +2266,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
 +
 +#endif /* MTK_ETH_H */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0050-net-next-mediatek-add-Kconfig-and-Makefile.patch

@@ -1,7 +1,7 @@
-From 8bc8e78ddec2c93d7fe3487dfdfeedd382e3b96f Mon Sep 17 00:00:00 2001
+From 31e907e5c3c2fc1c94d005bfccdd4a32b5a05f82 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 2 Mar 2016 04:32:43 +0100
-Subject: [PATCH 50/91] net-next: mediatek: add Kconfig and Makefile
+Subject: [PATCH 050/102] net-next: mediatek: add Kconfig and Makefile
 
 This patch adds the Makefile and Kconfig required to make the driver build.
 
@@ -15,6 +15,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  create mode 100644 drivers/net/ethernet/mediatek/Kconfig
  create mode 100644 drivers/net/ethernet/mediatek/Makefile
 
+diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
+index 31c5e47..cd28b95 100644
 --- a/drivers/net/ethernet/Kconfig
 +++ b/drivers/net/ethernet/Kconfig
 @@ -106,6 +106,7 @@ config LANTIQ_ETOP
@@ -25,6 +27,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  source "drivers/net/ethernet/mellanox/Kconfig"
  source "drivers/net/ethernet/micrel/Kconfig"
  source "drivers/net/ethernet/microchip/Kconfig"
+diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
+index 071f84e..c62191f 100644
 --- a/drivers/net/ethernet/Makefile
 +++ b/drivers/net/ethernet/Makefile
 @@ -46,6 +46,7 @@ obj-$(CONFIG_JME) += jme.o
@@ -35,6 +39,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
  obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/
  obj-$(CONFIG_NET_VENDOR_MICROCHIP) += microchip/
+diff --git a/drivers/net/ethernet/mediatek/Kconfig b/drivers/net/ethernet/mediatek/Kconfig
+new file mode 100644
+index 0000000..b0229f4
 --- /dev/null
 +++ b/drivers/net/ethernet/mediatek/Kconfig
 @@ -0,0 +1,17 @@
@@ -55,6 +62,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	  MediaTek MT2701/MT7623 chipset family.
 +
 +endif #NET_VENDOR_MEDIATEK
+diff --git a/drivers/net/ethernet/mediatek/Makefile b/drivers/net/ethernet/mediatek/Makefile
+new file mode 100644
+index 0000000..aa3f1c8
 --- /dev/null
 +++ b/drivers/net/ethernet/mediatek/Makefile
 @@ -0,0 +1,5 @@
@@ -63,3 +73,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#
 +
 +obj-$(CONFIG_NET_MEDIATEK_SOC)			+= mtk_eth_soc.o
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0051-net-next-mediatek-add-an-entry-to-MAINTAINERS.patch

@@ -1,7 +1,7 @@
-From d9b93fb0d4021694a2b7e47981cd9de67e83aa05 Mon Sep 17 00:00:00 2001
+From 514e4ce65a5f1b5bfa3cbca153f672844f093f0e Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 2 Mar 2016 04:34:04 +0100
-Subject: [PATCH 51/91] net-next: mediatek: add an entry to MAINTAINERS
+Subject: [PATCH 051/102] net-next: mediatek: add an entry to MAINTAINERS
 
 Add myself and Felix as the Maintainers for the MediaTek ethernet driver.
 
@@ -11,9 +11,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  MAINTAINERS |    7 +++++++
  1 file changed, 7 insertions(+)
 
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 233f834..73f0592 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -6907,6 +6907,13 @@ F:	include/uapi/linux/meye.h
+@@ -6902,6 +6902,13 @@ F:	include/uapi/linux/meye.h
  F:	include/uapi/linux/ivtv*
  F:	include/uapi/linux/uvcvideo.h
  
@@ -27,3 +29,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  MEDIATEK MT7601U WIRELESS LAN DRIVER
  M:	Jakub Kicinski <kubakici@wp.pl>
  L:	linux-wireless@vger.kernel.org
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0052-clk-dont-disable-unused-clocks.patch

@@ -1,13 +1,15 @@
-From cbcbd319d905cdcf4a71003b5634137fee03855b Mon Sep 17 00:00:00 2001
+From 5238c5d1d38661955ed3b52f45c46e00bfc9eb6e Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Thu, 7 Apr 2016 07:18:35 +0200
-Subject: [PATCH 60/91] clk: dont disable unused clocks
+Subject: [PATCH 052/102] clk: dont disable unused clocks
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
  drivers/clk/clk.c |    2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
+diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
+index f13c3f4..5e9ddae 100644
 --- a/drivers/clk/clk.c
 +++ b/drivers/clk/clk.c
 @@ -233,7 +233,7 @@ unlock_out:
@@ -19,3 +21,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static int __init clk_ignore_unused_setup(char *__unused)
  {
  	clk_ignore_unused = true;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0052-mtd-nand-add-an-mtd_to_nand-helper.patch

@@ -1,30 +0,0 @@
-From 69a0df9dd942799651a7ec06b3cfe7fc43b2e32a Mon Sep 17 00:00:00 2001
-From: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Date: Mon, 16 Nov 2015 14:37:35 +0100
-Subject: [PATCH 52/91] mtd: nand: add an mtd_to_nand() helper
-
-Some drivers are retrieving the nand_chip pointer using the container_of
-macro on a struct wrapping both the nand_chip and the mtd_info struct while
-the standard way of retrieving this pointer is through mtd->priv.
-Provide an helper to do that.
-
-Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- include/linux/mtd/nand.h |    5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -719,6 +719,11 @@ struct nand_chip {
- 	void *priv;
- };
- 
-+static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
-+{
-+	return mtd->priv;
-+}
-+
- /*
-  * NAND Flash Manufacturer ID Codes
-  */

target/linux/mediatek/patches-4.4/0053-clk-mediatek-enable-critical-clocks.patch

@@ -1,16 +1,18 @@
-From 6610fdbea393a4a8ed956b2aaf7012bea3a5069e Mon Sep 17 00:00:00 2001
+From c8fd103d6c07af5db47f061b70759b7c69169656 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Thu, 31 Mar 2016 06:46:51 +0200
-Subject: [PATCH 61/91] clk: mediatek: enable critical clocks
+Subject: [PATCH 053/102] clk: mediatek: enable critical clocks
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
  drivers/clk/mediatek/clk-mt2701.c |   22 ++++++++++++++++++++--
  1 file changed, 20 insertions(+), 2 deletions(-)
 
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+index 812b347..1634288 100644
 --- a/drivers/clk/mediatek/clk-mt2701.c
 +++ b/drivers/clk/mediatek/clk-mt2701.c
-@@ -573,6 +573,20 @@ static const struct mtk_gate top_clks[]
+@@ -573,6 +573,20 @@ static const struct mtk_gate top_clks[] __initconst = {
  	GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div", 28),
  };
  
@@ -31,7 +33,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static void __init mtk_topckgen_init(struct device_node *node)
  {
  	struct clk_onecell_data *clk_data;
-@@ -585,7 +599,7 @@ static void __init mtk_topckgen_init(str
+@@ -585,7 +599,7 @@ static void __init mtk_topckgen_init(struct device_node *node)
  		return;
  	}
  
@@ -40,7 +42,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
  								clk_data);
-@@ -606,6 +620,8 @@ static void __init mtk_topckgen_init(str
+@@ -606,6 +620,8 @@ static void __init mtk_topckgen_init(struct device_node *node)
  	if (r)
  		pr_err("%s(): could not register clock provider: %d\n",
  			__func__, r);
@@ -49,7 +51,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  }
  CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt2701-topckgen", mtk_topckgen_init);
  
-@@ -1202,7 +1218,7 @@ static void __init mtk_apmixedsys_init(s
+@@ -1202,7 +1218,7 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
  	struct clk_onecell_data *clk_data;
  	int r;
  
@@ -58,7 +60,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	if (!clk_data)
  		return;
  
-@@ -1213,6 +1229,8 @@ static void __init mtk_apmixedsys_init(s
+@@ -1213,6 +1229,8 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
  	if (r)
  		pr_err("%s(): could not register clock provider: %d\n",
  			__func__, r);
@@ -67,3 +69,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  }
  CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt2701-apmixedsys",
  							mtk_apmixedsys_init);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0053-mtd-nand-add-nand_to_mtd-helper.patch

@@ -1,27 +0,0 @@
-From 833645b92150d74642829c24c0ca1fbbdeccfb5c Mon Sep 17 00:00:00 2001
-From: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Date: Tue, 1 Dec 2015 12:03:07 +0100
-Subject: [PATCH 53/91] mtd: nand: add nand_to_mtd() helper
-
-Add a new helper to retrieve the MTD device attached to a NAND chip.
-
-Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- include/linux/mtd/nand.h |    5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -724,6 +724,11 @@ static inline struct nand_chip *mtd_to_n
- 	return mtd->priv;
- }
- 
-+static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
-+{
-+	return &chip->mtd;
-+}
-+
- /*
-  * NAND Flash Manufacturer ID Codes
-  */

target/linux/mediatek/patches-4.4/0054-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch

@@ -1,8 +1,8 @@
-From 2ed6efcef399d15910ff60eef72b4cf8e5265c47 Mon Sep 17 00:00:00 2001
+From 1387d4f0ebf4b48c09f2ea0d27a02936c3fa0010 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Thu, 31 Mar 2016 02:26:37 +0200
-Subject: [PATCH 62/91] clk: mediatek: Export CPU mux clocks for CPU frequency
+Subject: [PATCH 054/102] clk: mediatek: Export CPU mux clocks for CPU
- control
+ frequency control
 
 This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
 for intermediate clock source switching.
@@ -20,6 +20,8 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  create mode 100644 drivers/clk/mediatek/clk-cpumux.c
  create mode 100644 drivers/clk/mediatek/clk-cpumux.h
 
+diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
+index 5b2b91b..76bfab6 100644
 --- a/drivers/clk/mediatek/Makefile
 +++ b/drivers/clk/mediatek/Makefile
 @@ -1,4 +1,4 @@
@@ -28,6 +30,9 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  obj-$(CONFIG_RESET_CONTROLLER) += reset.o
  obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
  obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
+diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c
+new file mode 100644
+index 0000000..91b5238
 --- /dev/null
 +++ b/drivers/clk/mediatek/clk-cpumux.c
 @@ -0,0 +1,127 @@
@@ -158,6 +163,9 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
 +
 +	return 0;
 +}
+diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h
+new file mode 100644
+index 0000000..52c769f
 --- /dev/null
 +++ b/drivers/clk/mediatek/clk-cpumux.h
 @@ -0,0 +1,22 @@
@@ -183,6 +191,8 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
 +			      struct clk_onecell_data *clk_data);
 +
 +#endif /* __DRV_CLK_CPUMUX_H */
+diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
+index 1634288..5c37fcb 100644
 --- a/drivers/clk/mediatek/clk-mt2701.c
 +++ b/drivers/clk/mediatek/clk-mt2701.c
 @@ -18,6 +18,7 @@
@@ -193,7 +203,7 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  
  #include <dt-bindings/clock/mt2701-clk.h>
  
-@@ -465,6 +466,10 @@ static const char * const cpu_parents[]
+@@ -465,6 +466,10 @@ static const char * const cpu_parents[] __initconst = {
  	"mmpll"
  };
  
@@ -204,7 +214,7 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  static const struct mtk_composite top_muxes[] __initconst = {
  	MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
  		0x0040, 0, 3, INVALID_MUX_GATE_BIT),
-@@ -677,6 +682,9 @@ static void __init mtk_infrasys_init(str
+@@ -677,6 +682,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
  	mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
  						clk_data);
  
@@ -214,6 +224,8 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  	if (r)
  		pr_err("%s(): could not register clock provider: %d\n",
+diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
+index 227e356..b82c0e2 100644
 --- a/drivers/clk/mediatek/clk-mt8173.c
 +++ b/drivers/clk/mediatek/clk-mt8173.c
 @@ -18,6 +18,7 @@
@@ -224,7 +236,7 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  
  #include <dt-bindings/clock/mt8173-clk.h>
  
-@@ -526,6 +527,25 @@ static const char * const i2s3_b_ck_pare
+@@ -526,6 +527,25 @@ static const char * const i2s3_b_ck_parents[] __initconst = {
  	"apll2_div5"
  };
  
@@ -250,7 +262,7 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  static const struct mtk_composite top_muxes[] __initconst = {
  	/* CLK_CFG_0 */
  	MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
-@@ -945,6 +965,9 @@ static void __init mtk_infrasys_init(str
+@@ -945,6 +965,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
  						clk_data);
  	mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
  
@@ -260,6 +272,8 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  	if (r)
  		pr_err("%s(): could not register clock provider: %d\n",
+diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
+index 50972d1..a6c63b8 100644
 --- a/include/dt-bindings/clock/mt2701-clk.h
 +++ b/include/dt-bindings/clock/mt2701-clk.h
 @@ -217,7 +217,8 @@
@@ -272,6 +286,8 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  
  /* PERICFG */
  
+diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
+index 7956ba1..c82ed7c 100644
 --- a/include/dt-bindings/clock/mt8173-clk.h
 +++ b/include/dt-bindings/clock/mt8173-clk.h
 @@ -192,7 +192,9 @@
@@ -285,3 +301,6 @@ Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  
  /* PERI_SYS */
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0054-mtd-nand-add-helpers-to-access-priv.patch

@@ -1,34 +0,0 @@
-From af8437ee10a6304da30ca479480102b464b39c82 Mon Sep 17 00:00:00 2001
-From: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Date: Thu, 10 Dec 2015 09:00:39 +0100
-Subject: [PATCH 54/91] mtd: nand: add helpers to access ->priv
-
-Add two helpers to access the field reserved for private controller data.
-This makes it clearer what this field is reserved for and ease future
-refactoring.
-
-Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- include/linux/mtd/nand.h |   10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -729,6 +729,16 @@ static inline struct mtd_info *nand_to_m
- 	return &chip->mtd;
- }
- 
-+static inline void *nand_get_controller_data(struct nand_chip *chip)
-+{
-+	return chip->priv;
-+}
-+
-+static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
-+{
-+	chip->priv = priv;
-+}
-+
- /*
-  * NAND Flash Manufacturer ID Codes
-  */

target/linux/mediatek/patches-4.4/0055-cpufreq-mediatek-add-driver.patch

@@ -1,7 +1,7 @@
-From 668d2c777a41440daa55435c2a217e61c23e4a30 Mon Sep 17 00:00:00 2001
+From 60f4e41b367bdb29530468c91c1e613b17a37755 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 30 Mar 2016 23:48:53 +0200
-Subject: [PATCH 63/91] cpufreq: mediatek: add driver
+Subject: [PATCH 055/102] cpufreq: mediatek: add driver
 
 Signed-off-by: John Crispin <john@phrozen.org>
 ---
@@ -11,6 +11,8 @@ Signed-off-by: John Crispin <john@phrozen.org>
  3 files changed, 399 insertions(+)
  create mode 100644 drivers/cpufreq/mt7623-cpufreq.c
 
+diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
+index b1f8a73..baf945e 100644
 --- a/drivers/cpufreq/Kconfig.arm
 +++ b/drivers/cpufreq/Kconfig.arm
 @@ -81,6 +81,15 @@ config ARM_KIRKWOOD_CPUFREQ
@@ -29,9 +31,11 @@ Signed-off-by: John Crispin <john@phrozen.org>
  config ARM_MT8173_CPUFREQ
  	bool "Mediatek MT8173 CPUFreq support"
  	depends on ARCH_MEDIATEK && REGULATOR
+diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
+index c0af1a1..e198752 100644
 --- a/drivers/cpufreq/Makefile
 +++ b/drivers/cpufreq/Makefile
-@@ -57,6 +57,7 @@ obj-$(CONFIG_ARM_HISI_ACPU_CPUFREQ)	+= h
+@@ -57,6 +57,7 @@ obj-$(CONFIG_ARM_HISI_ACPU_CPUFREQ)	+= hisi-acpu-cpufreq.o
  obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)		+= imx6q-cpufreq.o
  obj-$(CONFIG_ARM_INTEGRATOR)		+= integrator-cpufreq.o
  obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ)	+= kirkwood-cpufreq.o
@@ -39,6 +43,9 @@ Signed-off-by: John Crispin <john@phrozen.org>
  obj-$(CONFIG_ARM_MT8173_CPUFREQ)	+= mt8173-cpufreq.o
  obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)	+= omap-cpufreq.o
  obj-$(CONFIG_ARM_PXA2xx_CPUFREQ)	+= pxa2xx-cpufreq.o
+diff --git a/drivers/cpufreq/mt7623-cpufreq.c b/drivers/cpufreq/mt7623-cpufreq.c
+new file mode 100644
+index 0000000..8d154ce
 --- /dev/null
 +++ b/drivers/cpufreq/mt7623-cpufreq.c
 @@ -0,0 +1,389 @@
@@ -431,3 +438,6 @@ Signed-off-by: John Crispin <john@phrozen.org>
 +	return 0;
 +}
 +device_initcall(mt7623_cpufreq_driver_init);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0055-mtd-nand-embed-an-mtd_info-structure-into-nand_chip.patch

@@ -1,37 +0,0 @@
-From f18fcf4468ffdce17747f3d331f998a7e9264142 Mon Sep 17 00:00:00 2001
-From: Boris BREZILLON <boris.brezillon@free-electrons.com>
-Date: Tue, 1 Dec 2015 12:03:06 +0100
-Subject: [PATCH 55/91] mtd: nand: embed an mtd_info structure into nand_chip
-
-Currently all NAND controller drivers are providing both the mtd_info and
-nand_chip struct and then let the NAND subsystem to initialize a few
-things before registering the mtd instance to the MTD layer.
-Embed an mtd_info field into nand_chip to add some consistency to all NAND
-controller drivers.
-This change will also help factorizing boilerplate code copied in all NAND
-drivers.
-
-Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- include/linux/mtd/nand.h |    2 ++
- 1 file changed, 2 insertions(+)
-
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -540,6 +540,7 @@ struct nand_buffers {
- 
- /**
-  * struct nand_chip - NAND Private Flash Chip Data
-+ * @mtd:		MTD device registered to the MTD framework
-  * @IO_ADDR_R:		[BOARDSPECIFIC] address to read the 8 I/O lines of the
-  *			flash device
-  * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the
-@@ -640,6 +641,7 @@ struct nand_buffers {
-  */
- 
- struct nand_chip {
-+	struct mtd_info mtd;
- 	void __iomem *IO_ADDR_R;
- 	void __iomem *IO_ADDR_W;
- 

target/linux/mediatek/patches-4.4/0056-arm-mediatek-make-a7-timer-work-Signed-off-by-John-C.patch

@@ -1,14 +1,16 @@
-From 6eeadfb48dc5e73dae115fc0be9416e3d5fed84d Mon Sep 17 00:00:00 2001
+From f8cda0bc698706413b5dd6fde827f9a2601ac61b Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Thu, 31 Mar 2016 06:07:01 +0200
-Subject: [PATCH 64/91] arm: mediatek: make a7 timer work Signed-off-by: John
+Subject: [PATCH 056/102] arm: mediatek: make a7 timer work Signed-off-by:
- Crispin <blogic@openwrt.org>
+ John Crispin <blogic@openwrt.org>
 
 ---
  arch/arm/mach-mediatek/Kconfig    |    1 +
  arch/arm/mach-mediatek/mediatek.c |    1 +
  2 files changed, 2 insertions(+)
 
+diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
+index a7fef77..2c05bc31 100644
 --- a/arch/arm/mach-mediatek/Kconfig
 +++ b/arch/arm/mach-mediatek/Kconfig
 @@ -24,6 +24,7 @@ config MACH_MT6592
@@ -19,9 +21,11 @@ Subject: [PATCH 64/91] arm: mediatek: make a7 timer work Signed-off-by: John
  	select MIGHT_HAVE_PCI
  
  config MACH_MT8127
+diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
+index bcfca37..7553a8c 100644
 --- a/arch/arm/mach-mediatek/mediatek.c
 +++ b/arch/arm/mach-mediatek/mediatek.c
-@@ -29,6 +29,7 @@ static void __init mediatek_timer_init(v
+@@ -29,6 +29,7 @@ static void __init mediatek_timer_init(void)
  	void __iomem *gpt_base;
  
  	if (of_machine_is_compatible("mediatek,mt6589") ||
@@ -29,3 +33,6 @@ Subject: [PATCH 64/91] arm: mediatek: make a7 timer work Signed-off-by: John
  	    of_machine_is_compatible("mediatek,mt8135") ||
  	    of_machine_is_compatible("mediatek,mt8127")) {
  		/* turn on GPT6 which ungates arch timer clocks */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0056-mtd-add-get-set-of_node-flash_node-helpers.patch

@@ -1,78 +0,0 @@
-From 59d8570d4b61af8544fc295d5e83ab7c28294bb8 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Tue, 22 Mar 2016 03:52:07 +0100
-Subject: [PATCH 56/91] mtd: add get/set of_node/flash_node helpers
-
-We are going to begin using the mtd->dev.of_node field for MTD device
-nodes, so let's add helpers for it. Also, we'll be making some
-conversions on spi_nor (and nand_chip eventually) too, so get that ready
-with their own helpers.
-
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
-Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
----
- include/linux/mtd/mtd.h     |   11 +++++++++++
- include/linux/mtd/nand.h    |   11 +++++++++++
- include/linux/mtd/spi-nor.h |   11 +++++++++++
- 3 files changed, 33 insertions(+)
-
---- a/include/linux/mtd/mtd.h
-+++ b/include/linux/mtd/mtd.h
-@@ -258,6 +258,17 @@ struct mtd_info {
- 	int usecount;
- };
- 
-+static inline void mtd_set_of_node(struct mtd_info *mtd,
-+				   struct device_node *np)
-+{
-+	mtd->dev.of_node = np;
-+}
-+
-+static inline struct device_node *mtd_get_of_node(struct mtd_info *mtd)
-+{
-+	return mtd->dev.of_node;
-+}
-+
- int mtd_erase(struct mtd_info *mtd, struct erase_info *instr);
- int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
- 	      void **virt, resource_size_t *phys);
---- a/include/linux/mtd/nand.h
-+++ b/include/linux/mtd/nand.h
-@@ -741,6 +741,17 @@ static inline void nand_set_controller_d
- 	chip->priv = priv;
- }
- 
-+static inline void nand_set_flash_node(struct nand_chip *chip,
-+				       struct device_node *np)
-+{
-+	chip->flash_node = np;
-+}
-+
-+static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
-+{
-+	return chip->flash_node;
-+}
-+
- /*
-  * NAND Flash Manufacturer ID Codes
-  */
---- a/include/linux/mtd/spi-nor.h
-+++ b/include/linux/mtd/spi-nor.h
-@@ -184,6 +184,17 @@ struct spi_nor {
- 	void *priv;
- };
- 
-+static inline void spi_nor_set_flash_node(struct spi_nor *nor,
-+					  struct device_node *np)
-+{
-+	nor->flash_node = np;
-+}
-+
-+static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
-+{
-+	return nor->flash_node;
-+}
-+
- /**
-  * spi_nor_scan() - scan the SPI NOR
-  * @nor:	the spi_nor structure

target/linux/mediatek/patches-4.4/0057-mtd-mediatek-device-tree-docs-for-MTK-Smart-Device-G.patch

@@ -1,58 +0,0 @@
-From 0fe612b501f1d56d76b2858d2ae779c1e766d064 Mon Sep 17 00:00:00 2001
-From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
-Date: Wed, 2 Mar 2016 12:00:11 -0500
-Subject: [PATCH 57/91] mtd: mediatek: device tree docs for MTK Smart Device
- Gen1 NAND
-
-This patch adds documentation support for Smart Device Gen1 type of
-NAND controllers.
-
-Mediatek's SoC 2701 is one of the SoCs that implements this controller.
-
-Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
----
- .../devicetree/bindings/mtd/mtksdg1-nand.txt       |   38 ++++++++++++++++++++
- 1 file changed, 38 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/mtd/mtksdg1-nand.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/mtd/mtksdg1-nand.txt
-@@ -0,0 +1,38 @@
-+MTK Smart Device SoCs NAND controller DT binding
-+
-+Required properties:
-+- compatible:          Should be "mediatek,mt2701-nfc".
-+- reg:                 The first contains base physical address and size of
-+                       NAND controller's registers. The second contains base
-+                       physical address and size of NAND ECC engine.
-+- interrupts:          the NFC NFI interrupt, and the NFC ECC interrupt
-+- clocks:              NAND controller clocks.
-+- clock-names:         NAND controller clocks internal name.
-+- vmch-supply:         NAND power supply.
-+- #address-cells:      Partition address, should be set 1.
-+- #size-cells:         Partition size, should be set 1.
-+
-+Optional properties:
-+
-+nand-on-flash-bbt:  Use a flash based bad block table.
-+
-+Optional subnodes:
-+- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
-+
-+Example:
-+
-+	nand: nand@1100d000 {
-+		compatible = "mediatek,mt2701-nfc";
-+		reg = <0 0x1100d000 0 0x1000>, <0 0x1100e000 0 0x1000>;
-+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>,
-+			<GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
-+		clocks = <&pericfg CLK_PERI_NFI>, <&pericfg CLK_PERI_NFI_ECC>,
-+			<&pericfg CLK_PERI_NFI_PAD>;
-+		clock-names = "nfi_ck", "nfi_ecc_ck", "nfi_pad_ck";
-+		vmch-supply = <&mt6323_vmch_reg>;
-+		status = "disabled";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+
-+		...
-+	};

target/linux/mediatek/patches-4.4/0057-net-mediatek-checking-for-IS_ERR-instead-of-NULL.patch

@@ -1,7 +1,7 @@
-From 0b88e5873b97ab20566b51134123fda7050d4d08 Mon Sep 17 00:00:00 2001
+From b9f9b937dd12dc57bd54a6c89b18eb40d4508424 Mon Sep 17 00:00:00 2001
 From: Dan Carpenter <dan.carpenter@oracle.com>
 Date: Tue, 15 Mar 2016 10:18:49 +0300
-Subject: [PATCH 65/91] net: mediatek: checking for IS_ERR() instead of NULL
+Subject: [PATCH 057/102] net: mediatek: checking for IS_ERR() instead of NULL
 
 of_phy_connect() returns NULL on error, it never returns error pointers.
 
@@ -11,9 +11,11 @@ Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index ba3afa5..9759fe5 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -186,9 +186,9 @@ static int mtk_phy_connect_node(struct m
+@@ -186,9 +186,9 @@ static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
  
  	phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
  				mtk_phy_link_adjust, 0, phy_mode);
@@ -25,3 +27,6 @@ Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
  	}
  
  	dev_info(eth->dev,
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0058-net-mediatek-unlock-on-error-in-mtk_tx_map.patch

@@ -1,7 +1,7 @@
-From 489994e9cb0d9f762c31e2af9205188ae8f3b013 Mon Sep 17 00:00:00 2001
+From 6c12340c0c307d18b8d6120f64a8275b6d4d3e67 Mon Sep 17 00:00:00 2001
 From: Dan Carpenter <dan.carpenter@oracle.com>
 Date: Tue, 15 Mar 2016 10:19:04 +0300
-Subject: [PATCH 66/91] net: mediatek: unlock on error in mtk_tx_map()
+Subject: [PATCH 058/102] net: mediatek: unlock on error in mtk_tx_map()
 
 There was a missing unlock on the error path.
 
@@ -11,6 +11,8 @@ Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    2 ++
  1 file changed, 2 insertions(+)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 9759fe5..c2c2e206 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 @@ -661,6 +661,8 @@ err_dma:
@@ -22,3 +24,6 @@ Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
  	return -ENOMEM;
  }
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0059-mtd-nand-backport-fixes.patch

@@ -1,41 +0,0 @@
-From 96bddff914c0cee1b16d809220e84b470b433122 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 31 Mar 2016 02:28:08 +0200
-Subject: [PATCH 59/91] mtd: nand: backport fixes
-
----
- drivers/mtd/nand/mtksdg1_nand.c |    9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
---- a/drivers/mtd/nand/mtksdg1_nand.c
-+++ b/drivers/mtd/nand/mtksdg1_nand.c
-@@ -107,6 +107,9 @@ static struct nand_ecclayout nand_4k_128
- 	.oobfree = { {0, 32} },
- };
- 
-+static const char * const part_probes[] = {
-+	"cmdlinepart", "RedBoot", "ofpart", NULL };
-+
- /* NFI register access */
- static inline void mtk_nfi_writel(struct mtk_nfc_host *host, u32 val, u32 reg)
- {
-@@ -1298,6 +1301,7 @@ static int mtk_nfc_probe(struct platform
- 
- 	chip = &host->chip;
- 	mtd = nand_to_mtd(chip);
-+	mtd->priv = chip;
- 	host->dev = dev;
- 
- 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-@@ -1428,7 +1432,10 @@ static int mtk_nfc_probe(struct platform
- 	}
- 	host->switch_oob = false;
- 
--	ret = mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
-+	ret = mtd_device_parse_register(mtd, part_probes,
-+			&(struct mtd_part_parser_data) {
-+				.of_node = pdev->dev.of_node,
-+			}, NULL, 0);
- 	if (ret) {
- 		dev_err(dev, "mtd parse partition error\n");
- 		goto nand_free;

target/linux/mediatek/patches-4.4/0059-net-mediatek-use-dma_addr_t-correctly.patch

@@ -1,7 +1,7 @@
-From ac345476b98f3856bbf3938e114d4be799f8bd69 Mon Sep 17 00:00:00 2001
+From a572747434b6153e75812c5466c0557e5ed69284 Mon Sep 17 00:00:00 2001
 From: Arnd Bergmann <arnd@arndb.de>
 Date: Mon, 14 Mar 2016 15:07:10 +0100
-Subject: [PATCH 67/91] net: mediatek: use dma_addr_t correctly
+Subject: [PATCH 059/102] net: mediatek: use dma_addr_t correctly
 
 dma_alloc_coherent() expects a dma_addr_t pointer as its argument,
 not an 'unsigned int', and gcc correctly warns about broken
@@ -17,9 +17,11 @@ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index c2c2e206..a005bc4 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -453,7 +453,7 @@ static inline void mtk_rx_get_desc(struc
+@@ -453,7 +453,7 @@ static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
  /* the qdma core needs scratch memory to be setup */
  static int mtk_init_fq_dma(struct mtk_eth *eth)
  {
@@ -28,3 +30,6 @@ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
  	int cnt = MTK_DMA_SIZE;
  	dma_addr_t dma_addr;
  	int i;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0060-net-mediatek-remove-incorrect-dma_mask-assignment.patch

@@ -1,7 +1,7 @@
-From 8b6bb80616460eda2e70e358c5fb70c0f4d4d02f Mon Sep 17 00:00:00 2001
+From 8473af12d5aa34613070447d6fd8f785f31301de Mon Sep 17 00:00:00 2001
 From: Arnd Bergmann <arnd@arndb.de>
 Date: Mon, 14 Mar 2016 15:07:11 +0100
-Subject: [PATCH 68/91] net: mediatek: remove incorrect dma_mask assignment
+Subject: [PATCH 060/102] net: mediatek: remove incorrect dma_mask assignment
 
 Device drivers should not mess with the DMA mask directly,
 but instead call dma_set_mask() etc if needed.
@@ -17,9 +17,11 @@ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    3 ---
  1 file changed, 3 deletions(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index a005bc4..fcd4ed7 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1678,9 +1678,6 @@ static int mtk_probe(struct platform_dev
+@@ -1678,9 +1678,6 @@ static int mtk_probe(struct platform_device *pdev)
  	struct mtk_eth *eth;
  	int err;
  
@@ -29,3 +31,6 @@ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
  	device_reset(&pdev->dev);
  
  	match = of_match_device(of_mtk_match, &pdev->dev);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0061-net-mediatek-check-device_reset-return-code.patch

@@ -1,7 +1,7 @@
-From cd7ea7dae994beea798115f4c34c96f45cc028d1 Mon Sep 17 00:00:00 2001
+From 99159791184752ece724b741f9fa6334fdc67123 Mon Sep 17 00:00:00 2001
 From: Arnd Bergmann <arnd@arndb.de>
 Date: Mon, 14 Mar 2016 15:07:12 +0100
-Subject: [PATCH 69/91] net: mediatek: check device_reset return code
+Subject: [PATCH 061/102] net: mediatek: check device_reset return code
 
 The device_reset() function may fail, so we have to check
 its return value, e.g. to make deferred probing work correctly.
@@ -18,9 +18,11 @@ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index fcd4ed7..7f2126b 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1678,7 +1678,9 @@ static int mtk_probe(struct platform_dev
+@@ -1678,7 +1678,9 @@ static int mtk_probe(struct platform_device *pdev)
  	struct mtk_eth *eth;
  	int err;
  
@@ -31,3 +33,6 @@ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
  
  	match = of_match_device(of_mtk_match, &pdev->dev);
  	soc = (struct mtk_soc_data *)match->data;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0062-net-mediatek-watchdog_timeo-was-not-set.patch

@@ -1,7 +1,7 @@
-From 5fac03871435c52f7f9b7f34aefb2774089d32f9 Mon Sep 17 00:00:00 2001
+From 387257cbd6f3f92de71e2f578d3a9414d0dada27 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Wed, 30 Mar 2016 03:18:17 +0200
-Subject: [PATCH 70/91] net: mediatek: watchdog_timeo was not set
+Subject: [PATCH 062/102] net: mediatek: watchdog_timeo was not set
 
 The original commit failed to set watchdog_timeo. This patch sets
 watchdog_timeo to HZ.
@@ -11,9 +11,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    1 +
  1 file changed, 1 insertion(+)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 7f2126b..7e6d2e2 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1645,6 +1645,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -1645,6 +1645,7 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
  	mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
  
  	SET_NETDEV_DEV(eth->netdev[id], eth->dev);
@@ -21,3 +23,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
  	eth->netdev[id]->base_addr = (unsigned long)eth->base;
  	eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0063-net-mediatek-mtk_cal_txd_req-returns-bad-value.patch

@@ -1,7 +1,7 @@
-From ca0d5851de3763fe309d3083693f1a438c6e98c9 Mon Sep 17 00:00:00 2001
+From d8f3e96943334c91ecc0827ed0d3232068c389e6 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 22 Mar 2016 04:42:27 +0100
-Subject: [PATCH 71/91] net: mediatek: mtk_cal_txd_req() returns bad value
+Subject: [PATCH 063/102] net: mediatek: mtk_cal_txd_req() returns bad value
 
 The code used to also support the PDMA engine, which had 2 packet pointers
 per descriptor. Because of this we have to divide the result by 2 and round
@@ -12,9 +12,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 7e6d2e2..4d8d0a3 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -681,7 +681,7 @@ static inline int mtk_cal_txd_req(struct
+@@ -681,7 +681,7 @@ static inline int mtk_cal_txd_req(struct sk_buff *skb)
  		nfrags += skb_shinfo(skb)->nr_frags;
  	}
  
@@ -23,3 +25,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  }
  
  static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0064-net-mediatek-remove-superflous-reset-call.patch

@@ -1,7 +1,7 @@
-From 51dc0a2114c3d6e51bf2acde415fccdec031e480 Mon Sep 17 00:00:00 2001
+From 2597d2cedba62b2a3fdca9c044187705f98a0372 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Fri, 25 Mar 2016 04:24:27 +0100
-Subject: [PATCH 72/91] net: mediatek: remove superflous reset call
+Subject: [PATCH 064/102] net: mediatek: remove superflous reset call
 
 HW reset is triggered int he mtk_hw_init() function. There is no need to
 reset the core during probe.
@@ -11,9 +11,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    4 ----
  1 file changed, 4 deletions(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 4d8d0a3..293ea59 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1679,10 +1679,6 @@ static int mtk_probe(struct platform_dev
+@@ -1679,10 +1679,6 @@ static int mtk_probe(struct platform_device *pdev)
  	struct mtk_eth *eth;
  	int err;
  
@@ -24,3 +26,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	match = of_match_device(of_mtk_match, &pdev->dev);
  	soc = (struct mtk_soc_data *)match->data;
  
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0065-net-mediatek-fix-stop-and-wakeup-of-queue.patch

@@ -1,7 +1,7 @@
-From 868eb5a3d0217e1ecdc2f628c6dc4fcd18562a71 Mon Sep 17 00:00:00 2001
+From afc838dde560ab584d3fb0e4b011e4a6770dab3d Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 29 Mar 2016 16:41:07 +0200
-Subject: [PATCH 73/91] net: mediatek: fix stop and wakeup of queue
+Subject: [PATCH 065/102] net: mediatek: fix stop and wakeup of queue
 
 The driver supports 2 MACs. Both run on the same DMA ring. If we go
 above/below the TX rings thershold value, we always need to wake/stop
@@ -13,9 +13,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |   37 +++++++++++++++++++--------
  1 file changed, 27 insertions(+), 10 deletions(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 293ea59..04bdb9d 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -684,6 +684,28 @@ static inline int mtk_cal_txd_req(struct
+@@ -684,6 +684,28 @@ static inline int mtk_cal_txd_req(struct sk_buff *skb)
  	return nfrags;
  }
  
@@ -44,7 +46,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
  {
  	struct mtk_mac *mac = netdev_priv(dev);
-@@ -695,7 +717,7 @@ static int mtk_start_xmit(struct sk_buff
+@@ -695,7 +717,7 @@ static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
  
  	tx_num = mtk_cal_txd_req(skb);
  	if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
@@ -53,7 +55,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		netif_err(eth, tx_queued, dev,
  			  "Tx Ring full when queue awake!\n");
  		return NETDEV_TX_BUSY;
-@@ -720,10 +742,10 @@ static int mtk_start_xmit(struct sk_buff
+@@ -720,10 +742,10 @@ static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
  		goto drop;
  
  	if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) {
@@ -66,7 +68,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	}
  
  	return NETDEV_TX_OK;
-@@ -897,13 +919,8 @@ static int mtk_poll_tx(struct mtk_eth *e
+@@ -897,13 +919,8 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
  	if (!total)
  		return 0;
  
@@ -82,3 +84,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	return total;
  }
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0066-net-mediatek-fix-mtk_pending_work.patch

@@ -1,7 +1,7 @@
-From 300ca8c6b5dcee2593f22d5bf8f13bb4da8c19c5 Mon Sep 17 00:00:00 2001
+From e2cc73e6ddb0cc39b8f58654a449651a621916a9 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 29 Mar 2016 17:00:47 +0200
-Subject: [PATCH 74/91] net: mediatek: fix mtk_pending_work
+Subject: [PATCH 066/102] net: mediatek: fix mtk_pending_work
 
 The driver supports 2 MACs. Both run on the same DMA ring. If we hit a TX
 timeout we need to stop both netdevs before retarting them again. If we
@@ -13,9 +13,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |   30 +++++++++++++++++++--------
  1 file changed, 21 insertions(+), 9 deletions(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 04bdb9d..26eeb1a 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1430,19 +1430,31 @@ static int mtk_do_ioctl(struct net_devic
+@@ -1430,19 +1430,31 @@ static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  
  static void mtk_pending_work(struct work_struct *work)
  {
@@ -56,3 +58,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	}
  	rtnl_unlock();
  }
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0067-net-mediatek-fix-TX-locking.patch

@@ -1,7 +1,7 @@
-From 506c56fe0c3986c13fbca474ee91b061fbc850ca Mon Sep 17 00:00:00 2001
+From 6f152b2bdb295d86beb746494ef6fddf17986f8e Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 29 Mar 2016 17:20:01 +0200
-Subject: [PATCH 75/91] net: mediatek: fix TX locking
+Subject: [PATCH 067/102] net: mediatek: fix TX locking
 
 Inside the TX path there is a lock inside the tx_map function. This is
 however too late. The patch moves the lock to the start of the xmit
@@ -15,9 +15,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |   20 ++++++++++----------
  1 file changed, 10 insertions(+), 10 deletions(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 26eeb1a..67b18f9 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -536,7 +536,6 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -536,7 +536,6 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
  	struct mtk_eth *eth = mac->hw;
  	struct mtk_tx_dma *itxd, *txd;
  	struct mtk_tx_buf *tx_buf;
@@ -25,7 +27,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	dma_addr_t mapped_addr;
  	unsigned int nr_frags;
  	int i, n_desc = 1;
-@@ -568,11 +567,6 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -568,11 +567,6 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
  	if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
  		return -ENOMEM;
  
@@ -37,7 +39,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	WRITE_ONCE(itxd->txd1, mapped_addr);
  	tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
  	dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
-@@ -632,8 +626,6 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -632,8 +626,6 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
  	WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
  				(!nr_frags * TX_DMA_LS0)));
  
@@ -55,7 +57,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	return -ENOMEM;
  }
  
-@@ -712,14 +702,22 @@ static int mtk_start_xmit(struct sk_buff
+@@ -712,14 +702,22 @@ static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
  	struct mtk_eth *eth = mac->hw;
  	struct mtk_tx_ring *ring = &eth->tx_ring;
  	struct net_device_stats *stats = &dev->stats;
@@ -78,7 +80,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		return NETDEV_TX_BUSY;
  	}
  
-@@ -747,10 +745,12 @@ static int mtk_start_xmit(struct sk_buff
+@@ -747,10 +745,12 @@ static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
  			     ring->thresh))
  			mtk_wake_queue(eth);
  	}
@@ -91,3 +93,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	stats->tx_dropped++;
  	dev_kfree_skb(skb);
  	return NETDEV_TX_OK;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0068-net-mediatek-move-the-pending_work-struct-to-the-dev.patch

@@ -1,7 +1,7 @@
-From d42de6ec9325c29d0f59c5df74a5cbceb00ddd9d Mon Sep 17 00:00:00 2001
+From 29bc7a1e374425937b5dd2f316dbeef343d4c68a Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 29 Mar 2016 17:24:24 +0200
-Subject: [PATCH 76/91] net: mediatek: move the pending_work struct to the
+Subject: [PATCH 068/102] net: mediatek: move the pending_work struct to the
  device generic struct
 
 The worker always touches both netdevs. It is ethernet core and not MAC
@@ -13,9 +13,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/net/ethernet/mediatek/mtk_eth_soc.h |    4 ++--
  2 files changed, 6 insertions(+), 8 deletions(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 67b18f9..bbcd607 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1193,7 +1193,7 @@ static void mtk_tx_timeout(struct net_de
+@@ -1193,7 +1193,7 @@ static void mtk_tx_timeout(struct net_device *dev)
  	eth->netdev[mac->id]->stats.tx_errors++;
  	netif_err(eth, tx_err, dev,
  		  "transmit timed out\n");
@@ -24,7 +26,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  }
  
  static irqreturn_t mtk_handle_irq(int irq, void *_eth)
-@@ -1438,7 +1438,7 @@ static void mtk_pending_work(struct work
+@@ -1438,7 +1438,7 @@ static void mtk_pending_work(struct work_struct *work)
  
  	/* stop all devices to make sure that dma is properly shut down */
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
@@ -33,7 +35,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  			continue;
  		mtk_stop(eth->netdev[i]);
  		__set_bit(i, &restart);
-@@ -1464,15 +1464,13 @@ static int mtk_cleanup(struct mtk_eth *e
+@@ -1464,15 +1464,13 @@ static int mtk_cleanup(struct mtk_eth *eth)
  	int i;
  
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
@@ -50,7 +52,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	return 0;
  }
-@@ -1660,7 +1658,6 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -1660,7 +1658,6 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
  	mac->id = id;
  	mac->hw = eth;
  	mac->of_node = np;
@@ -58,7 +60,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	mac->hw_stats = devm_kzalloc(eth->dev,
  				     sizeof(*mac->hw_stats),
-@@ -1762,6 +1759,7 @@ static int mtk_probe(struct platform_dev
+@@ -1762,6 +1759,7 @@ static int mtk_probe(struct platform_device *pdev)
  
  	eth->dev = &pdev->dev;
  	eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
@@ -66,6 +68,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	err = mtk_hw_init(eth);
  	if (err)
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+index 48a5292..eed626d 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 @@ -363,6 +363,7 @@ struct mtk_rx_ring {
@@ -100,3 +104,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  };
  
  /* the struct describing the SoC. these are declared in the soc_xyz.c files */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0069-net-mediatek-do-not-set-the-QID-field-in-the-TX-DMA-.patch

@@ -1,8 +1,8 @@
-From 2675e2a40d78c55fc2d578ec71cc990170cacc42 Mon Sep 17 00:00:00 2001
+From 4742349c1595d38b3e3b463e66cf21af4217c869 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Thu, 7 Apr 2016 17:36:23 +0200
-Subject: [PATCH 77/91] net: mediatek: do not set the QID field in the TX DMA
+Subject: [PATCH 069/102] net: mediatek: do not set the QID field in the TX
- descriptors
+ DMA descriptors
 
 The QID field gets set to the mac id. This made the DMA linked list queue
 the traffic of each MAC on a different internal queue. However during long
@@ -18,9 +18,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    3 +--
  1 file changed, 1 insertion(+), 2 deletions(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index bbcd607..bab5d45 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -603,8 +603,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -603,8 +603,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
  			WRITE_ONCE(txd->txd1, mapped_addr);
  			WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
  					       TX_DMA_PLEN0(frag_map_size) |
@@ -30,3 +32,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  			WRITE_ONCE(txd->txd4, 0);
  
  			tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0070-net-mediatek-update-the-IRQ-part-of-the-binding-docu.patch

@@ -1,7 +1,7 @@
-From 289e6b23aa394126f50048f673ac266686bbf65e Mon Sep 17 00:00:00 2001
+From 297ef52cd21e28da671996d7b4f39f268d2d0ec1 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Tue, 29 Mar 2016 14:32:07 +0200
-Subject: [PATCH 78/91] net: mediatek: update the IRQ part of the binding
+Subject: [PATCH 070/102] net: mediatek: update the IRQ part of the binding
  document
 
 The current binding document only describes a single interrupt. Update the
@@ -16,9 +16,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  Documentation/devicetree/bindings/net/mediatek-net.txt |    7 +++++--
  1 file changed, 5 insertions(+), 2 deletions(-)
 
+diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
+index 5ca7929..32eaaca 100644
 --- a/Documentation/devicetree/bindings/net/mediatek-net.txt
 +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
-@@ -9,7 +9,8 @@ have dual GMAC each represented by a chi
+@@ -9,7 +9,8 @@ have dual GMAC each represented by a child node..
  Required properties:
  - compatible: Should be "mediatek,mt7623-eth"
  - reg: Address and length of the register set for the device
@@ -39,3 +41,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
  	resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
  	reset-names = "eth";
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0071-pwm-add-pwm-mediatek.patch

@@ -0,0 +1,351 @@
+From 6f5941c93bdf7649f392f1263b9068d360ceab4d Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Fri, 6 May 2016 02:55:48 +0200
+Subject: [PATCH 071/102] pwm: add pwm-mediatek
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/arm/boot/dts/mt7623-evb.dts |   17 +++
+ arch/arm/boot/dts/mt7623.dtsi    |   22 ++++
+ drivers/pwm/Kconfig              |    9 ++
+ drivers/pwm/Makefile             |    1 +
+ drivers/pwm/pwm-mediatek.c       |  230 ++++++++++++++++++++++++++++++++++++++
+ 5 files changed, 279 insertions(+)
+ create mode 100644 drivers/pwm/pwm-mediatek.c
+
+diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
+index 5ad1448..70bc6b1 100644
+--- a/arch/arm/boot/dts/mt7623-evb.dts
++++ b/arch/arm/boot/dts/mt7623-evb.dts
+@@ -341,6 +341,17 @@
+ 			output-low;
+ 		};
+ 	};
++
++	pwm_pins: pwm {
++		pins_pwm1 {
++			pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>;
++		};
++
++		pins_pwm2 {
++			pinmux = <MT7623_PIN_205_PWM2_FUNC_PWM2>;
++		};
++	};
++
+ };
+ 
+ &nandc {
+@@ -419,3 +430,9 @@
+ 	mediatek,reset-pin = <&pio 15 0>;
+ 	status = "okay";
+ };
++
++&pwm {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm_pins>;
++	status = "okay";
++};
+diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
+index cbbdf16..3f50e7e 100644
+--- a/arch/arm/boot/dts/mt7623.dtsi
++++ b/arch/arm/boot/dts/mt7623.dtsi
+@@ -324,6 +324,28 @@
+ 		status = "disabled";
+ 	};
+ 
++	pwm: pwm@11006000 {
++		compatible = "mediatek,mt7623-pwm";
++	
++		reg = <0 0x11006000 0 0x1000>;
++		
++		resets = <&pericfg MT2701_PERI_PWM_SW_RST>;
++		reset-names = "pwm";
++
++		#pwm-cells = <2>;
++		clocks = <&topckgen CLK_TOP_PWM_SEL>,
++			 <&pericfg CLK_PERI_PWM>,
++			 <&pericfg CLK_PERI_PWM1>,
++			 <&pericfg CLK_PERI_PWM2>,
++			 <&pericfg CLK_PERI_PWM3>,
++			 <&pericfg CLK_PERI_PWM4>,
++			 <&pericfg CLK_PERI_PWM5>;
++		clock-names = "top", "main", "pwm1", "pwm2",
++			      "pwm3", "pwm4", "pwm5";
++	
++		status = "disabled";
++	};
++
+ 	spi: spi@1100a000 {
+ 		compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
+ 		reg = <0 0x1100a000 0 0x1000>;
+diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
+index 2f4641a..5860b1f 100644
+--- a/drivers/pwm/Kconfig
++++ b/drivers/pwm/Kconfig
+@@ -260,6 +260,15 @@ config PWM_MTK_DISP
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called pwm-mtk-disp.
+ 
++config PWM_MEDIATEK
++	tristate "MediaTek PWM support"
++	depends on ARCH_MEDIATEK || COMPILE_TEST
++	help
++	  Generic PWM framework driver for Mediatek ARM SoC.
++
++	  To compile this driver as a module, choose M here: the module
++	  will be called pwm-mxs.
++
+ config PWM_MXS
+ 	tristate "Freescale MXS PWM support"
+ 	depends on ARCH_MXS && OF
+diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
+index 69b8275..a90d5de 100644
+--- a/drivers/pwm/Makefile
++++ b/drivers/pwm/Makefile
+@@ -22,6 +22,7 @@ obj-$(CONFIG_PWM_LPC32XX)	+= pwm-lpc32xx.o
+ obj-$(CONFIG_PWM_LPSS)		+= pwm-lpss.o
+ obj-$(CONFIG_PWM_LPSS_PCI)	+= pwm-lpss-pci.o
+ obj-$(CONFIG_PWM_LPSS_PLATFORM)	+= pwm-lpss-platform.o
++obj-$(CONFIG_PWM_MEDIATEK)	+= pwm-mediatek.o
+ obj-$(CONFIG_PWM_MTK_DISP)	+= pwm-mtk-disp.o
+ obj-$(CONFIG_PWM_MXS)		+= pwm-mxs.o
+ obj-$(CONFIG_PWM_PCA9685)	+= pwm-pca9685.o
+diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
+new file mode 100644
+index 0000000..9d8d16d
+--- /dev/null
++++ b/drivers/pwm/pwm-mediatek.c
+@@ -0,0 +1,230 @@
++/*
++ * Mediatek Pulse Width Modulator driver
++ *
++ * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pwm.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++
++#define NUM_PWM		5
++
++/* PWM registers and bits definitions */
++#define PWMCON			0x00
++#define PWMHDUR			0x04
++#define PWMLDUR			0x08
++#define PWMGDUR			0x0c
++#define PWMWAVENUM		0x28
++#define PWMDWIDTH		0x2c
++#define PWMTHRES		0x30
++
++/**
++ * struct mtk_pwm_chip - struct representing pwm chip
++ *
++ * @mmio_base: base address of pwm chip
++ * @chip: linux pwm chip representation
++ */
++struct mtk_pwm_chip {
++	void __iomem *mmio_base;
++	struct pwm_chip chip;
++	struct clk *clk_top;
++	struct clk *clk_main;
++	struct clk *clk_pwm[NUM_PWM];
++};
++
++static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
++{
++	return container_of(chip, struct mtk_pwm_chip, chip);
++}
++
++static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
++				  unsigned long offset)
++{
++	return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset);
++}
++
++static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
++				    unsigned int num, unsigned long offset,
++				    unsigned long val)
++{
++	iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset);
++}
++
++static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
++			    int duty_ns, int period_ns)
++{
++	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
++	u32 resolution = 100 / 4;
++	u32 clkdiv = 0;
++
++	resolution = 1000000000 / (clk_get_rate(pc->clk_pwm[pwm->hwpwm]));
++
++	while (period_ns / resolution  > 8191) {
++		clkdiv++;
++		resolution *= 2;
++	}
++
++	if (clkdiv > 7)
++		return -1;
++
++	mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
++	mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
++	mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
++	return 0;
++}
++
++static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
++	u32 val;
++	int ret;
++
++	ret = clk_prepare(pc->clk_pwm[pwm->hwpwm]);
++	if (ret < 0)
++		return ret;
++
++	val = ioread32(pc->mmio_base);
++	val |= BIT(pwm->hwpwm);
++	iowrite32(val, pc->mmio_base);
++
++	return 0;
++}
++
++static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++	struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
++	u32 val;
++
++	val = ioread32(pc->mmio_base);
++	val &= ~BIT(pwm->hwpwm);
++	iowrite32(val, pc->mmio_base);
++        clk_unprepare(pc->clk_pwm[pwm->hwpwm]);
++}
++
++static const struct pwm_ops mtk_pwm_ops = {
++	.config = mtk_pwm_config,
++	.enable = mtk_pwm_enable,
++	.disable = mtk_pwm_disable,
++	.owner = THIS_MODULE,
++};
++
++static int mtk_pwm_probe(struct platform_device *pdev)
++{
++	struct mtk_pwm_chip *pc;
++	struct resource *r;
++	int ret;
++
++	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
++	if (!pc)
++		return -ENOMEM;
++
++	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
++	if (IS_ERR(pc->mmio_base))
++		return PTR_ERR(pc->mmio_base);
++
++	pc->clk_main = devm_clk_get(&pdev->dev, "main");
++        if (IS_ERR(pc->clk_main))
++		return PTR_ERR(pc->clk_main);
++
++	pc->clk_top = devm_clk_get(&pdev->dev, "top");
++        if (IS_ERR(pc->clk_top))
++		return PTR_ERR(pc->clk_top);
++
++	pc->clk_pwm[0] = devm_clk_get(&pdev->dev, "pwm1");
++        if (IS_ERR(pc->clk_pwm[0]))
++		return PTR_ERR(pc->clk_pwm[0]);
++
++	pc->clk_pwm[1] = devm_clk_get(&pdev->dev, "pwm2");
++        if (IS_ERR(pc->clk_pwm[1]))
++		return PTR_ERR(pc->clk_pwm[1]);
++
++	pc->clk_pwm[2] = devm_clk_get(&pdev->dev, "pwm3");
++        if (IS_ERR(pc->clk_pwm[2]))
++		return PTR_ERR(pc->clk_pwm[2]);
++
++	pc->clk_pwm[3] = devm_clk_get(&pdev->dev, "pwm4");
++        if (IS_ERR(pc->clk_pwm[3]))
++		return PTR_ERR(pc->clk_pwm[3]);
++
++	pc->clk_pwm[4] = devm_clk_get(&pdev->dev, "pwm5");
++        if (IS_ERR(pc->clk_pwm[4]))
++		return PTR_ERR(pc->clk_pwm[4]);
++
++	ret = clk_prepare(pc->clk_top);
++        if (ret < 0)
++		return ret;
++
++	ret = clk_prepare(pc->clk_main);
++	if (ret < 0)
++		goto disable_clk_top;
++
++	platform_set_drvdata(pdev, pc);
++
++	pc->chip.dev = &pdev->dev;
++	pc->chip.ops = &mtk_pwm_ops;
++	pc->chip.base = -1;
++	pc->chip.npwm = NUM_PWM;
++
++	ret = pwmchip_add(&pc->chip);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
++		goto disable_clk_main;
++	}
++
++	return 0;
++
++disable_clk_main:
++	clk_unprepare(pc->clk_main);
++disable_clk_top:
++	clk_unprepare(pc->clk_top);
++
++	return ret;
++}
++
++static int mtk_pwm_remove(struct platform_device *pdev)
++{
++	struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
++	int i;
++
++	for (i = 0; i < NUM_PWM; i++)
++		pwm_disable(&pc->chip.pwms[i]);
++
++	return pwmchip_remove(&pc->chip);
++}
++
++static const struct of_device_id mtk_pwm_of_match[] = {
++	{ .compatible = "mediatek,mt7623-pwm" },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
++
++static struct platform_driver mtk_pwm_driver = {
++	.driver = {
++		.name = "mtk-pwm",
++		.owner = THIS_MODULE,
++		.of_match_table = mtk_pwm_of_match,
++	},
++	.probe = mtk_pwm_probe,
++	.remove = mtk_pwm_remove,
++};
++
++module_platform_driver(mtk_pwm_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
++MODULE_ALIAS("platform:mtk-pwm");
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0073-of-mtd-prepare-helper-reading-NAND-ECC-algo-from-DT.patch

@@ -0,0 +1,98 @@
+From 410a91f6efa1c4c3c4369d1dd2c31286749dff33 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Wed, 23 Mar 2016 11:19:01 +0100
+Subject: [PATCH 073/102] of: mtd: prepare helper reading NAND ECC algo from
+ DT
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+NAND subsystem is being slightly reworked to store ECC details in
+separated fields. In future we'll want to add support for more DT
+properties as specifying every possible setup with a single
+"nand-ecc-mode" is a pretty bad idea.
+To allow this let's add a helper that will support something like
+"nand-ecc-algo" in future. Right now we use it for keeping backward
+compatibility.
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
+---
+ drivers/of/of_mtd.c    |   36 ++++++++++++++++++++++++++++++++++++
+ include/linux/of_mtd.h |    6 ++++++
+ 2 files changed, 42 insertions(+)
+
+diff --git a/drivers/of/of_mtd.c b/drivers/of/of_mtd.c
+index b7361ed..15d056e 100644
+--- a/drivers/of/of_mtd.c
++++ b/drivers/of/of_mtd.c
+@@ -50,6 +50,42 @@ int of_get_nand_ecc_mode(struct device_node *np)
+ EXPORT_SYMBOL_GPL(of_get_nand_ecc_mode);
+ 
+ /**
++ * of_get_nand_ecc_algo - Get nand ecc algorithm for given device_node
++ * @np:	Pointer to the given device_node
++ *
++ * The function gets ecc algorithm and returns its enum value, or errno in error
++ * case.
++ */
++int of_get_nand_ecc_algo(struct device_node *np)
++{
++	const char *pm;
++	int err;
++
++	/*
++	 * TODO: Read ECC algo OF property and map it to enum nand_ecc_algo.
++	 * It's not implemented yet as currently NAND subsystem ignores
++	 * algorithm explicitly set this way. Once it's handled we should
++	 * document & support new property.
++	 */
++
++	/*
++	 * For backward compatibility we also read "nand-ecc-mode" checking
++	 * for some obsoleted values that were specifying ECC algorithm.
++	 */
++	err = of_property_read_string(np, "nand-ecc-mode", &pm);
++	if (err < 0)
++		return err;
++
++	if (!strcasecmp(pm, "soft"))
++		return NAND_ECC_HAMMING;
++	else if (!strcasecmp(pm, "soft_bch"))
++		return NAND_ECC_BCH;
++
++	return -ENODEV;
++}
++EXPORT_SYMBOL_GPL(of_get_nand_ecc_algo);
++
++/**
+  * of_get_nand_ecc_step_size - Get ECC step size associated to
+  * the required ECC strength (see below).
+  * @np:	Pointer to the given device_node
+diff --git a/include/linux/of_mtd.h b/include/linux/of_mtd.h
+index e266caa..0f6aca5 100644
+--- a/include/linux/of_mtd.h
++++ b/include/linux/of_mtd.h
+@@ -13,6 +13,7 @@
+ 
+ #include <linux/of.h>
+ int of_get_nand_ecc_mode(struct device_node *np);
++int of_get_nand_ecc_algo(struct device_node *np);
+ int of_get_nand_ecc_step_size(struct device_node *np);
+ int of_get_nand_ecc_strength(struct device_node *np);
+ int of_get_nand_bus_width(struct device_node *np);
+@@ -25,6 +26,11 @@ static inline int of_get_nand_ecc_mode(struct device_node *np)
+ 	return -ENOSYS;
+ }
+ 
++static inline int of_get_nand_ecc_algo(struct device_node *np)
++{
++	return -ENOSYS;
++}
++
+ static inline int of_get_nand_ecc_step_size(struct device_node *np)
+ {
+ 	return -ENOSYS;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0074-mtd-mediatek-device-tree-docs-for-MTK-Smart-Device-G.patch

@@ -0,0 +1,185 @@
+From 5e1c00983efeca4522ac2e8574e3e3997d26a203 Mon Sep 17 00:00:00 2001
+From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+Date: Fri, 29 Apr 2016 12:17:21 -0400
+Subject: [PATCH 074/102] mtd: mediatek: device tree docs for MTK Smart Device
+ Gen1 NAND
+
+This patch adds documentation support for Smart Device Gen1 type of
+NAND controllers.
+
+Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+---
+ Documentation/devicetree/bindings/mtd/mtk-nand.txt |  161 ++++++++++++++++++++
+ 1 file changed, 161 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/mtd/mtk-nand.txt
+
+diff --git a/Documentation/devicetree/bindings/mtd/mtk-nand.txt b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
+new file mode 100644
+index 0000000..175767d
+--- /dev/null
++++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
+@@ -0,0 +1,161 @@
++MTK SoCs NAND FLASH controller (NFC) DT binding
++
++This file documents the device tree bindings for MTK SoCs NAND controllers.
++The functional split of the controller requires two drivers to operate:
++the nand controller interface driver and the ECC engine driver.
++
++The hardware description for both devices must be captured as device
++tree nodes.
++
++1) NFC NAND Controller Interface (NFI):
++=======================================
++
++The first part of NFC is NAND Controller Interface (NFI) HW.
++Required NFI properties:
++- compatible:			Should be "mediatek,mtxxxx-nfc".
++- reg:				Base physical address and size of NFI.
++- interrupts:			Interrupts of NFI.
++- clocks:			NFI required clocks.
++- clock-names:			NFI clocks internal name.
++- status:			Disabled default. Then set "okay" by platform.
++- ecc-engine:			Required ECC Engine node.
++- #address-cells:		NAND chip index, should be 1.
++- #size-cells:			Should be 0.
++
++Example:
++
++	nandc: nfi@1100d000 {
++		compatible = "mediatek,mt2701-nfc";
++		reg = <0 0x1100d000 0 0x1000>;
++		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&pericfg CLK_PERI_NFI>,
++			 <&pericfg CLK_PERI_NFI_PAD>;
++		clock-names = "nfi_clk", "pad_clk";
++		status = "disabled";
++		ecc-engine = <&bch>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++        };
++
++Platform related properties, should be set in {platform_name}.dts:
++- children nodes:	NAND chips.
++
++Children nodes properties:
++- reg:			Chip Select Signal, default 0.
++			Set as reg = <0>, <1> when need 2 CS.
++Optional:
++- nand-on-flash-bbt:	Store BBT on NAND Flash.
++- nand-ecc-mode:	the NAND ecc mode (check driver for supported modes)
++- nand-ecc-step-size:	Number of data bytes covered by a single ECC step.
++			The controller only supports 512 and 1024.
++			For large page NANDs ther recommended value is 1024.
++- nand-ecc-strength:	Number of bits to correct per ECC step.
++			The valid values that the controller supports are: 4, 6,
++			8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
++			48, 52, 56, 60.
++			The strength should be calculated as follows:
++			E = (S - F) * 8 / 14
++			S = O / (P / Q)
++				E :nand-ecc-strength;
++				S :spare size per sector;
++				F : FDM size, should be in the range [1,8].
++				    It is used to store free oob data.
++				O : oob size;
++				P : page size;
++				Q :nand-ecc-step-size
++			If the result does not match any one of the listed
++			choices above, please select the smaller valid value from
++			the list.
++			(otherwise the driver will do the clamping at runtime).
++- vmch-supply:		NAND power supply.
++- pinctrl-names:	Default NAND pin GPIO setting name.
++- pinctrl-0:		GPIO setting node.
++
++Example:
++	&pio {
++		nand_pins_default: nanddefault {
++			pins_dat {
++				pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>,
++					 <MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>,
++					 <MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>,
++					 <MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>,
++					 <MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>,
++					 <MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>,
++					 <MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>,
++					 <MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>,
++					 <MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>;
++				input-enable;
++				drive-strength = <MTK_DRIVE_8mA>;
++				bias-pull-up;
++			};
++
++			pins_we {
++				pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>;
++				drive-strength = <MTK_DRIVE_8mA>;
++				bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
++			};
++
++			pins_ale {
++				pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>;
++				drive-strength = <MTK_DRIVE_8mA>;
++				bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
++			};
++		};
++	};
++
++	&nandc {
++		status = "okay";
++		pinctrl-names = "default";
++		pinctrl-0 = <&nand_pins_default>;
++		nand@0 {
++			reg = <0>;
++			nand-on-flash-bbt;
++			nand-ecc-mode = "hw";
++			nand-ecc-strength = <24>;
++			nand-ecc-step-size = <1024>;
++		};
++	};
++
++NAND chip optional subnodes:
++- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
++
++Example:
++	nand@0 {
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			preloader@0 {
++				label = "pl";
++				read-only;
++				reg = <0x00000000 0x00400000>;
++			};
++			android@0x00400000 {
++				label = "android";
++				reg = <0x00400000 0x12c00000>;
++			};
++		};
++	};
++
++2) ECC Engine:
++==============
++
++Required BCH properties:
++- compatible:	Should be "mediatek,mtxxxx-ecc".
++- reg:		Base physical address and size of ECC.
++- interrupts:	Interrupts of ECC.
++- clocks:	ECC required clocks.
++- clock-names:	ECC clocks internal name.
++- status:	Disabled default. Then set "okay" by platform.
++
++Example:
++
++	bch: ecc@1100e000 {
++		compatible = "mediatek,mt2701-ecc";
++		reg = <0 0x1100e000 0 0x1000>;
++		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
++		clocks = <&pericfg CLK_PERI_NFI_ECC>;
++		clock-names = "nfiecc_clk";
++		status = "disabled";
++	};
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0076-mtd-nand-add-power-domains-to-the-mediatek-driver.patch

@@ -0,0 +1,72 @@
+From 5dc0d474396e04e6c140d71f0e113eb1c03501c5 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Tue, 17 May 2016 05:44:10 +0200
+Subject: [PATCH 076/102] mtd: nand: add power domains to the mediatek driver
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/mtd/nand/mtk_nand.c |   13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mtd/nand/mtk_nand.c b/drivers/mtd/nand/mtk_nand.c
+index 907b90c..bde1a1d 100644
+--- a/drivers/mtd/nand/mtk_nand.c
++++ b/drivers/mtd/nand/mtk_nand.c
+@@ -16,6 +16,7 @@
+ 
+ #include <linux/platform_device.h>
+ #include <linux/dma-mapping.h>
++#include <linux/pm_runtime.h>
+ #include <linux/interrupt.h>
+ #include <linux/delay.h>
+ #include <linux/clk.h>
+@@ -102,6 +103,7 @@
+ #define NFI_MASTER_STA		(0x224)
+ #define		MASTER_STA_MASK		(0x0FFF)
+ #define NFI_EMPTY_THRESH	(0x23C)
++#define NFI_ACCCON1		(0x244)
+ 
+ #define MTK_NAME		"mtk-nand"
+ #define KB(x)			((x) * 1024UL)
+@@ -539,6 +541,8 @@ static void mtk_nfc_bad_mark_swap(struct mtd_info *mtd, uint8_t *buf, int raw)
+ 	struct mtk_nfc_nand_chip *nand = to_mtk_nand(chip);
+ 	u32 bad_pos = nand->bad_mark.pos;
+ 
++	return;
++
+ 	if (raw)
+ 		bad_pos += nand->bad_mark.sec * mtk_data_len(chip);
+ 	else
+@@ -946,7 +950,8 @@ static int mtk_nfc_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
+ 
+ static inline void mtk_nfc_hw_init(struct mtk_nfc *nfc)
+ {
+-	nfi_writel(nfc, 0x10804211, NFI_ACCCON);
++	nfi_writel(nfc, 0x30c77fff, NFI_ACCCON);
++	nfi_writel(nfc, 0xC03222, NFI_ACCCON1);
+ 	nfi_writew(nfc, 0xf1, NFI_CNRNB);
+ 	nfi_writew(nfc, PAGEFMT_8K_16K, NFI_PAGEFMT);
+ 
+@@ -1328,6 +1333,9 @@ static int mtk_nfc_probe(struct platform_device *pdev)
+ 		goto clk_disable;
+ 	}
+ 
++	pm_runtime_enable(dev);
++	pm_runtime_get_sync(dev);
++
+ 	platform_set_drvdata(pdev, nfc);
+ 
+ 	ret = mtk_nfc_nand_chips_init(dev, nfc);
+@@ -1362,6 +1370,9 @@ static int mtk_nfc_remove(struct platform_device *pdev)
+ 	mtk_ecc_release(nfc->ecc);
+ 	mtk_nfc_disable_clk(&nfc->clk);
+ 
++	pm_runtime_put_sync(&pdev->dev);
++	pm_runtime_disable(&pdev->dev);
++
+ 	return 0;
+ }
+ 
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0077-net-next-mediatek-use-mdiobus_free-in-favour-of-kfre.patch

@@ -0,0 +1,41 @@
+From b1c85818c3fb00022dc125bb62d657d3fd3cf49c Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Sat, 7 May 2016 06:31:08 +0200
+Subject: [PATCH 077/102] net-next: mediatek: use mdiobus_free() in favour of
+ kfree()
+
+The driver currently uses kfree() to clear the mii_bus. This is not the
+correct way to clear the memory and mdiobus_free() should be used instead.
+This patch fixes the two instances where this happens in the driver.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index bab5d45..0c8d369 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -280,7 +280,7 @@ static int mtk_mdio_init(struct mtk_eth *eth)
+ 	return 0;
+ 
+ err_free_bus:
+-	kfree(eth->mii_bus);
++	mdiobus_free(eth->mii_bus);
+ 
+ err_put_node:
+ 	of_node_put(mii_np);
+@@ -295,7 +295,7 @@ static void mtk_mdio_cleanup(struct mtk_eth *eth)
+ 
+ 	mdiobus_unregister(eth->mii_bus);
+ 	of_node_put(eth->mii_bus->dev.of_node);
+-	kfree(eth->mii_bus);
++	mdiobus_free(eth->mii_bus);
+ }
+ 
+ static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0078-net-next-mediatek-fix-gigabit-and-flow-control-adver.patch

@@ -0,0 +1,76 @@
+From 09313f26999e2685e0b9434374e7308e1f447e55 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Fri, 22 Apr 2016 11:05:23 +0200
+Subject: [PATCH 078/102] net-next: mediatek: fix gigabit and flow control
+ advertisement
+
+The current code will not setup the PHYs advertisement features correctly.
+Fix this and properly advertise Gigabit features and properly handle
+asymmetric pause frames.
+
+Signed-off-by: Sean Wang <keyhaede@gmail.com>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |   30 +++++++++++++++++++++++----
+ 1 file changed, 26 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 0c8d369..3436c7b 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -133,6 +133,8 @@ static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
+ static void mtk_phy_link_adjust(struct net_device *dev)
+ {
+ 	struct mtk_mac *mac = netdev_priv(dev);
++	u16 lcl_adv = 0, rmt_adv = 0;
++	u8 flowctrl;
+ 	u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
+ 		  MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
+ 		  MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
+@@ -150,11 +152,30 @@ static void mtk_phy_link_adjust(struct net_device *dev)
+ 	if (mac->phy_dev->link)
+ 		mcr |= MAC_MCR_FORCE_LINK;
+ 
+-	if (mac->phy_dev->duplex)
++	if (mac->phy_dev->duplex) {
+ 		mcr |= MAC_MCR_FORCE_DPX;
+ 
+-	if (mac->phy_dev->pause)
+-		mcr |= MAC_MCR_FORCE_RX_FC | MAC_MCR_FORCE_TX_FC;
++		if (mac->phy_dev->pause)
++			rmt_adv = LPA_PAUSE_CAP;
++		if (mac->phy_dev->asym_pause)
++			rmt_adv |= LPA_PAUSE_ASYM;
++
++		if (mac->phy_dev->advertising & ADVERTISED_Pause)
++			lcl_adv |= ADVERTISE_PAUSE_CAP;
++		if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
++			lcl_adv |= ADVERTISE_PAUSE_ASYM;
++
++		flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
++
++		if (flowctrl & FLOW_CTRL_TX)
++			mcr |= MAC_MCR_FORCE_TX_FC;
++		if (flowctrl & FLOW_CTRL_RX)
++			mcr |= MAC_MCR_FORCE_RX_FC;
++
++		netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
++			  flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
++			  flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
++	}
+ 
+ 	mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
+ 
+@@ -236,7 +257,8 @@ static int mtk_phy_connect(struct mtk_mac *mac)
+ 	mac->phy_dev->autoneg = AUTONEG_ENABLE;
+ 	mac->phy_dev->speed = 0;
+ 	mac->phy_dev->duplex = 0;
+-	mac->phy_dev->supported &= PHY_BASIC_FEATURES;
++	mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
++				   SUPPORTED_Asym_Pause;
+ 	mac->phy_dev->advertising = mac->phy_dev->supported |
+ 				    ADVERTISED_Autoneg;
+ 	phy_start_aneg(mac->phy_dev);
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0079-net-next-mediatek-add-fixed-phy-support.patch

@@ -0,0 +1,43 @@
+From 09f0b50ae838bd6e2bbf0aa22de9f352122297de Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Fri, 22 Apr 2016 11:06:03 +0200
+Subject: [PATCH 079/102] net-next: mediatek: add fixed-phy support
+
+The MT7623 SoC has a builtin gigabit switch. If we want to use it, GMAC1
+needs to be configured using a fixed link speed and flow control settings.
+The easiest way to do this is to used the fixed-phy driver, allowing us to
+reuse the existing mdio polling code to setup the MAC.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |    6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 3436c7b..ab61789 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -229,6 +229,9 @@ static int mtk_phy_connect(struct mtk_mac *mac)
+ 	u32 val, ge_mode;
+ 
+ 	np = of_parse_phandle(mac->of_node, "phy-handle", 0);
++	if (!np && of_phy_is_fixed_link(mac->of_node))
++		if (!of_phy_register_fixed_link(mac->of_node))
++			np = of_node_get(mac->of_node);
+ 	if (!np)
+ 		return -ENODEV;
+ 
+@@ -257,6 +260,9 @@ static int mtk_phy_connect(struct mtk_mac *mac)
+ 	mac->phy_dev->autoneg = AUTONEG_ENABLE;
+ 	mac->phy_dev->speed = 0;
+ 	mac->phy_dev->duplex = 0;
++	if (of_phy_is_fixed_link(mac->of_node))
++		mac->phy_dev->supported |= SUPPORTED_Pause |
++					   SUPPORTED_Asym_Pause;
+ 	mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
+ 				   SUPPORTED_Asym_Pause;
+ 	mac->phy_dev->advertising = mac->phy_dev->supported |
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0080-net-next-mediatek-fix-gigabit-and-flow-control-adver.patch

@@ -1,54 +0,0 @@
-From 6918f290a9019425043dbedf7b39bc82a69e23a6 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 22 Apr 2016 11:05:23 +0200
-Subject: [PATCH 80/91] net-next: mediatek: fix gigabit and flow control
- advertisement
-
-The current code will not setup the PHYs advertisement features correctly.
-Fix this and properly advertise Gigabit features and properly handle
-asymmetric pause frames.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c |   16 ++++++++++++++--
- 1 file changed, 14 insertions(+), 2 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -133,6 +133,8 @@ static int mtk_mdio_read(struct mii_bus
- static void mtk_phy_link_adjust(struct net_device *dev)
- {
- 	struct mtk_mac *mac = netdev_priv(dev);
-+	u16 lcl_adv, rmt_adv = 0;
-+	u8 flowctrl;
- 	u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
- 		  MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
- 		  MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
-@@ -154,7 +156,16 @@ static void mtk_phy_link_adjust(struct n
- 		mcr |= MAC_MCR_FORCE_DPX;
- 
- 	if (mac->phy_dev->pause)
--		mcr |= MAC_MCR_FORCE_RX_FC | MAC_MCR_FORCE_TX_FC;
-+		rmt_adv = LPA_PAUSE_CAP;
-+	if (mac->phy_dev->asym_pause)
-+		rmt_adv |= LPA_PAUSE_ASYM;
-+
-+	lcl_adv = mii_advertise_flowctrl(FLOW_CTRL_RX | FLOW_CTRL_TX);
-+	flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
-+	if (flowctrl & FLOW_CTRL_TX)
-+		mcr |= MAC_MCR_FORCE_TX_FC;
-+	if (flowctrl & FLOW_CTRL_RX)
-+		mcr |= MAC_MCR_FORCE_RX_FC;
- 
- 	mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
- 
-@@ -236,7 +247,8 @@ static int mtk_phy_connect(struct mtk_ma
- 	mac->phy_dev->autoneg = AUTONEG_ENABLE;
- 	mac->phy_dev->speed = 0;
- 	mac->phy_dev->duplex = 0;
--	mac->phy_dev->supported &= PHY_BASIC_FEATURES;
-+	mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
-+			           ~SUPPORTED_Asym_Pause;
- 	mac->phy_dev->advertising = mac->phy_dev->supported |
- 				    ADVERTISED_Autoneg;
- 	phy_start_aneg(mac->phy_dev);

target/linux/mediatek/patches-4.4/0080-net-next-mediatek-properly-handle-RGMII-modes.patch

@@ -0,0 +1,36 @@
+From 25eaa5d6483a5899e6bf48b47f762f05c186b4b6 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Fri, 22 Apr 2016 11:08:43 +0200
+Subject: [PATCH 080/102] net-next: mediatek: properly handle RGMII modes
+
+If an external Gigabit PHY is connected to either of the MACs we need to
+be able to tell the PHY to use a delay. Not doing so will result in heavy
+packet loss and/or data corruption when using PHYs such as the IC+ IP1001.
+We tell the PHY which MII delay mode to use via the devictree.
+
+The ethernet driver needs to be adapted to handle all 3 rgmii-*id modes
+in the same way as normal rgmii when setting up the MAC.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |    3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index ab61789..76ecb1b 100644
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -236,6 +236,9 @@ static int mtk_phy_connect(struct mtk_mac *mac)
+ 		return -ENODEV;
+ 
+ 	switch (of_get_phy_mode(np)) {
++	case PHY_INTERFACE_MODE_RGMII_TXID:
++	case PHY_INTERFACE_MODE_RGMII_RXID:
++	case PHY_INTERFACE_MODE_RGMII_ID:
+ 	case PHY_INTERFACE_MODE_RGMII:
+ 		ge_mode = 0;
+ 		break;
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0081-net-next-mediatek-add-fixed-phy-support.patch

@@ -1,27 +0,0 @@
-From b5ecc24a027dea24f3ff798f87f65dd42015b342 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 22 Apr 2016 11:06:03 +0200
-Subject: [PATCH 81/91] net-next: mediatek: add fixed-phy support
-
-The MT7623 SoC has a builtin gigabit switch. If we want to use it, GMAC1
-needs to be configured using a fixed link speed and flow control settings.
-The easiest way to do this is to used the fixed-phy driver, allowing us to
-reuse the existing mdio polling code to setup the MAC.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c |    3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -219,6 +219,9 @@ static int mtk_phy_connect(struct mtk_ma
- 	u32 val, ge_mode;
- 
- 	np = of_parse_phandle(mac->of_node, "phy-handle", 0);
-+	if (!np && of_phy_is_fixed_link(mac->of_node))
-+		if (!of_phy_register_fixed_link(mac->of_node))
-+			np = of_node_get(mac->of_node);
- 	if (!np)
- 		return -ENODEV;
- 

target/linux/mediatek/patches-4.4/0081-net-next-mediatek-fix-DQL-support.patch

@@ -1,16 +1,26 @@
-From f26f228f312fafc090d21036b682bd1062bb731f Mon Sep 17 00:00:00 2001
+From 81cdbda2a08375b9d5915567d2210bf2433e7332 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
+From: John Crispin <john@phrozen.org>
 Date: Sat, 23 Apr 2016 11:57:21 +0200
-Subject: [PATCH 79/91] net-next: mediatek: fix BQL support
+Subject: [PATCH 081/102] net-next: mediatek: fix DQL support
 
-Signed-off-by: John Crispin <blogic@openwrt.org>
+The MTK ethernet core has 2 MACs both sitting on the same DMA ring. The
+current code will assign the TX traffic of each MAC to its own DQL. This
+results in the amount of data, that DQL says is in the queue incorrect. As
+the data from multiple devices is infact enqueued. This makes any decision
+based on these value non deterministic. Fix this by tracking all TX
+traffic, regardless of the MAC it belongs to in the DQL of all devices
+using the DMA.
+
+Signed-off-by: John Crispin <john@phrozen.org>
 ---
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |   33 ++++++++++++++++-----------
  1 file changed, 20 insertions(+), 13 deletions(-)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index 76ecb1b..feedd5a 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -625,7 +625,16 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -656,7 +656,16 @@ static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
  	WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
  				(!nr_frags * TX_DMA_LS0)));
  
@@ -28,7 +38,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	skb_tx_timestamp(skb);
  
  	ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
-@@ -853,21 +862,18 @@ static int mtk_poll_tx(struct mtk_eth *e
+@@ -884,21 +893,18 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
  	struct mtk_tx_dma *desc;
  	struct sk_buff *skb;
  	struct mtk_tx_buf *tx_buf;
@@ -53,7 +63,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		u32 next_cpu = desc->txd2;
  		int mac;
  
-@@ -887,9 +893,8 @@ static int mtk_poll_tx(struct mtk_eth *e
+@@ -918,9 +924,8 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
  		}
  
  		if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
@@ -65,7 +75,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  		}
  		mtk_tx_unmap(eth->dev, tx_buf);
  
-@@ -902,11 +907,13 @@ static int mtk_poll_tx(struct mtk_eth *e
+@@ -933,11 +938,13 @@ static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
  
  	mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
  
@@ -82,3 +92,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	}
  
  	/* read hw index again make sure no new tx packet */
+-- 
+1.7.10.4
+

target/linux/mediatek/patches-4.4/0082-net-next-mediatek-add-RX-delay-support.patch

@@ -1,24 +0,0 @@
-From bbd92ed51c48a4586f149767841a5495cbc5a979 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 22 Apr 2016 11:08:43 +0200
-Subject: [PATCH 82/91] net-next: mediatek: add RX delay support
-
-If an external Gigabit PHY is connected to either of the MACs we need to
-tell the to use a RX delay. Not doing so will result in heavy packet loss
-and/or data corruption of RX traffic.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c |    1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -226,6 +226,7 @@ static int mtk_phy_connect(struct mtk_ma
- 		return -ENODEV;
- 
- 	switch (of_get_phy_mode(np)) {
-+	case PHY_INTERFACE_MODE_RGMII_RXID:
- 	case PHY_INTERFACE_MODE_RGMII:
- 		ge_mode = 0;
- 		break;

target/linux/mediatek/patches-4.4/0082-net-next-mediatek-add-missing-return-code-check.patch

@@ -1,19 +1,22 @@
-From d20b45f50d6b3352aa7be76eb7a28cffcfe379da Mon Sep 17 00:00:00 2001
+From 51ca1e9f141499fd7c95bff5401215b706656754 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
+From: John Crispin <john@phrozen.org>
 Date: Sat, 23 Apr 2016 09:06:05 +0200
-Subject: [PATCH 83/91] net-next: mediatek: add missing return code check
+Subject: [PATCH 082/102] net-next: mediatek: add missing return code check
 
 The code fails to check if the scratch memory was properly allocated. Add
 this check and return with an error if the allocation failed.
 
-Signed-off-by: John Crispin <blogic@openwrt.org>
+Signed-off-by: Sean Wang <keyhaede@gmail.com>
+Signed-off-by: John Crispin <john@phrozen.org>
 ---
  drivers/net/ethernet/mediatek/mtk_eth_soc.c |    3 +++
  1 file changed, 3 insertions(+)
 
+diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+index feedd5a..fefbf16 100644
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -483,6 +483,9 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -498,6 +498,9 @@ static int mtk_init_fq_dma(struct mtk_eth *eth)
  
  	eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
  				    GFP_KERNEL);
@@ -23,3 +26,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  	dma_addr = dma_map_single(eth->dev,
  				  eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
  				  DMA_FROM_DEVICE);
+-- 
+1.7.10.4
+