packages: bump uboot-sunxi to 2016.01-rc3, along with H3 PSCI/SMP patches
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> SVN-Revision: 48154
This commit is contained in:
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f6340da7df
commit
f15fc140f1
6 changed files with 211 additions and 2 deletions
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@ -9,13 +9,13 @@ include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/kernel.mk
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PKG_NAME:=u-boot
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PKG_VERSION:=2016.01-rc2
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PKG_VERSION:=2016.01-rc3
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PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
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PKG_SOURCE_URL:= \
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http://mirror2.openwrt.org/sources \
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ftp://ftp.denx.de/pub/u-boot
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PKG_MD5SUM:=aca6c7a38534812ab529e90aae976422
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PKG_MD5SUM:=8ec1743d75448bd3d0c73f8722db9213
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PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
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28
package/boot/uboot-sunxi/patches/003-fix-h3-dramclk.patch
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28
package/boot/uboot-sunxi/patches/003-fix-h3-dramclk.patch
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@ -0,0 +1,28 @@
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From 0892c1d5371263e2a02c6fd484fa9647439a7ec9 Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Wed, 23 Dec 2015 11:48:40 +0100
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Subject: [PATCH] sunxi: Remove Orangepi PC RAM speed to 624 MHz
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There are some reports of stability issues at 672 MHz, see:
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http://linux-sunxi.org/Orange_Pi_PC#DRAM_clock_speed_limit
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So reduce the DRAM speed to 624MHz which seems to be reliable everywhere.
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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---
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configs/orangepi_pc_defconfig | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
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index 75afca9..358caa5 100644
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--- a/configs/orangepi_pc_defconfig
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+++ b/configs/orangepi_pc_defconfig
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@@ -1,7 +1,7 @@
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CONFIG_ARM=y
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CONFIG_ARCH_SUNXI=y
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CONFIG_MACH_SUN8I_H3=y
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-CONFIG_DRAM_CLK=672
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+CONFIG_DRAM_CLK=624
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CONFIG_DRAM_ZQ=3881979
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CONFIG_DRAM_ODT_EN=y
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# CONFIG_VIDEO is not set
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@ -0,0 +1,60 @@
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diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
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index dfb0a3e..7a6a3cc 100644
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--- a/arch/arm/cpu/armv7/sunxi/Makefile
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+++ b/arch/arm/cpu/armv7/sunxi/Makefile
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@@ -33,6 +33,7 @@ obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
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endif
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obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o
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obj-$(CONFIG_MACH_SUN6I) += tzpc.o
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+obj-$(CONFIG_MACH_SUN8I) += tzpc.o
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obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
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obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
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diff --git a/arch/arm/cpu/armv7/sunxi/tzpc.c b/arch/arm/cpu/armv7/sunxi/tzpc.c
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index 5c9c69b..6c8a0fd 100644
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--- a/arch/arm/cpu/armv7/sunxi/tzpc.c
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+++ b/arch/arm/cpu/armv7/sunxi/tzpc.c
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@@ -13,6 +13,15 @@ void tzpc_init(void)
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{
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struct sunxi_tzpc *tzpc = (struct sunxi_tzpc *)SUNXI_TZPC_BASE;
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+#ifdef CONFIG_MACH_SUN6I
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/* Enable non-secure access to the RTC */
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- writel(SUNXI_TZPC_DECPORT0_RTC, &tzpc->decport0_set);
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+ writel(SUN6I_TZPC_DECPORT0_RTC, &tzpc->decport0_set);
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+#endif
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+
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+#ifdef CONFIG_MACH_SUN8I_H3
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+ /* Enable non-secure access to all peripherals */
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+ writel(SUN8I_H3_TZPC_DECPORT0_ALL, &tzpc->decport0_set);
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+ writel(SUN8I_H3_TZPC_DECPORT1_ALL, &tzpc->decport1_set);
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+ writel(SUN8I_H3_TZPC_DECPORT2_ALL, &tzpc->decport2_set);
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+#endif
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}
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diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h b/arch/arm/include/asm/arch-sunxi/tzpc.h
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index ba4d43b..95c55cd 100644
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--- a/arch/arm/include/asm/arch-sunxi/tzpc.h
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+++ b/arch/arm/include/asm/arch-sunxi/tzpc.h
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@@ -13,10 +13,21 @@ struct sunxi_tzpc {
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u32 decport0_status; /* 0x04 Status of decode protection port 0 */
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u32 decport0_set; /* 0x08 Set decode protection port 0 */
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u32 decport0_clear; /* 0x0c Clear decode protection port 0 */
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+ /* For A80 and later SoCs */
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+ u32 decport1_status; /* 0x10 Status of decode protection port 1 */
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+ u32 decport1_set; /* 0x14 Set decode protection port 1 */
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+ u32 decport1_clear; /* 0x18 Clear decode protection port 1 */
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+ u32 decport2_status; /* 0x1c Status of decode protection port 2 */
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+ u32 decport2_set; /* 0x20 Set decode protection port 2 */
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+ u32 decport2_clear; /* 0x24 Clear decode protection port 2 */
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};
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#endif
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-#define SUNXI_TZPC_DECPORT0_RTC (1 << 1)
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+#define SUN6I_TZPC_DECPORT0_RTC (1 << 1)
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+
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+#define SUN8I_H3_TZPC_DECPORT0_ALL 0xbe
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+#define SUN8I_H3_TZPC_DECPORT1_ALL 0xff
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+#define SUN8I_H3_TZPC_DECPORT2_ALL 0x7f
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void tzpc_init(void);
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@ -0,0 +1,83 @@
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diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
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index 47fb70f..5cc5d25 100644
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--- a/arch/arm/cpu/armv7/sunxi/clock.c
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+++ b/arch/arm/cpu/armv7/sunxi/clock.c
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@@ -14,12 +14,17 @@
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#include <asm/arch/gpio.h>
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#include <asm/arch/sys_proto.h>
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+__weak void clock_init_sec(void)
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+{
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+}
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+
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int clock_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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clock_init_safe();
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#endif
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clock_init_uart();
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+ clock_init_sec();
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return 0;
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}
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diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
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index 4501884..d0085e8 100644
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--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
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+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
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@@ -45,6 +45,19 @@ void clock_init_safe(void)
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}
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#endif
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+void clock_init_sec(void)
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+{
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+ struct sunxi_ccm_reg * const ccm =
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+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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+
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+#ifdef CONFIG_MACH_SUN8I_H3
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+ setbits_le32(&ccm->ccu_sec_switch,
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+ CCM_SEC_SWITCH_MBUS_NONSEC |
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+ CCM_SEC_SWITCH_BUS_NONSEC |
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+ CCM_SEC_SWITCH_PLL_NONSEC);
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+#endif
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+}
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+
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void clock_init_uart(void)
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{
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#if CONFIG_CONS_INDEX < 5
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diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
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index 8ca58ae..6c0573f 100644
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--- a/arch/arm/include/asm/arch-sunxi/clock.h
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+++ b/arch/arm/include/asm/arch-sunxi/clock.h
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@@ -30,6 +30,7 @@ int clock_init(void);
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int clock_twi_onoff(int port, int state);
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void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz);
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void clock_init_safe(void);
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+void clock_init_sec(void);
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void clock_init_uart(void);
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#endif
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diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
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index 5c76275..554d858 100644
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--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
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+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
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@@ -137,6 +137,8 @@ struct sunxi_ccm_reg {
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u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */
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u32 reserved24;
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u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
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+ u32 reserved25[5];
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+ u32 ccu_sec_switch; /* 0x2f0 CCU Security Switch, H3 only */
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};
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/* apb2 bit field */
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@@ -375,6 +377,11 @@ struct sunxi_ccm_reg {
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#define CCM_DE_CTRL_PLL10 (5 << 24)
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#define CCM_DE_CTRL_GATE (1 << 31)
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+/* CCU security switch, H3 only */
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+#define CCM_SEC_SWITCH_MBUS_NONSEC (1 << 2)
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+#define CCM_SEC_SWITCH_BUS_NONSEC (1 << 1)
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+#define CCM_SEC_SWITCH_PLL_NONSEC (1 << 0)
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+
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#ifndef __ASSEMBLY__
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void clock_set_pll1(unsigned int hz);
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void clock_set_pll3(unsigned int hz);
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@ -0,0 +1,22 @@
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diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
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index 4ff46e4..90b5bfd 100644
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--- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
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+++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
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@@ -106,7 +106,7 @@ psci_fiq_enter:
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str r10, [r8, #0x100]
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timer_wait r10, ONE_MS
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-#ifdef CONFIG_MACH_SUN6I
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+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
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@ Activate power clamp
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lsl r12, r9, #2 @ x4
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add r12, r12, r8
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@@ -170,7 +170,7 @@ psci_cpu_on:
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movw r0, #(SUNXI_PRCM_BASE & 0xffff)
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movt r0, #(SUNXI_PRCM_BASE >> 16)
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-#ifdef CONFIG_MACH_SUN6I
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+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3)
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@ Release power clamp
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lsl r5, r1, #2 @ 1 register per CPU
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add r5, r5, r0 @ PRCM
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@ -0,0 +1,16 @@
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diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
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index 9d67847..28e6bb4 100644
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--- a/board/sunxi/Kconfig
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+++ b/board/sunxi/Kconfig
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@@ -71,8 +71,11 @@ config MACH_SUN8I_A33
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config MACH_SUN8I_H3
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bool "sun8i (Allwinner H3)"
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select CPU_V7
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+ select CPU_V7_HAS_NONSEC
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+ select CPU_V7_HAS_VIRT
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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+ select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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config MACH_SUN8I_A83T
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bool "sun8i (Allwinner A83T)"
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