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ramips: pci: sync with staging driver

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This is an amagalmation of two upstream commits dealing with whitespace
and dead code removal. I'm synching instead of having two separate commits
as they go out of order compared to previous commits here.

Tested on GnuBee PC1.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
This commit is contained in:
Rosen Penev 2018-05-14 11:14:22 -07:00 committed by John Crispin
parent 2d401925b9
commit e07baec9fa
1 changed files with 139 additions and 157 deletions
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296
target/linux/ramips/files-4.14/arch/mips/pci/pci-mt7621.c
View file

@ -52,108 +52,103 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_pci.h> #include <linux/of_pci.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <ralink_regs.h> #include <ralink_regs.h>
extern void pcie_phy_init(void);
extern void chk_phy_pll(void);
/* /*
* These functions and structures provide the BIOS scan and mapping of the PCI * These functions and structures provide the BIOS scan and mapping of the PCI
* devices. * devices.
*/ */
#define RALINK_PCIE0_CLK_EN (1<<24) #define RALINK_PCIE0_CLK_EN (1<<24)
#define RALINK_PCIE1_CLK_EN (1<<25) #define RALINK_PCIE1_CLK_EN (1<<25)
#define RALINK_PCIE2_CLK_EN (1<<26) #define RALINK_PCIE2_CLK_EN (1<<26)
#define RALINK_PCI_CONFIG_ADDR 0x20 #define RALINK_PCI_CONFIG_ADDR 0x20
#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028) #define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C) #define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
#define RALINK_PCIE0_RST (1<<24) #define RALINK_PCIE0_RST (1<<24)
#define RALINK_PCIE1_RST (1<<25) #define RALINK_PCIE1_RST (1<<25)
#define RALINK_PCIE2_RST (1<<26) #define RALINK_PCIE2_RST (1<<26)
#define RALINK_SYSCTL_BASE 0xBE000000 #define RALINK_SYSCTL_BASE 0xBE000000
#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000) #define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C) #define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
#define RALINK_PCI_BASE 0xBE140000 #define RALINK_PCI_BASE 0xBE140000
#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000) #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
#define RT6855_PCIE0_OFFSET 0x2000 #define RT6855_PCIE0_OFFSET 0x2000
#define RT6855_PCIE1_OFFSET 0x3000 #define RT6855_PCIE1_OFFSET 0x3000
#define RT6855_PCIE2_OFFSET 0x4000 #define RT6855_PCIE2_OFFSET 0x4000
#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010) #define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018) #define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030) #define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034) #define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038) #define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050) #define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060) #define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064) #define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010) #define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018) #define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030) #define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034) #define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038) #define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050) #define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060) #define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064) #define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010) #define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018) #define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030) #define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034) #define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038) #define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050) #define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060) #define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064) #define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000) #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000) #define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
#define MV_WRITE(ofs, data) \
*(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
#define MV_READ(ofs, data) \
*(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
#define MV_READ_DATA(ofs) \
le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
#define MV_WRITE(ofs, data) \ #define MV_WRITE_16(ofs, data) \
*(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data) *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
#define MV_READ(ofs, data) \ #define MV_READ_16(ofs, data) \
*(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs))) *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
#define MV_READ_DATA(ofs) \
le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
#define MV_WRITE_16(ofs, data) \ #define MV_WRITE_8(ofs, data) \
*(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data) *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
#define MV_READ_16(ofs, data) \ #define MV_READ_8(ofs, data) \
*(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs))) *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
#define MV_WRITE_8(ofs, data) \ #define RALINK_PCI_MM_MAP_BASE 0x60000000
*(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data #define RALINK_PCI_IO_MAP_BASE 0x1e160000
#define MV_READ_8(ofs, data) \
*(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
#define RALINK_PCI_MM_MAP_BASE 0x60000000
#define RALINK_PCI_IO_MAP_BASE 0x1e160000
#define RALINK_SYSTEM_CONTROL_BASE 0xbe000000 #define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
#define ASSERT_SYSRST_PCIE(val) do { \ #define ASSERT_SYSRST_PCIE(val) \
if (*(unsigned int *)(0xbe00000c) == 0x00030101) \ do { \
RALINK_RSTCTRL |= val; \ if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
else \ RALINK_RSTCTRL |= val; \
RALINK_RSTCTRL &= ~val; \ else \
} while(0) RALINK_RSTCTRL &= ~val; \
#define DEASSERT_SYSRST_PCIE(val) do { \ } while(0)
if (*(unsigned int *)(0xbe00000c) == 0x00030101) \ #define DEASSERT_SYSRST_PCIE(val) \
RALINK_RSTCTRL &= ~val; \ do { \
else \ if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
RALINK_RSTCTRL |= val; \ RALINK_RSTCTRL &= ~val; \
} while(0) else \
RALINK_RSTCTRL |= val; \
} while(0)
#define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14) #define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
#define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30) #define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
#define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34) #define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
@ -188,8 +183,6 @@ static int pcie_link_status = 0;
#define PCI_ACCESS_WRITE_2 4 #define PCI_ACCESS_WRITE_2 4
#define PCI_ACCESS_WRITE_4 5 #define PCI_ACCESS_WRITE_4 5
static int pcie_irq[3];
static int config_access(unsigned char access_type, struct pci_bus *bus, static int config_access(unsigned char access_type, struct pci_bus *bus,
unsigned int devfn, unsigned int where, u32 * data) unsigned int devfn, unsigned int where, u32 * data)
{ {
@ -275,7 +268,6 @@ write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
return PCIBIOS_SUCCESSFUL; return PCIBIOS_SUCCESSFUL;
} }
static int static int
pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val) pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
{ {
@ -303,13 +295,12 @@ pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u
} }
struct pci_ops mt7621_pci_ops= { struct pci_ops mt7621_pci_ops= {
.read = pci_config_read, .read = pci_config_read,
.write = pci_config_write, .write = pci_config_write,
}; };
static struct resource mt7621_res_pci_mem1; static struct resource mt7621_res_pci_mem1;
static struct resource mt7621_res_pci_io1; static struct resource mt7621_res_pci_io1;
static struct pci_controller mt7621_controller = { static struct pci_controller mt7621_controller = {
.pci_ops = &mt7621_pci_ops, .pci_ops = &mt7621_pci_ops,
.mem_resource = &mt7621_res_pci_mem1, .mem_resource = &mt7621_res_pci_mem1,
@ -322,10 +313,10 @@ read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned l
unsigned int address_reg, data_reg, address; unsigned int address_reg, data_reg, address;
address_reg = RALINK_PCI_CONFIG_ADDR; address_reg = RALINK_PCI_CONFIG_ADDR;
data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG; data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ; address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
MV_WRITE(address_reg, address); MV_WRITE(address_reg, address);
MV_READ(data_reg, val); MV_READ(data_reg, val);
return; return;
} }
@ -342,7 +333,6 @@ write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned
return; return;
} }
int int
pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{ {
@ -371,11 +361,8 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
void void
set_pcie_phy(u32 *addr, int start_b, int bits, int val) set_pcie_phy(u32 *addr, int start_b, int bits, int val)
{ {
// printk("0x%p:", addr);
// printk(" %x", *addr);
*(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b); *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
*(unsigned int *)(addr) |= val << start_b; *(unsigned int *)(addr) |= val << start_b;
// printk(" -> %x\n", *addr);
} }
void void
@ -402,75 +389,75 @@ set_phy_for_ssc(void)
/* Debug Xtal Type */ /* Debug Xtal Type */
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
if(reg <= 5 && reg >= 3) { // 40MHz Xtal if(reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
printk("***** Xtal 40MHz *****\n"); printk("***** Xtal 40MHz *****\n");
} else { // 25MHz | 20MHz Xtal } else { // 25MHz | 20MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
if (reg >= 6) { if (reg >= 6) {
printk("***** Xtal 25MHz *****\n"); printk("***** Xtal 25MHz *****\n");
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode) set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
} else { } else {
printk("***** Xtal 20MHz *****\n"); printk("***** Xtal 20MHz *****\n");
} }
} }
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
if(reg <= 5 && reg >= 3) { // 40MHz Xtal if(reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
} }
/* Enable PHY and disable force mode */ /* Enable PHY and disable force mode */
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
/* Set PCIe Port2 PHY to disable SSC */ /* Set PCIe Port2 PHY to disable SSC */
/* Debug Xtal Type */ /* Debug Xtal Type */
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
if(reg <= 5 && reg >= 3) { // 40MHz Xtal if(reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
} else { // 25MHz | 20MHz Xtal } else { // 25MHz | 20MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode) set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
if (reg >= 6) { // 25MHz Xtal if (reg >= 6) { // 25MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode) set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
} }
} }
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
if(reg <= 5 && reg >= 3) { // 40MHz Xtal if(reg <= 5 && reg >= 3) { // 40MHz Xtal
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
} }
/* Enable PHY and disable force mode */ /* Enable PHY and disable force mode */
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
} }
void setup_cm_memory_region(struct resource *mem_resource) void setup_cm_memory_region(struct resource *mem_resource)
@ -478,25 +465,21 @@ void setup_cm_memory_region(struct resource *mem_resource)
resource_size_t mask; resource_size_t mask;
if (mips_cps_numiocu(0)) { if (mips_cps_numiocu(0)) {
/* FIXME: hardware doesn't accept mask values with 1s after /* FIXME: hardware doesn't accept mask values with 1s after
0s (e.g. 0xffef), so it would be great to warn if that's * 0s (e.g. 0xffef), so it would be great to warn if that's
about to happen */ * about to happen */
mask = ~(mem_resource->end - mem_resource->start); mask = ~(mem_resource->end - mem_resource->start);
write_gcr_reg1_base(mem_resource->start); write_gcr_reg1_base(mem_resource->start);
write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0); write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n", printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
read_gcr_reg1_base(), (unsigned long long)read_gcr_reg1_base(),
read_gcr_reg1_mask()); (unsigned long long)read_gcr_reg1_mask());
} }
} }
static int mt7621_pci_probe(struct platform_device *pdev) static int mt7621_pci_probe(struct platform_device *pdev)
{ {
unsigned long val = 0; unsigned long val = 0;
int i;
for (i = 0; i < 3; i++)
pcie_irq[i] = irq_of_parse_and_map(pdev->dev.of_node, i);
iomem_resource.start = 0; iomem_resource.start = 0;
iomem_resource.end= ~0; iomem_resource.end= ~0;
@ -508,7 +491,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
val |= RALINK_PCIE2_RST; val |= RALINK_PCIE2_RST;
ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST); ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
*(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3); *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
*(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3; *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
@ -524,17 +506,17 @@ static int mt7621_pci_probe(struct platform_device *pdev)
val |= RALINK_PCIE2_RST; val |= RALINK_PCIE2_RST;
DEASSERT_SYSRST_PCIE(val); DEASSERT_SYSRST_PCIE(val);
printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2 if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
bypass_pipe_rst(); bypass_pipe_rst();
set_phy_for_ssc(); set_phy_for_ssc();
printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
read_config(0, 0, 0, 0x70c, &val); read_config(0, 0, 0, 0x70c, &val);
printk("Port 0 N_FTS = %x\n", (unsigned int)val); printk("Port 0 N_FTS = %x\n", (unsigned int)val);
read_config(0, 1, 0, 0x70c, &val); read_config(0, 1, 0, 0x70c, &val);
printk("Port 1 N_FTS = %x\n", (unsigned int)val); printk("Port 1 N_FTS = %x\n", (unsigned int)val);
read_config(0, 2, 0, 0x70c, &val); read_config(0, 2, 0, 0x70c, &val);
printk("Port 2 N_FTS = %x\n", (unsigned int)val); printk("Port 2 N_FTS = %x\n", (unsigned int)val);
@ -562,6 +544,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status |= 1<<0; pcie_link_status |= 1<<0;
RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
} }
if(( RALINK_PCI1_STATUS & 0x1) == 0) if(( RALINK_PCI1_STATUS & 0x1) == 0)
{ {
printk("PCIE1 no card, disable it(RST&CLK)\n"); printk("PCIE1 no card, disable it(RST&CLK)\n");
@ -572,6 +555,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status |= 1<<1; pcie_link_status |= 1<<1;
RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
} }
if (( RALINK_PCI2_STATUS & 0x1) == 0) { if (( RALINK_PCI2_STATUS & 0x1) == 0) {
printk("PCIE2 no card, disable it(RST&CLK)\n"); printk("PCIE2 no card, disable it(RST&CLK)\n");
ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST); ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
@ -581,6 +565,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
pcie_link_status |= 1<<2; pcie_link_status |= 1<<2;
RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
} }
if (pcie_link_status == 0) if (pcie_link_status == 0)
return 0; return 0;
@ -620,12 +605,10 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2 RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
break; break;
} }
printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
//printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
/* /*
ioport_resource.start = mt7621_res_pci_io1.start; ioport_resource.start = mt7621_res_pci_io1.start;
ioport_resource.end = mt7621_res_pci_io1.end; ioport_resource.end = mt7621_res_pci_io1.end;
*/ */
RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE; RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
@ -638,6 +621,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
RALINK_PCI0_CLASS = 0x06040001; RALINK_PCI0_CLASS = 0x06040001;
printk("PCIE0 enabled\n"); printk("PCIE0 enabled\n");
} }
//PCIe1 //PCIe1
if ((pcie_link_status & 0x2) != 0) { if ((pcie_link_status & 0x2) != 0) {
RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
@ -645,6 +629,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
RALINK_PCI1_CLASS = 0x06040001; RALINK_PCI1_CLASS = 0x06040001;
printk("PCIE1 enabled\n"); printk("PCIE1 enabled\n");
} }
//PCIe2 //PCIe2
if ((pcie_link_status & 0x4) != 0) { if ((pcie_link_status & 0x4) != 0) {
RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
@ -657,7 +642,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
case 7: case 7:
read_config(0, 2, 0, 0x4, &val); read_config(0, 2, 0, 0x4, &val);
write_config(0, 2, 0, 0x4, val|0x4); write_config(0, 2, 0, 0x4, val|0x4);
// write_config(0, 1, 0, 0x4, val|0x7);
read_config(0, 2, 0, 0x70c, &val); read_config(0, 2, 0, 0x70c, &val);
val &= ~(0xff)<<8; val &= ~(0xff)<<8;
val |= 0x50<<8; val |= 0x50<<8;
@ -667,7 +651,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
case 6: case 6:
read_config(0, 1, 0, 0x4, &val); read_config(0, 1, 0, 0x4, &val);
write_config(0, 1, 0, 0x4, val|0x4); write_config(0, 1, 0, 0x4, val|0x4);
// write_config(0, 1, 0, 0x4, val|0x7);
read_config(0, 1, 0, 0x70c, &val); read_config(0, 1, 0, 0x70c, &val);
val &= ~(0xff)<<8; val &= ~(0xff)<<8;
val |= 0x50<<8; val |= 0x50<<8;
@ -675,7 +658,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
default: default:
read_config(0, 0, 0, 0x4, &val); read_config(0, 0, 0, 0x4, &val);
write_config(0, 0, 0, 0x4, val|0x4); //bus master enable write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
// write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
read_config(0, 0, 0, 0x70c, &val); read_config(0, 0, 0, 0x70c, &val);
val &= ~(0xff)<<8; val &= ~(0xff)<<8;
val |= 0x50<<8; val |= 0x50<<8;