imx6: drop support for 3.13
Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 40754
This commit is contained in:
Luka Perkov
parent
aa3d844d34
commit
dce36465ad
9 changed files with 0 additions and 3006 deletions
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@ -1,362 +0,0 @@
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CONFIG_AHCI_IMX=y
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CONFIG_ALIGNMENT_TRAP=y
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CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
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CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
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CONFIG_ARCH_HAS_CPUFREQ=y
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CONFIG_ARCH_HAS_OPP=y
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CONFIG_ARCH_HAS_RESET_CONTROLLER=y
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CONFIG_ARCH_HAS_TICK_BROADCAST=y
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CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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CONFIG_ARCH_MULTIPLATFORM=y
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# CONFIG_ARCH_MULTI_CPU_AUTO is not set
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CONFIG_ARCH_MULTI_V6_V7=y
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CONFIG_ARCH_MULTI_V7=y
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CONFIG_ARCH_MXC=y
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# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
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CONFIG_ARCH_NR_GPIO=0
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CONFIG_ARCH_REQUIRE_GPIOLIB=y
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# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
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# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
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CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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CONFIG_ARM=y
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# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
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# CONFIG_ARM_CPU_SUSPEND is not set
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CONFIG_ARM_ERRATA_754322=y
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CONFIG_ARM_ERRATA_764369=y
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CONFIG_ARM_ERRATA_775420=y
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CONFIG_ARM_GIC=y
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CONFIG_ARM_IMX6Q_CPUFREQ=y
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# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
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CONFIG_ARM_L1_CACHE_SHIFT=6
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CONFIG_ARM_L1_CACHE_SHIFT_6=y
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# CONFIG_ARM_LPAE is not set
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CONFIG_ARM_NR_BANKS=8
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CONFIG_ARM_PATCH_PHYS_VIRT=y
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CONFIG_ARM_THUMB=y
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# CONFIG_ARM_THUMBEE is not set
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CONFIG_ARM_VIRT_EXT=y
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CONFIG_ATA=y
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CONFIG_ATAGS=y
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# CONFIG_ATA_SFF is not set
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CONFIG_AUTO_ZRELADDR=y
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# CONFIG_CACHE_L2X0 is not set
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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CONFIG_CLKDEV_LOOKUP=y
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CONFIG_CLKSRC_MMIO=y
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CONFIG_CLKSRC_OF=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_COMMON_CLK=y
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CONFIG_CPU_32v6K=y
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CONFIG_CPU_32v7=y
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CONFIG_CPU_ABRT_EV7=y
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# CONFIG_CPU_BPREDICT_DISABLE is not set
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CONFIG_CPU_CACHE_V7=y
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CONFIG_CPU_CACHE_VIPT=y
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CONFIG_CPU_COPY_V6=y
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CONFIG_CPU_CP15=y
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CONFIG_CPU_CP15_MMU=y
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CONFIG_CPU_FREQ=y
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# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
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# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
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CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
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# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
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# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
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CONFIG_CPU_FREQ_GOV_COMMON=y
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CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
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CONFIG_CPU_FREQ_GOV_ONDEMAND=y
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CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
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CONFIG_CPU_FREQ_GOV_POWERSAVE=y
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CONFIG_CPU_FREQ_GOV_USERSPACE=y
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CONFIG_CPU_FREQ_STAT=y
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CONFIG_CPU_FREQ_STAT_DETAILS=y
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CONFIG_CPU_HAS_ASID=y
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# CONFIG_CPU_ICACHE_DISABLE is not set
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CONFIG_CPU_PABRT_V7=y
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CONFIG_CPU_RMAP=y
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CONFIG_CPU_TLB_V7=y
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CONFIG_CPU_V7=y
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CONFIG_CRC16=y
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CONFIG_CRYPTO_CRC32C=y
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CONFIG_CRYPTO_DEFLATE=y
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CONFIG_CRYPTO_HASH=y
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CONFIG_CRYPTO_HASH2=y
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CONFIG_CRYPTO_LZO=y
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CONFIG_CRYPTO_XZ=y
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CONFIG_DCACHE_WORD_ACCESS=y
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CONFIG_DEBUG_IMX_UART_PORT=1
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CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
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# CONFIG_DEBUG_UART_8250 is not set
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# CONFIG_DEBUG_UART_PL01X is not set
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# CONFIG_DEBUG_USER is not set
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CONFIG_DECOMPRESS_BZIP2=y
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CONFIG_DECOMPRESS_GZIP=y
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CONFIG_DECOMPRESS_LZO=y
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CONFIG_DECOMPRESS_XZ=y
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CONFIG_DMADEVICES=y
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CONFIG_DMA_ENGINE=y
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CONFIG_DMA_OF=y
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CONFIG_DTC=y
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# CONFIG_DW_DMAC_CORE is not set
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# CONFIG_DW_DMAC_PCI is not set
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CONFIG_EXT2_FS=y
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CONFIG_EXT2_FS_POSIX_ACL=y
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CONFIG_EXT2_FS_SECURITY=y
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CONFIG_EXT2_FS_XATTR=y
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CONFIG_EXT3_FS=y
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CONFIG_EXT3_FS_POSIX_ACL=y
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CONFIG_EXT3_FS_SECURITY=y
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CONFIG_EXT3_FS_XATTR=y
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CONFIG_EXT4_FS=y
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CONFIG_EXT4_FS_POSIX_ACL=y
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CONFIG_EXT4_FS_SECURITY=y
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CONFIG_FEC=y
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CONFIG_FRAME_POINTER=y
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CONFIG_FS_MBCACHE=y
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CONFIG_FS_POSIX_ACL=y
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
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CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
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CONFIG_GENERIC_CPUFREQ_CPU0=y
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CONFIG_GENERIC_IDLE_POLL_SETUP=y
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CONFIG_GENERIC_IO=y
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CONFIG_GENERIC_IRQ_CHIP=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_NET_UTILS=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_STRNCPY_FROM_USER=y
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CONFIG_GENERIC_STRNLEN_USER=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_DEVRES=y
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CONFIG_GPIO_GENERIC=y
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CONFIG_GPIO_MXC=y
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CONFIG_GPIO_SYSFS=y
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# CONFIG_HAMRADIO is not set
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CONFIG_HARDIRQS_SW_RESEND=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT=y
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# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
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CONFIG_HAVE_ARCH_JUMP_LABEL=y
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CONFIG_HAVE_ARCH_KGDB=y
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CONFIG_HAVE_ARCH_PFN_VALID=y
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CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
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CONFIG_HAVE_ARCH_TRACEHOOK=y
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CONFIG_HAVE_ARM_SCU=y
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CONFIG_HAVE_ARM_TWD=y
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# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
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CONFIG_HAVE_BPF_JIT=y
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CONFIG_HAVE_CLK=y
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CONFIG_HAVE_CLK_PREPARE=y
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CONFIG_HAVE_CONTEXT_TRACKING=y
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CONFIG_HAVE_C_RECORDMCOUNT=y
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CONFIG_HAVE_DEBUG_KMEMLEAK=y
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CONFIG_HAVE_DMA_API_DEBUG=y
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CONFIG_HAVE_DMA_ATTRS=y
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CONFIG_HAVE_DMA_CONTIGUOUS=y
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CONFIG_HAVE_DYNAMIC_FTRACE=y
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_HW_BREAKPOINT=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_IMX_ANATOP=y
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CONFIG_HAVE_IMX_GPC=y
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CONFIG_HAVE_IMX_MMDC=y
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CONFIG_HAVE_IMX_SRC=y
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CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
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CONFIG_HAVE_KERNEL_GZIP=y
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CONFIG_HAVE_KERNEL_LZ4=y
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CONFIG_HAVE_KERNEL_LZMA=y
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CONFIG_HAVE_KERNEL_LZO=y
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CONFIG_HAVE_KERNEL_XZ=y
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CONFIG_HAVE_MEMBLOCK=y
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CONFIG_HAVE_NET_DSA=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HAVE_PERF_EVENTS=y
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CONFIG_HAVE_PERF_REGS=y
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CONFIG_HAVE_PERF_USER_STACK_DUMP=y
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CONFIG_HAVE_PROC_CPU=y
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CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
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CONFIG_HAVE_SMP=y
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CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
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CONFIG_HAVE_UID16=y
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CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
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CONFIG_HZ_FIXED=0
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CONFIG_I2C=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_IMX=y
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CONFIG_IMX2_WDT=y
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CONFIG_IMX_DMA=y
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CONFIG_IMX_SDMA=y
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# CONFIG_IMX_WEIM is not set
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IOMMU_HELPER=y
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_WORK=y
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CONFIG_JBD=y
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CONFIG_JBD2=y
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CONFIG_KTIME_SCALAR=y
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# CONFIG_LEDS_REGULATOR is not set
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CONFIG_LZO_COMPRESS=y
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CONFIG_LZO_DECOMPRESS=y
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# CONFIG_MACH_EUKREA_CPUIMX51SD is not set
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# CONFIG_MACH_IMX51_DT is not set
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# CONFIG_MACH_MX51_BABBAGE is not set
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CONFIG_MDIO_BOARDINFO=y
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CONFIG_MFD_SYSCON=y
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CONFIG_MIGHT_HAVE_CACHE_L2X0=y
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CONFIG_MIGHT_HAVE_PCI=y
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CONFIG_MMC=y
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CONFIG_MMC_BLOCK=y
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# CONFIG_MMC_MXC is not set
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ESDHC_IMX=y
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CONFIG_MMC_SDHCI_IO_ACCESSORS=y
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# CONFIG_MMC_SDHCI_PCI is not set
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CONFIG_MMC_SDHCI_PLTFM=y
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# CONFIG_MMC_TIFM_SD is not set
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CONFIG_MODULES_USE_ELF_REL=y
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CONFIG_MTD_M25P80=y
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CONFIG_MTD_NAND=y
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CONFIG_MTD_NAND_ECC=y
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CONFIG_MTD_NAND_GPMI_NAND=y
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# CONFIG_MTD_PHYSMAP_OF is not set
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# CONFIG_MTD_SM_COMMON is not set
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CONFIG_MTD_UBI=y
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CONFIG_MTD_UBI_BEB_LIMIT=20
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# CONFIG_MTD_UBI_FASTMAP is not set
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# CONFIG_MTD_UBI_GLUEBI is not set
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CONFIG_MTD_UBI_WL_THRESHOLD=4096
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CONFIG_MULTI_IRQ_HANDLER=y
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CONFIG_MUTEX_SPIN_ON_OWNER=y
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# CONFIG_MX3_IPU is not set
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# CONFIG_MXC_DEBUG_BOARD is not set
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# CONFIG_MXC_IRQ_PRIOR is not set
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CONFIG_MXS_DMA=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NEON=y
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CONFIG_NET_FLOW_LIMIT=y
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CONFIG_NET_RX_BUSY_POLL=y
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CONFIG_NLS=y
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CONFIG_NLS_CODEPAGE_437=y
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CONFIG_NO_HZ_COMMON=y
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CONFIG_NO_HZ_IDLE=y
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CONFIG_NR_CPUS=4
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CONFIG_OF=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_EARLY_FLATTREE=y
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CONFIG_OF_FLATTREE=y
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CONFIG_OF_GPIO=y
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CONFIG_OF_IRQ=y
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CONFIG_OF_MDIO=y
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CONFIG_OF_MTD=y
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CONFIG_OF_NET=y
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CONFIG_OF_PCI=y
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CONFIG_OF_PCI_IRQ=y
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||||||
CONFIG_OLD_SIGACTION=y
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CONFIG_OLD_SIGSUSPEND3=y
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CONFIG_PAGEFLAGS_EXTENDED=y
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CONFIG_PAGE_OFFSET=0x80000000
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CONFIG_PCI=y
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CONFIG_PCIEAER=y
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||||||
CONFIG_PCIEPORTBUS=y
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CONFIG_PCIE_DW=y
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||||||
CONFIG_PCI_DOMAINS=y
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||||||
CONFIG_PCI_IMX6=y
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||||||
CONFIG_PERF_EVENTS=y
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||||||
CONFIG_PERF_USE_VMALLOC=y
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||||||
CONFIG_PHYLIB=y
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||||||
CONFIG_PINCTRL=y
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||||||
CONFIG_PINCTRL_IMX=y
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||||||
CONFIG_PINCTRL_IMX6Q=y
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||||||
CONFIG_PINCTRL_IMX6SL=y
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||||||
# CONFIG_PINCTRL_SINGLE is not set
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||||||
CONFIG_PM_OPP=y
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|
||||||
CONFIG_PPS=y
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||||||
# CONFIG_PREEMPT_RCU is not set
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|
||||||
CONFIG_PROC_DEVICETREE=y
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|
||||||
CONFIG_PTP_1588_CLOCK=y
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||||||
CONFIG_RATIONAL=y
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|
||||||
CONFIG_RCU_STALL_COMMON=y
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|
||||||
CONFIG_RD_BZIP2=y
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|
||||||
CONFIG_RD_GZIP=y
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||||||
CONFIG_RD_LZO=y
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|
||||||
CONFIG_RD_XZ=y
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|
||||||
CONFIG_REGMAP=y
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|
||||||
CONFIG_REGMAP_I2C=y
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|
||||||
CONFIG_REGMAP_MMIO=y
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|
||||||
CONFIG_REGMAP_SPI=y
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|
||||||
CONFIG_REGULATOR=y
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|
||||||
CONFIG_REGULATOR_ANATOP=y
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|
||||||
# CONFIG_REGULATOR_DEBUG is not set
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|
||||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
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|
||||||
CONFIG_REGULATOR_PFUZE100=y
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|
||||||
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
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|
||||||
# CONFIG_RFKILL_REGULATOR is not set
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|
||||||
CONFIG_RFS_ACCEL=y
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|
||||||
CONFIG_RPS=y
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|
||||||
CONFIG_RTC_CLASS=y
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|
||||||
# CONFIG_RTC_DRV_IMXDI is not set
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|
||||||
# CONFIG_RTC_DRV_MXC is not set
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|
||||||
CONFIG_SATA_AHCI_PLATFORM=y
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|
||||||
CONFIG_SCHED_HRTICK=y
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|
||||||
CONFIG_SCSI=y
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|
||||||
CONFIG_SERIAL_IMX=y
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|
||||||
CONFIG_SERIAL_IMX_CONSOLE=y
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|
||||||
CONFIG_SMP=y
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|
||||||
CONFIG_SMP_ON_UP=y
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|
||||||
CONFIG_SOC_BUS=y
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|
||||||
# CONFIG_SOC_IMX53 is not set
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|
||||||
CONFIG_SOC_IMX6Q=y
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|
||||||
CONFIG_SOC_IMX6SL=y
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|
||||||
# CONFIG_SOC_VF610 is not set
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|
||||||
CONFIG_SPARSE_IRQ=y
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|
||||||
CONFIG_SPI=y
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|
||||||
CONFIG_SPI_BITBANG=y
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||||||
CONFIG_SPI_IMX=y
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||||||
CONFIG_SPI_MASTER=y
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|
||||||
CONFIG_STMP_DEVICE=y
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|
||||||
CONFIG_STOP_MACHINE=y
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|
||||||
CONFIG_SWIOTLB=y
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|
||||||
# CONFIG_SWP_EMULATE is not set
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|
||||||
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
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|
||||||
# CONFIG_THUMB2_KERNEL is not set
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|
||||||
CONFIG_TICK_CPU_ACCOUNTING=y
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|
||||||
CONFIG_TREE_RCU=y
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|
||||||
CONFIG_UBIFS_FS=y
|
|
||||||
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
|
|
||||||
CONFIG_UBIFS_FS_LZO=y
|
|
||||||
CONFIG_UBIFS_FS_XZ=y
|
|
||||||
CONFIG_UBIFS_FS_ZLIB=y
|
|
||||||
CONFIG_UID16=y
|
|
||||||
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
|
|
||||||
# CONFIG_USB_MXS_PHY is not set
|
|
||||||
CONFIG_USB_SUPPORT=y
|
|
||||||
CONFIG_USE_OF=y
|
|
||||||
CONFIG_VECTORS_BASE=0xffff0000
|
|
||||||
CONFIG_VFP=y
|
|
||||||
CONFIG_VFPv3=y
|
|
||||||
CONFIG_VMSPLIT_2G=y
|
|
||||||
# CONFIG_VMSPLIT_3G is not set
|
|
||||||
# CONFIG_XEN is not set
|
|
||||||
CONFIG_XPS=y
|
|
||||||
CONFIG_XZ_DEC_ARM=y
|
|
||||||
CONFIG_XZ_DEC_BCJ=y
|
|
||||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
|
||||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
|
||||||
# CONFIG_ZBUD is not set
|
|
||||||
CONFIG_ZLIB_DEFLATE=y
|
|
||||||
CONFIG_ZLIB_INFLATE=y
|
|
||||||
CONFIG_ZONE_DMA_FLAG=0
|
|
||||||
|
|
@ -1,31 +0,0 @@
|
||||||
From 1759b172f78263de7077a2743e11f3b718682849 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Tim Harvey <tharvey@gateworks.com>
|
|
||||||
Date: Tue, 22 Oct 2013 21:51:27 -0700
|
|
||||||
Subject: [PATCH 1/3] ARM: dts: disable flexcan by default
|
|
||||||
|
|
||||||
Typically nodes are disabled by default and enabled when needed.
|
|
||||||
|
|
||||||
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
|
||||||
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
||||||
---
|
|
||||||
arch/arm/boot/dts/imx6qdl.dtsi | 2 ++
|
|
||||||
1 file changed, 2 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm/boot/dts/imx6qdl.dtsi
|
|
||||||
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
|
|
||||||
@@ -331,6 +331,7 @@
|
|
||||||
interrupts = <0 110 0x04>;
|
|
||||||
clocks = <&clks 108>, <&clks 109>;
|
|
||||||
clock-names = "ipg", "per";
|
|
||||||
+ status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
can2: flexcan@02094000 {
|
|
||||||
@@ -339,6 +340,7 @@
|
|
||||||
interrupts = <0 111 0x04>;
|
|
||||||
clocks = <&clks 110>, <&clks 111>;
|
|
||||||
clock-names = "ipg", "per";
|
|
||||||
+ status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
gpt: gpt@02098000 {
|
|
||||||
|
|
@ -1,115 +0,0 @@
|
||||||
From 925467009cc6d92edb02b9e68710db022cd56f41 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Tim Harvey <tharvey@gateworks.com>
|
|
||||||
Date: Tue, 22 Oct 2013 21:51:25 -0700
|
|
||||||
Subject: [PATCH 2/3] ARM: dts: added several new imx-pinmux groups
|
|
||||||
|
|
||||||
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
|
||||||
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
||||||
---
|
|
||||||
arch/arm/boot/dts/imx6qdl.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++++
|
|
||||||
1 file changed, 60 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm/boot/dts/imx6qdl.dtsi
|
|
||||||
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
|
|
||||||
@@ -639,6 +639,14 @@
|
|
||||||
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
|
|
||||||
>;
|
|
||||||
};
|
|
||||||
+
|
|
||||||
+ pinctrl_audmux_4: audmux-4 {
|
|
||||||
+ fsl,pins = <
|
|
||||||
+ MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x80000000
|
|
||||||
+ MX6QDL_PAD_EIM_D25__AUD5_RXC 0x80000000
|
|
||||||
+ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
|
|
||||||
+ >;
|
|
||||||
+ };
|
|
||||||
};
|
|
||||||
|
|
||||||
ecspi1 {
|
|
||||||
@@ -811,6 +819,28 @@
|
|
||||||
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
|
|
||||||
>;
|
|
||||||
};
|
|
||||||
+
|
|
||||||
+ /* No Strobe */
|
|
||||||
+ pinctrl_gpmi_nand_2: gpmi-nand-2 {
|
|
||||||
+ fsl,pins = <
|
|
||||||
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
|
||||||
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
|
||||||
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
|
||||||
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
|
||||||
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
|
||||||
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
|
|
||||||
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
|
||||||
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
|
||||||
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
|
||||||
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
|
||||||
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
|
||||||
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
|
||||||
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
|
||||||
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
|
||||||
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
|
||||||
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
|
||||||
+ >;
|
|
||||||
+ };
|
|
||||||
};
|
|
||||||
|
|
||||||
hdmi_hdcp {
|
|
||||||
@@ -1058,6 +1088,13 @@
|
|
||||||
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
|
||||||
>;
|
|
||||||
};
|
|
||||||
+
|
|
||||||
+ pinctrl_uart1_2: uart1grp-2 {
|
|
||||||
+ fsl,pins = <
|
|
||||||
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
|
||||||
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
|
|
||||||
+ >;
|
|
||||||
+ };
|
|
||||||
};
|
|
||||||
|
|
||||||
uart2 {
|
|
||||||
@@ -1076,6 +1113,13 @@
|
|
||||||
MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
|
|
||||||
>;
|
|
||||||
};
|
|
||||||
+
|
|
||||||
+ pinctrl_uart2_3: uart2grp-3 {
|
|
||||||
+ fsl,pins = <
|
|
||||||
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
|
|
||||||
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
|
|
||||||
+ >;
|
|
||||||
+ };
|
|
||||||
};
|
|
||||||
|
|
||||||
uart3 {
|
|
||||||
@@ -1096,6 +1140,13 @@
|
|
||||||
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
|
|
||||||
>;
|
|
||||||
};
|
|
||||||
+
|
|
||||||
+ pinctrl_uart3_3: uart3grp-3 {
|
|
||||||
+ fsl,pins = <
|
|
||||||
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
|
|
||||||
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
|
|
||||||
+ >;
|
|
||||||
+ };
|
|
||||||
};
|
|
||||||
|
|
||||||
uart4 {
|
|
||||||
@@ -1106,6 +1157,15 @@
|
|
||||||
>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
+
|
|
||||||
+ uart5 {
|
|
||||||
+ pinctrl_uart5_1: uart5grp-1 {
|
|
||||||
+ fsl,pins = <
|
|
||||||
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
|
|
||||||
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
|
|
||||||
+ >;
|
|
||||||
+ };
|
|
||||||
+ };
|
|
||||||
|
|
||||||
usbotg {
|
|
||||||
pinctrl_usbotg_1: usbotggrp-1 {
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,68 +0,0 @@
|
||||||
From 4bb1d09fe48f51efac2f51b9280796e2d00a6c4a Mon Sep 17 00:00:00 2001
|
|
||||||
From: Tim Harvey <tharvey@gateworks.com>
|
|
||||||
Date: Tue, 22 Oct 2013 21:51:28 -0700
|
|
||||||
Subject: [PATCH] ARM: imx: add PCI fixup for PEX860X on Gateworks board
|
|
||||||
|
|
||||||
The PEX860X has GPIO's which are used for PCI Reset lines on the
|
|
||||||
Gateworks Ventana boards. The GPIO's need to be set as output
|
|
||||||
level high so as to allow the PCIe devices to come out of reset.
|
|
||||||
|
|
||||||
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
|
||||||
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
||||||
---
|
|
||||||
arch/arm/mach-imx/mach-imx6q.c | 30 ++++++++++++++++++++++++++++++
|
|
||||||
1 file changed, 30 insertions(+)
|
|
||||||
|
|
||||||
--- a/arch/arm/mach-imx/mach-imx6q.c
|
|
||||||
+++ b/arch/arm/mach-imx/mach-imx6q.c
|
|
||||||
@@ -13,6 +13,7 @@
|
|
||||||
#include <linux/clk.h>
|
|
||||||
#include <linux/clkdev.h>
|
|
||||||
#include <linux/cpu.h>
|
|
||||||
+#include <linux/delay.h>
|
|
||||||
#include <linux/export.h>
|
|
||||||
#include <linux/init.h>
|
|
||||||
#include <linux/io.h>
|
|
||||||
@@ -23,6 +24,7 @@
|
|
||||||
#include <linux/of_irq.h>
|
|
||||||
#include <linux/of_platform.h>
|
|
||||||
#include <linux/pm_opp.h>
|
|
||||||
+#include <linux/pci.h>
|
|
||||||
#include <linux/phy.h>
|
|
||||||
#include <linux/reboot.h>
|
|
||||||
#include <linux/regmap.h>
|
|
||||||
@@ -78,6 +80,34 @@ static int ksz9031rn_phy_fixup(struct ph
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
+/*
|
|
||||||
+ * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
|
|
||||||
+ * as they are used for slots1-7 PERST#
|
|
||||||
+ */
|
|
||||||
+static void ventana_pciesw_early_fixup(struct pci_dev *dev)
|
|
||||||
+{
|
|
||||||
+ u32 dw;
|
|
||||||
+
|
|
||||||
+ if (!of_machine_is_compatible("gw,ventana"))
|
|
||||||
+ return;
|
|
||||||
+
|
|
||||||
+ if (dev->devfn != 0)
|
|
||||||
+ return;
|
|
||||||
+
|
|
||||||
+ pci_read_config_dword(dev, 0x62c, &dw);
|
|
||||||
+ dw |= 0xaaa8; // GPIO1-7 outputs
|
|
||||||
+ pci_write_config_dword(dev, 0x62c, dw);
|
|
||||||
+
|
|
||||||
+ pci_read_config_dword(dev, 0x644, &dw);
|
|
||||||
+ dw |= 0xfe; // GPIO1-7 output high
|
|
||||||
+ pci_write_config_dword(dev, 0x644, dw);
|
|
||||||
+
|
|
||||||
+ msleep(100);
|
|
||||||
+}
|
|
||||||
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
|
|
||||||
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
|
|
||||||
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
|
|
||||||
+
|
|
||||||
static int ar8031_phy_fixup(struct phy_device *dev)
|
|
||||||
{
|
|
||||||
u16 val;
|
|
||||||
|
|
@ -1,67 +0,0 @@
|
||||||
From fce8591f73c6a30c231f220d1092362aae0b985c Mon Sep 17 00:00:00 2001
|
|
||||||
From: Pratyush Anand <pratyush.anand@st.com>
|
|
||||||
Date: Wed, 11 Dec 2013 15:08:33 +0530
|
|
||||||
Subject: [PATCH] PCI: designware: Fix I/O transfers by using CPU (not realio)
|
|
||||||
address
|
|
||||||
|
|
||||||
pp->io_base, which is the input of the outbound IO address translation
|
|
||||||
unit, should be the CPU address. It was incorrectly programmed to the
|
|
||||||
realio address.
|
|
||||||
|
|
||||||
We should pass global_io_offset rather than sys->io_offset to
|
|
||||||
pci_ioremap_io(), so we map the new window into the first available spot in
|
|
||||||
the Linux view of the I/O space.
|
|
||||||
|
|
||||||
We must also pass CPU address instead of realio address to pci_ioremap_io().
|
|
||||||
|
|
||||||
This patch fixes above issue. It has been tested with Lecroy PTC in AIC
|
|
||||||
mode and Pericom PI7C9X2G303EL PCIe switch, which does not work otherwise.
|
|
||||||
|
|
||||||
Tested-by: Mohit Kumar <mohit.kumar@st.com>
|
|
||||||
Tested-by: Tim Harvey <tharvey@gateworks.com>
|
|
||||||
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
|
|
||||||
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
|
||||||
Reviewed-by: Marek Vasut <marex@denx.de
|
|
||||||
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
|
|
||||||
Acked-by: Arnd Bergmann <arnd@arndb.de>
|
|
||||||
Acked-by: Jingoo Han <jg1.han@samsung.com>
|
|
||||||
Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
|
|
||||||
---
|
|
||||||
drivers/pci/host/pcie-designware.c | 5 ++---
|
|
||||||
1 file changed, 2 insertions(+), 3 deletions(-)
|
|
||||||
|
|
||||||
--- a/drivers/pci/host/pcie-designware.c
|
|
||||||
+++ b/drivers/pci/host/pcie-designware.c
|
|
||||||
@@ -394,6 +394,7 @@ int __init dw_pcie_host_init(struct pcie
|
|
||||||
+ global_io_offset);
|
|
||||||
pp->config.io_size = resource_size(&pp->io);
|
|
||||||
pp->config.io_bus_addr = range.pci_addr;
|
|
||||||
+ pp->io_base = range.cpu_addr;
|
|
||||||
}
|
|
||||||
if (restype == IORESOURCE_MEM) {
|
|
||||||
of_pci_range_to_resource(&range, np, &pp->mem);
|
|
||||||
@@ -419,7 +420,6 @@ int __init dw_pcie_host_init(struct pcie
|
|
||||||
|
|
||||||
pp->cfg0_base = pp->cfg.start;
|
|
||||||
pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
|
|
||||||
- pp->io_base = pp->io.start;
|
|
||||||
pp->mem_base = pp->mem.start;
|
|
||||||
|
|
||||||
pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
|
|
||||||
@@ -585,7 +585,6 @@ static int dw_pcie_wr_other_conf(struct
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
-
|
|
||||||
static int dw_pcie_valid_config(struct pcie_port *pp,
|
|
||||||
struct pci_bus *bus, int dev)
|
|
||||||
{
|
|
||||||
@@ -679,7 +678,7 @@ static int dw_pcie_setup(int nr, struct
|
|
||||||
|
|
||||||
if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
|
|
||||||
sys->io_offset = global_io_offset - pp->config.io_bus_addr;
|
|
||||||
- pci_ioremap_io(sys->io_offset, pp->io.start);
|
|
||||||
+ pci_ioremap_io(global_io_offset, pp->io_base);
|
|
||||||
global_io_offset += SZ_64K;
|
|
||||||
pci_add_resource_offset(&sys->resources, &pp->io,
|
|
||||||
sys->io_offset);
|
|
||||||
|
|
@ -1,69 +0,0 @@
|
||||||
From: Tim Harvey <tharvey@gateworks.com>
|
|
||||||
Subject: [PATCH] sky2: allow mac to come from dt
|
|
||||||
|
|
||||||
The driver reads the mac address from the device registers which would
|
|
||||||
need to have been programmed by the bootloader. This patch adds
|
|
||||||
the ability to pull the mac from devicetree via the aliases/sky2 node.
|
|
||||||
|
|
||||||
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
|
||||||
---
|
|
||||||
drivers/net/ethernet/marvell/sky2.c | 33 ++++++++++++++++++++++++++++++++-
|
|
||||||
1 file changed, 32 insertions(+), 1 deletion(-)
|
|
||||||
|
|
||||||
--- a/drivers/net/ethernet/marvell/sky2.c
|
|
||||||
+++ b/drivers/net/ethernet/marvell/sky2.c
|
|
||||||
@@ -44,6 +44,8 @@
|
|
||||||
#include <linux/prefetch.h>
|
|
||||||
#include <linux/debugfs.h>
|
|
||||||
#include <linux/mii.h>
|
|
||||||
+#include <linux/of_device.h>
|
|
||||||
+#include <linux/of_net.h>
|
|
||||||
|
|
||||||
#include <asm/irq.h>
|
|
||||||
|
|
||||||
@@ -4748,6 +4750,7 @@ static struct net_device *sky2_init_netd
|
|
||||||
{
|
|
||||||
struct sky2_port *sky2;
|
|
||||||
struct net_device *dev = alloc_etherdev(sizeof(*sky2));
|
|
||||||
+ unsigned char *iap, tmpaddr[ETH_ALEN];
|
|
||||||
|
|
||||||
if (!dev)
|
|
||||||
return NULL;
|
|
||||||
@@ -4805,8 +4808,36 @@ static struct net_device *sky2_init_netd
|
|
||||||
|
|
||||||
dev->features |= dev->hw_features;
|
|
||||||
|
|
||||||
+ /*
|
|
||||||
+ * try to get mac address in the following order:
|
|
||||||
+ * 1) from device tree data
|
|
||||||
+ * 2) from internal registers set by bootloader
|
|
||||||
+ */
|
|
||||||
+ iap = NULL;
|
|
||||||
+ if (IS_ENABLED(CONFIG_OF)) {
|
|
||||||
+ struct device_node *np;
|
|
||||||
+ np = of_find_node_by_path("/aliases");
|
|
||||||
+ if (np) {
|
|
||||||
+ const char *path = of_get_property(np, "sky2", NULL);
|
|
||||||
+ if (path)
|
|
||||||
+ np = of_find_node_by_path(path);
|
|
||||||
+ if (np)
|
|
||||||
+ path = of_get_mac_address(np);
|
|
||||||
+ if (path)
|
|
||||||
+ iap = (unsigned char *) path;
|
|
||||||
+ }
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
+ /*
|
|
||||||
+ * 2) mac registers set by bootloader
|
|
||||||
+ */
|
|
||||||
+ if (!iap || !is_valid_ether_addr(iap)) {
|
|
||||||
+ memcpy_fromio(&tmpaddr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
|
|
||||||
+ iap = &tmpaddr[0];
|
|
||||||
+ }
|
|
||||||
+
|
|
||||||
/* read the mac address */
|
|
||||||
- memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
|
|
||||||
+ memcpy(dev->dev_addr, iap, ETH_ALEN);
|
|
||||||
|
|
||||||
return dev;
|
|
||||||
}
|
|
||||||
|
|
@ -1,11 +0,0 @@
|
||||||
--- a/arch/arm/boot/dts/imx6dl-wandboard.dts
|
|
||||||
+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
|
|
||||||
@@ -19,4 +19,8 @@
|
|
||||||
memory {
|
|
||||||
reg = <0x10000000 0x40000000>;
|
|
||||||
};
|
|
||||||
+
|
|
||||||
+ chosen {
|
|
||||||
+ bootargs = "console=ttymxc0,115200";
|
|
||||||
+ };
|
|
||||||
};
|
|
||||||
|
|
@ -1,43 +0,0 @@
|
||||||
From: Tim Harvey <tharvey@gateworks.com>
|
|
||||||
Subject: [PATCH] PCI: imx6: add support for legacy irqs
|
|
||||||
|
|
||||||
The i.MX6 supports legacy IRQ's via 155,154,153,152. When devices
|
|
||||||
are behind a PCIe-to-PCIe switch (at least for the TI XIO2001) the
|
|
||||||
mapping is reversed from when they are behind a PCIe switch.
|
|
||||||
|
|
||||||
This patch still needs some review and clarification before going
|
|
||||||
upstream.
|
|
||||||
---
|
|
||||||
drivers/pci/host/pcie-designware.c | 21 ++++++++++++++++++++-
|
|
||||||
1 file changed, 20 insertions(+), 1 deletion(-)
|
|
||||||
|
|
||||||
--- a/drivers/pci/host/pcie-designware.c
|
|
||||||
+++ b/drivers/pci/host/pcie-designware.c
|
|
||||||
@@ -711,7 +711,26 @@ static int dw_pcie_map_irq(const struct
|
|
||||||
{
|
|
||||||
struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
|
|
||||||
|
|
||||||
- return pp->irq;
|
|
||||||
+ /* TI XIO2001 PCIe-to-PCI bridge IRQs are flipped it seems */
|
|
||||||
+ if ( dev->bus && dev->bus->self
|
|
||||||
+ && (dev->bus->self->vendor == 0x104c)
|
|
||||||
+ && (dev->bus->self->device == 0x8240)) {
|
|
||||||
+ switch (pin) {
|
|
||||||
+ case 1: return pp->irq - 3;
|
|
||||||
+ case 2: return pp->irq - 2;
|
|
||||||
+ case 3: return pp->irq - 1;
|
|
||||||
+ case 4: return pp->irq;
|
|
||||||
+ default: return -1;
|
|
||||||
+ }
|
|
||||||
+ } else {
|
|
||||||
+ switch (pin) {
|
|
||||||
+ case 1: return pp->irq;
|
|
||||||
+ case 2: return pp->irq - 1;
|
|
||||||
+ case 3: return pp->irq - 2;
|
|
||||||
+ case 4: return pp->irq - 3;
|
|
||||||
+ default: return -1;
|
|
||||||
+ }
|
|
||||||
+ }
|
|
||||||
}
|
|
||||||
|
|
||||||
static void dw_pcie_add_bus(struct pci_bus *bus)
|
|
||||||
Loading…
Reference in a new issue