ar71xx: ar934x_nfc: add experimental support for hardware ECC
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 38069
This commit is contained in:
Gabor Juhos
parent
ceecdfb1c9
commit
d6fef0cb39
4 changed files with 352 additions and 3 deletions
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@ -206,6 +206,7 @@ CONFIG_MTD_M25P80=y
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# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
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# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
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CONFIG_MTD_MYLOADER_PARTS=y
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# CONFIG_MTD_NAND_AR934X_HW_ECC is not set
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2
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CONFIG_MTD_REDBOOT_PARTS=y
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@ -1,7 +1,7 @@
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/*
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* Driver for the built-in NAND controller of the Atheros AR934x SoCs
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*
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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@ -122,6 +122,24 @@
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#define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
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#define AR934X_NFC_INT_CMD_END BIT(1)
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#define AR934X_NFC_ECC_CTRL_ERR_THRES_S 8
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#define AR934X_NFC_ECC_CTRL_ERR_THRES_M 0x1f
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#define AR934X_NFC_ECC_CTRL_ECC_CAP_S 5
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#define AR934X_NFC_ECC_CTRL_ECC_CAP_M 0x7
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#define AR934X_NFC_ECC_CTRL_ECC_CAP_2 0
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#define AR934X_NFC_ECC_CTRL_ECC_CAP_4 1
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#define AR934X_NFC_ECC_CTRL_ECC_CAP_6 2
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#define AR934X_NFC_ECC_CTRL_ECC_CAP_8 3
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#define AR934X_NFC_ECC_CTRL_ECC_CAP_10 4
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#define AR934X_NFC_ECC_CTRL_ECC_CAP_12 5
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#define AR934X_NFC_ECC_CTRL_ECC_CAP_14 6
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#define AR934X_NFC_ECC_CTRL_ECC_CAP_16 7
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#define AR934X_NFC_ECC_CTRL_ERR_OVER BIT(2)
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#define AR934X_NFC_ECC_CTRL_ERR_UNCORRECT BIT(1)
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#define AR934X_NFC_ECC_CTRL_ERR_CORRECT BIT(0)
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#define AR934X_NFC_ECC_OFFS_OFSET_M 0xffff
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/* default timing values */
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#define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
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#define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
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@ -182,6 +200,11 @@ struct ar934x_nfc {
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u32 irq_status;
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u32 ctrl_reg;
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u32 ecc_ctrl_reg;
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u32 ecc_offset_reg;
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u32 ecc_thres;
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u32 ecc_oob_pos;
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bool small_page;
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unsigned int addr_count0;
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unsigned int addr_count1;
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@ -205,6 +228,16 @@ struct ar934x_nfc {
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static void ar934x_nfc_restart(struct ar934x_nfc *nfc);
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static inline bool
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is_all_ff(u8 *buf, int len)
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{
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while (len--)
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if (buf[len] != 0xff)
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return false;
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return true;
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}
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static inline void
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ar934x_nfc_wr(struct ar934x_nfc *nfc, unsigned reg, u32 val)
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{
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@ -455,6 +488,8 @@ retry:
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ar934x_nfc_wr(nfc, AR934X_NFC_REG_DATA_SIZE, len);
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ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
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ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_CTRL, dma_ctrl);
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ar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_CTRL, nfc->ecc_ctrl_reg);
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ar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_OFFSET, nfc->ecc_offset_reg);
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if (ar934x_nfc_use_irq(nfc)) {
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ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, AR934X_NFC_IRQ_MASK);
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@ -613,6 +648,7 @@ ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column,
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int page_addr)
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{
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struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
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struct nand_chip *nand = mtd->priv;
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nfc->read_id = false;
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if (command != NAND_CMD_PAGEPROG)
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@ -696,6 +732,11 @@ ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column,
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break;
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case NAND_CMD_PAGEPROG:
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if (nand->ecc.mode == NAND_ECC_HW) {
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/* the data is already written */
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break;
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}
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if (nfc->small_page)
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ar934x_nfc_send_cmd(nfc, nfc->seqin_read_cmd);
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@ -794,6 +835,206 @@ ar934x_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
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nfc->buf_index = buf_index;
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}
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static inline void
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ar934x_nfc_enable_hwecc(struct ar934x_nfc *nfc)
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{
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nfc->ctrl_reg |= AR934X_NFC_CTRL_ECC_EN;
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nfc->ctrl_reg &= ~AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
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}
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static inline void
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ar934x_nfc_disable_hwecc(struct ar934x_nfc *nfc)
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{
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nfc->ctrl_reg &= ~AR934X_NFC_CTRL_ECC_EN;
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nfc->ctrl_reg |= AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
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}
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static int
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ar934x_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
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int page)
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{
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struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
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int err;
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nfc_dbg(nfc, "read_oob: page:%d\n", page);
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err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize, page,
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mtd->oobsize);
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if (err)
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return err;
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memcpy(chip->oob_poi, nfc->buf, mtd->oobsize);
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return 0;
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}
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static int
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ar934x_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
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int page)
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{
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struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
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nfc_dbg(nfc, "write_oob: page:%d\n", page);
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memcpy(nfc->buf, chip->oob_poi, mtd->oobsize);
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return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, mtd->writesize,
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page, mtd->oobsize);
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}
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static int
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ar934x_nfc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
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u8 *buf, int oob_required, int page)
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{
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struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
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int len;
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int err;
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nfc_dbg(nfc, "read_page_raw: page:%d oob:%d\n", page, oob_required);
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len = mtd->writesize;
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if (oob_required)
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len += mtd->oobsize;
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err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page, len);
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if (err)
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return err;
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memcpy(buf, nfc->buf, mtd->writesize);
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if (oob_required)
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memcpy(chip->oob_poi, &nfc->buf[mtd->writesize], mtd->oobsize);
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return 0;
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}
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static int
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ar934x_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
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u8 *buf, int oob_required, int page)
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{
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struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
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u32 ecc_ctrl;
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int max_bitflips = 0;
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bool ecc_failed;
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bool ecc_corrected;
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int err;
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nfc_dbg(nfc, "read_page: page:%d oob:%d\n", page, oob_required);
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ar934x_nfc_enable_hwecc(nfc);
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err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page,
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mtd->writesize);
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ar934x_nfc_disable_hwecc(nfc);
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if (err)
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return err;
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/* TODO: optimize to avoid memcpy */
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memcpy(buf, nfc->buf, mtd->writesize);
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/* read the ECC status */
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ecc_ctrl = ar934x_nfc_rr(nfc, AR934X_NFC_REG_ECC_CTRL);
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ecc_failed = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_UNCORRECT;
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ecc_corrected = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_CORRECT;
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if (oob_required || ecc_failed) {
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err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize,
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page, mtd->oobsize);
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if (err)
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return err;
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if (oob_required)
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memcpy(chip->oob_poi, nfc->buf, mtd->oobsize);
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}
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if (ecc_failed) {
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/*
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* The hardware ECC engine reports uncorrectable errors
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* on empty pages. Check the ECC bytes and the data. If
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* both contains 0xff bytes only, dont report a failure.
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*
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* TODO: prebuild a buffer with 0xff bytes and use memcmp
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* for better performance?
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*/
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if (!is_all_ff(&nfc->buf[nfc->ecc_oob_pos], chip->ecc.total) ||
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!is_all_ff(buf, mtd->writesize))
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mtd->ecc_stats.failed++;
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} else if (ecc_corrected) {
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/*
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* The hardware does not report the exact count of the
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* corrected bitflips, use assumptions based on the
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* threshold.
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*/
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if (ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_OVER) {
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/*
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* The number of corrected bitflips exceeds the
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* threshold. Assume the maximum.
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*/
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max_bitflips = chip->ecc.strength * chip->ecc.steps;
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} else {
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max_bitflips = nfc->ecc_thres * chip->ecc.steps;
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}
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mtd->ecc_stats.corrected += max_bitflips;
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}
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return max_bitflips;
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}
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static int
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ar934x_nfc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
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const u8 *buf, int oob_required)
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{
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struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
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int page;
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int len;
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page = nfc->seqin_page_addr;
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nfc_dbg(nfc, "write_page_raw: page:%d oob:%d\n", page, oob_required);
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memcpy(nfc->buf, buf, mtd->writesize);
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len = mtd->writesize;
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if (oob_required) {
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memcpy(&nfc->buf[mtd->writesize], chip->oob_poi, mtd->oobsize);
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len += mtd->oobsize;
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}
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return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page, len);
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}
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static int
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ar934x_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
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const u8 *buf, int oob_required)
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{
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struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
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int page;
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int err;
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page = nfc->seqin_page_addr;
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nfc_dbg(nfc, "write_page: page:%d oob:%d\n", page, oob_required);
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/* write OOB first */
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if (oob_required &&
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!is_all_ff(chip->oob_poi, mtd->oobsize)) {
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err = ar934x_nfc_write_oob(mtd, chip, page);
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if (err)
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return err;
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}
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/* TODO: optimize to avoid memcopy */
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memcpy(nfc->buf, buf, mtd->writesize);
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ar934x_nfc_enable_hwecc(nfc);
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err = ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page,
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mtd->writesize);
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ar934x_nfc_disable_hwecc(nfc);
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return err;
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}
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static void
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ar934x_nfc_hw_init(struct ar934x_nfc *nfc)
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{
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@ -1006,6 +1247,86 @@ ar934x_nfc_init_tail(struct mtd_info *mtd)
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return err;
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}
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static struct nand_ecclayout ar934x_nfc_oob_64_hwecc = {
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.eccbytes = 28,
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.eccpos = {
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20, 21, 22, 23, 24, 25, 26,
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27, 28, 29, 30, 31, 32, 33,
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34, 35, 36, 37, 38, 39, 40,
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41, 42, 43, 44, 45, 46, 47,
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},
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.oobfree = {
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{
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.offset = 4,
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.length = 16,
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},
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{
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.offset = 48,
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.length = 16,
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},
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},
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};
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static int
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ar934x_nfc_setup_hwecc(struct ar934x_nfc *nfc)
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{
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struct nand_chip *nand = &nfc->nand_chip;
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u32 ecc_cap;
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u32 ecc_thres;
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if (!config_enabled(CONFIG_MTD_NAND_AR934X_HW_ECC)) {
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dev_err(nfc->parent, "hardware ECC support is disabled\n");
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return -EINVAL;
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}
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switch (nfc->mtd.writesize) {
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case 2048:
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nand->ecc.size = 512;
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nand->ecc.bytes = 7;
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nand->ecc.strength = 4;
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nand->ecc.layout = &ar934x_nfc_oob_64_hwecc;
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break;
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default:
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dev_err(nfc->parent,
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"hardware ECC is not available for %d byte pages\n",
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nfc->mtd.writesize);
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return -EINVAL;
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}
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BUG_ON(!nand->ecc.layout);
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switch (nand->ecc.strength) {
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case 4:
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ecc_cap = AR934X_NFC_ECC_CTRL_ECC_CAP_4;
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ecc_thres = 4;
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break;
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default:
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dev_err(nfc->parent, "unsupported ECC strength %u\n",
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nand->ecc.strength);
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return -EINVAL;
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}
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nfc->ecc_thres = ecc_thres;
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nfc->ecc_oob_pos = nand->ecc.layout->eccpos[0];
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nfc->ecc_ctrl_reg = ecc_cap << AR934X_NFC_ECC_CTRL_ECC_CAP_S;
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nfc->ecc_ctrl_reg |= ecc_thres << AR934X_NFC_ECC_CTRL_ERR_THRES_S;
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nfc->ecc_offset_reg = nfc->mtd.writesize + nfc->ecc_oob_pos;
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nand->ecc.mode = NAND_ECC_HW;
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nand->ecc.read_page = ar934x_nfc_read_page;
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nand->ecc.read_page_raw = ar934x_nfc_read_page_raw;
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nand->ecc.write_page = ar934x_nfc_write_page;
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nand->ecc.write_page_raw = ar934x_nfc_write_page_raw;
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nand->ecc.read_oob = ar934x_nfc_read_oob;
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nand->ecc.write_oob = ar934x_nfc_write_oob;
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return 0;
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}
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static int
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ar934x_nfc_probe(struct platform_device *pdev)
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{
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@ -1071,7 +1392,6 @@ ar934x_nfc_probe(struct platform_device *pdev)
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mtd->name = dev_name(&pdev->dev);
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nand->chip_delay = 25;
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nand->ecc.mode = NAND_ECC_SOFT;
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nand->dev_ready = ar934x_nfc_dev_ready;
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nand->cmdfunc = ar934x_nfc_cmdfunc;
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@ -1106,6 +1426,23 @@ ar934x_nfc_probe(struct platform_device *pdev)
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goto err_free_buf;
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}
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switch (pdata->ecc_mode) {
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case AR934X_NFC_ECC_SOFT:
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nand->ecc.mode = NAND_ECC_SOFT;
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break;
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case AR934X_NFC_ECC_HW:
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ret = ar934x_nfc_setup_hwecc(nfc);
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if (ret)
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goto err_free_buf;
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break;
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default:
|
||||
dev_err(nfc->parent, "unknown ECC mode %d\n", pdata->ecc_mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = nand_scan_tail(mtd);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "scan tail failed, err:%d\n", ret);
|
||||
|
|
|
|||
|
|
@ -17,12 +17,19 @@
|
|||
struct mtd_info;
|
||||
struct mtd_partition;
|
||||
|
||||
enum ar934x_nfc_ecc_mode {
|
||||
AR934X_NFC_ECC_SOFT = 0,
|
||||
AR934X_NFC_ECC_HW,
|
||||
};
|
||||
|
||||
struct ar934x_nfc_platform_data {
|
||||
const char *name;
|
||||
struct mtd_partition *parts;
|
||||
int nr_parts;
|
||||
|
||||
bool swap_dma;
|
||||
enum ar934x_nfc_ecc_mode ecc_mode;
|
||||
|
||||
void (*hw_reset)(bool active);
|
||||
void (*select_chip)(int chip_no);
|
||||
int (*scan_fixup)(struct mtd_info *mtd);
|
||||
|
|
|
|||
|
|
@ -1,12 +1,16 @@
|
|||
--- a/drivers/mtd/nand/Kconfig
|
||||
+++ b/drivers/mtd/nand/Kconfig
|
||||
@@ -552,4 +552,8 @@ config MTD_NAND_RB750
|
||||
@@ -552,4 +552,12 @@ config MTD_NAND_RB750
|
||||
tristate "NAND flash driver for the RouterBoard 750"
|
||||
depends on MTD_NAND && ATH79_MACH_RB750
|
||||
|
||||
+config MTD_NAND_AR934X
|
||||
+ tristate "NAND flash driver for the Qualcomm Atheros AR934x/QCA955x SoCs"
|
||||
+ depends on (SOC_AR934X || SOC_QCA955X)
|
||||
+
|
||||
+config MTD_NAND_AR934X_HW_ECC
|
||||
+ bool "Hardware ECC support for the AR934X NAND Controller (EXPERIMENTAL)"
|
||||
+ depends on MTD_NAND_AR934X
|
||||
+
|
||||
endif # MTD_NAND
|
||||
--- a/drivers/mtd/nand/Makefile
|
||||
|
|
|
|||
Loading…
Reference in a new issue