add support for arv4518 and arv752DWP22 boards
SVN-Revision: 25071
This commit is contained in:
John Crispin
parent
275c33c6f8
commit
d6f4fa08eb
23 changed files with 4001 additions and 8 deletions
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@ -27,11 +27,6 @@ config UBOOT_RAMBOOT_DDR_CONFIG
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It will be used to create a RAM boot image
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Select for Danube evalution board easy50712_DDR166M.conf .
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Select for AR9 evalution board easy50812.conf .
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config UBOOT_A800
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bool "add ARV452 Switch bringup hack"
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help
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Say Y, if you have a arv452 board (wav-281, A800, ..)
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Select for arcadyan PSC RAM board arcadyan.conf .
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endmenu
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@ -28,10 +28,9 @@ endif
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define Package/uboot-lantiq
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SECTION:=boot
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CATEGORY:=Boot Loaders
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DEPENDS:=@TARGET_ifxmips
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DEPENDS:=@TARGET_lantiq
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TITLE:=U-Boot for Lantiq reference boards
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URL:=http://www.denx.de/wiki/U-Boot
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MENU:=1
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endef
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define Build/Prepare
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141
package/uboot-lantiq/arcadyan_psc166.conf
Normal file
141
package/uboot-lantiq/arcadyan_psc166.conf
Normal file
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@ -0,0 +1,141 @@
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0xbf800060 0x7
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0xbf800010 0x0
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0xbf800020 0x0
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0xbf800200 0x02
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0xbf800210 0x0
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;REG32(MC_DC0) = 0x00001B1B;
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0xbf801000 0x1b1b
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;REG32(MC_DC1) = 0x00000000;
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0xbf801010 0x0
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;REG32(MC_DC2) = 0x00000000;
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0xbf801020 0x0
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;REG32(MC_DC3) = 0x00000000;
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0xbf801030 0x0
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;REG32(MC_DC4) = 0x00000000;
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0xbf801040 0x0
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;REG32(MC_DC5) = 0x00000200;
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0xbf801050 0x200
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;REG32(MC_DC6) = 0x00000306;
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; 0xbf801060 0x0306
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0xbf801060 0x0605
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;REG32(MC_DC7) = 0x00000303;
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; 0xbf801070 0x302
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; 0xbf801070 0x0203
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0xbf801070 0x0303
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;REG32(MC_DC8) = 0x00000102;
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0xbf801080 0x102
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;REG32(MC_DC9) = 0x0000070A;
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0xbf801090 0x70a
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; 0xbf801090 0x608
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;REG32(MC_DC10) = 0x00000203;
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0xbf8010a0 0x203
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;REG32(MC_DC11) = 0x00000C02;
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0xbf8010b0 0xc02
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; 0xbf8010b0 0x0a02
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;REG32(MC_DC12) = 0x000001C8;
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0xbf8010c0 0x1c8
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;REG32(MC_DC13) = 0x00000001;
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0xbf8010d0 0x1
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;REG32(MC_DC14) = 0x00000000;
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0xbf8010e0 0x0
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;REG32(MC_DC15) = 0x00000F5F;
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; 0xbf8010f0 0xf5f
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; 0xbf8010f0 0xf3c
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0xbf8010f0 0x130
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;REG32(MC_DC16) = 0x0000C800;
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0xbf801100 0xc800
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;REG32(MC_DC17) = 0x0000000D;
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; 0xbf801110 0xd
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0xbf801110 0xd
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;REG32(MC_DC18) = 0x00000300;
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; 0xbf801120 0x300
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0xbf801120 0x301
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;REG32(MC_DC19) = 0x00000300;
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; 0xbf801130 0x300
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0xbf801130 0x200
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;REG32(MC_DC20) = 0x00000A04;
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; 0xbf801140 0xa04
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0xbf801140 0xa03
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;REG32(MC_DC21) = 0x00001c00;
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; 0xbf801150 0xd00
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; 0xbf801150 0x1f00
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0xbf801150 0x1b00
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;REG32(MC_DC22) = 0x00001E1E;
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; 0xbf801160 0xd0d
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; 0xbf801160 0x1f1f
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0xbf801160 0x1b1b
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;REG32(MC_DC23) = 0x00000000;
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0xbf801170 0x0
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;//Disable ECC
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;REG32(MC_DC24) = 0x0000007F;
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; 0xbf801180 0x7f
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; 0xbf801180 0x062
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; 0xbf801180 0x37f
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0xbf801180 0x59
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;REG32(MC_DC25) = 0x00000000;
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0xbf801190 0x0
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;REG32(MC_DC26) = 0x00000000;
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0xbf8011a0 0x0
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;REG32(MC_DC27) = 0x00000000;
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0xbf8011b0 0x0
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;REG32(MC_DC28) = 0x00000A24;
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; 0xbf8011c0 0xa24
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0xbf8011c0 0x510
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;REG32(MC_DC29) = 0x00002D89;
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; 0xbf8011d0 0x2d89
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; 0xbf8011d0 0x2d92
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0xbf8011d0 0x4e20
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;REG32(MC_DC30) = 0x00000022;
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; 0xbf8011e0 0x8300
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0xbf8011e0 0x8235
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;REG32(MC_DC31) = 0x00000000;
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0xbf8011f0 0x0
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;REG32(MC_DC32) = 0x00000000;
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0xbf801200 0x0
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;REG32(MC_DC33) = 0x00000000;
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0xbf801210 0x0
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;REG32(MC_DC34) = 0x00000000;
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0xbf801220 0x0
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;REG32(MC_DC35) = 0x00000000;
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0xbf801230 0x0
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;REG32(MC_DC36) = 0x00000000;
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0xbf801240 0x0
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;REG32(MC_DC37) = 0x00000000;
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0xbf801250 0x0
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;REG32(MC_DC38) = 0x00000000;
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0xbf801260 0x0
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;REG32(MC_DC39) = 0x00000000;
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0xbf801270 0x0
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;REG32(MC_DC40) = 0x00000000;
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0xbf801280 0x0
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;REG32(MC_DC41) = 0x00000000;
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0xbf801290 0x0
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;REG32(MC_DC42) = 0x00000000;
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0xbf8012a0 0x0
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;REG32(MC_DC43) = 0x00000000;
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0xbf8012b0 0x0
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;REG32(MC_DC44) = 0x00000000;
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0xbf8012c0 0x0
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;REG32(MC_DC45) = 0x00000600;
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0xbf8012d0 0x500
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;REG32(MC_DC46) = 0x00000000;
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0xbf8012e0 0x0
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0xbf800060 0x05
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0xbf801030 0x100
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47
package/uboot-lantiq/files/board/arcadyan/arv4518/Makefile
Normal file
47
package/uboot-lantiq/files/board/arcadyan/arv4518/Makefile
Normal file
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@ -0,0 +1,47 @@
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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#COBJS := $(BOARD).o
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COBJS-y += arv4518.o
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SOBJS = lowlevel_init.o pmuenable.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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334
package/uboot-lantiq/files/board/arcadyan/arv4518/arv4518.c
Normal file
334
package/uboot-lantiq/files/board/arcadyan/arv4518/arv4518.c
Normal file
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@ -0,0 +1,334 @@
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/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2010
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* Thomas Langer, Ralph Hempel
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <asm/addrspace.h>
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#include <asm/danube.h>
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#include <asm/reboot.h>
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#include <asm/io.h>
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#if defined(CONFIG_CMD_HTTPD)
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#include <httpd.h>
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#endif
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#if defined(CONFIG_PCI)
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#include <pci.h>
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#endif
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extern ulong ifx_get_ddr_hz(void);
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extern ulong ifx_get_cpuclk(void);
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/* IDs and registers of known external switches */
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#define ID_RTL8306 0x5988
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#define CONFIG_EXTRA_SWITCH 1
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void _machine_restart(void)
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{
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*DANUBE_RCU_RST_REQ |=1<<30;
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}
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#ifdef CONFIG_SYS_RAMBOOT
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phys_size_t initdram(int board_type)
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{
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return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
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}
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#elif defined(CONFIG_USE_DDR_RAM)
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phys_size_t initdram(int board_type)
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{
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return (CONFIG_SYS_MAX_RAM);
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}
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#else
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static ulong max_sdram_size(void) /* per Chip Select */
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{
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/* The only supported SDRAM data width is 16bit.
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*/
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#define CFG_DW 4
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/* The only supported number of SDRAM banks is 4.
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*/
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#define CFG_NB 4
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ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
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int cols = cfgpb0 & 0xF;
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int rows = (cfgpb0 & 0xF0) >> 4;
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ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
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return size;
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}
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'.
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*/
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static long int dram_size(long int *base, long int maxsize)
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{
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volatile long int *addr;
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ulong cnt, val;
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ulong save[32]; /* to make test non-destructive */
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unsigned char i = 0;
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for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
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addr = base + cnt; /* pointer arith! */
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save[i++] = *addr;
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*addr = ~cnt;
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}
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/* write 0 to base address */
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addr = base;
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save[i] = *addr;
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*addr = 0;
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/* check at base address */
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if ((val = *addr) != 0) {
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*addr = save[i];
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return (0);
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}
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for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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val = *addr;
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*addr = save[--i];
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if (val != (~cnt)) {
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return (cnt * sizeof (long));
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}
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}
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return (maxsize);
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}
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phys_size_t initdram(int board_type)
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{
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int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
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ulong size, max_size = 0;
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ulong our_address;
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/* load t9 into our_address */
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asm volatile ("move %0, $25" : "=r" (our_address) :);
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/* Can't probe for RAM size unless we are running from Flash.
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* find out whether running from DRAM or Flash.
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*/
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if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
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{
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return max_sdram_size();
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}
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for (cols = 0x8; cols <= 0xC; cols++)
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{
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for (rows = 0xB; rows <= 0xD; rows++)
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{
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*DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
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(rows << 4) | cols;
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size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
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max_sdram_size());
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if (size > max_size)
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{
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best_val = *DANUBE_SDRAM_MC_CFGPB0;
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max_size = size;
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}
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}
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}
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*DANUBE_SDRAM_MC_CFGPB0 = best_val;
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return max_size;
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}
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#endif
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int checkboard (void)
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{
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unsigned long chipid = *DANUBE_MPS_CHIPID;
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int part_num;
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puts ("Board: ");
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part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
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switch (part_num)
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{
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case 0x129:
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case 0x12D:
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case 0x12b:
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puts("Danube/Twinpass/Vinax-VE ");
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break;
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default:
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printf ("unknown, chip part number 0x%03X ", part_num);
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break;
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}
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printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
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printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
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printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
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return 0;
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}
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT
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int board_early_init_f(void)
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{
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#ifdef CONFIG_EBU_ADDSEL0
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(*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
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#endif
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#ifdef CONFIG_EBU_ADDSEL1
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(*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
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#endif
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#ifdef CONFIG_EBU_ADDSEL2
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(*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
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#endif
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#ifdef CONFIG_EBU_ADDSEL3
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(*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
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#endif
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#ifdef CONFIG_EBU_BUSCON0
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(*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
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#endif
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#ifdef CONFIG_EBU_BUSCON1
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(*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
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#endif
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#ifdef CONFIG_EBU_BUSCON2
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(*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
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#endif
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#ifdef CONFIG_EBU_BUSCON3
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(*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
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#endif
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return 0;
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}
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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#ifdef CONFIG_EXTRA_SWITCH
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static int external_switch_init(void)
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{
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unsigned short chipid;
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static char * const name = "lq_cpe_eth";
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/* earlier no valid response is available, at least on Twinpass & Tantos @ 111MHz, M4530 platform */
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udelay(100000);
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puts("\nsearching for rtl8306 switch ... ");
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if (miiphy_read(name, 4, 30, &chipid) == 0) {
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puts("s1\n");
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if (chipid == ID_RTL8306) {
|
||||
puts("found");
|
||||
/* set led mode */
|
||||
miiphy_write(name, 0, 19, 0xffff);
|
||||
/* magic */
|
||||
miiphy_write(name, 4, 22, 0x877f);
|
||||
puts("\n");
|
||||
return 0;
|
||||
}
|
||||
puts("failed\n");
|
||||
}
|
||||
puts("\nno known switch found ... \n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_EXTRA_SWITCH */
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#if defined(CONFIG_IFX_ETOP)
|
||||
uchar enetaddr[6];
|
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr))
|
||||
eth_setenv_enetaddr("ethaddr", (uchar *)0xb03f0016);
|
||||
|
||||
*DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
|
||||
*DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
|
||||
|
||||
if (lq_eth_initialize(bis))
|
||||
return -1;
|
||||
|
||||
*DANUBE_RCU_RST_REQ |=1;
|
||||
udelay(200000);
|
||||
*DANUBE_RCU_RST_REQ &=(unsigned long)~1;
|
||||
udelay(1000);
|
||||
|
||||
#ifdef CONFIG_EXTRA_SWITCH
|
||||
if (external_switch_init()<0)
|
||||
return -1;
|
||||
#endif /* CONFIG_EXTRA_SWITCH */
|
||||
#endif /* CONFIG_IFX_ETOP */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_HTTPD)
|
||||
int do_http_upgrade(const unsigned char *data, const ulong size)
|
||||
{
|
||||
char buf[128];
|
||||
|
||||
if(getenv ("ram_addr") == NULL)
|
||||
return -1;
|
||||
if(getenv ("kernel_addr") == NULL)
|
||||
return -1;
|
||||
/* check the image */
|
||||
if(run_command("imi ${ram_addr}", 0) < 0) {
|
||||
return -1;
|
||||
}
|
||||
/* write the image to the flash */
|
||||
puts("http ugrade ...\n");
|
||||
sprintf(buf, "era ${kernel_addr} +0x%lx; cp.b ${ram_addr} ${kernel_addr} 0x%lx", size, size);
|
||||
return run_command(buf, 0);
|
||||
}
|
||||
|
||||
int do_http_progress(const int state)
|
||||
{
|
||||
/* toggle LED's here */
|
||||
switch(state) {
|
||||
case HTTP_PROGRESS_START:
|
||||
puts("http start\n");
|
||||
break;
|
||||
case HTTP_PROGRESS_TIMEOUT:
|
||||
puts(".");
|
||||
break;
|
||||
case HTTP_PROGRESS_UPLOAD_READY:
|
||||
puts("http upload ready\n");
|
||||
break;
|
||||
case HTTP_PROGRESS_UGRADE_READY:
|
||||
puts("http ugrade ready\n");
|
||||
break;
|
||||
case HTTP_PROGRESS_UGRADE_FAILED:
|
||||
puts("http ugrade failed\n");
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long do_http_tmp_address(void)
|
||||
{
|
||||
char *s = getenv ("ram_addr");
|
||||
if (s) {
|
||||
ulong tmp = simple_strtoul (s, NULL, 16);
|
||||
return tmp;
|
||||
}
|
||||
return 0 /*0x80a00000*/;
|
||||
}
|
||||
|
||||
#endif
|
||||
60
package/uboot-lantiq/files/board/arcadyan/arv4518/config.mk
Normal file
60
package/uboot-lantiq/files/board/arcadyan/arv4518/config.mk
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
#
|
||||
# (C) Copyright 2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# Danube board with MIPS 24Kc CPU core
|
||||
#
|
||||
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
|
||||
|
||||
ifdef CONFIG_LZMA_BOOTSTRAP
|
||||
|
||||
ifdef BUILD_BOOTSTRAP
|
||||
|
||||
$(info BUILD_BOOTSTRAP )
|
||||
#TEXT_BASE = 0xB0000000
|
||||
TEXT_BASE = 0x80010000
|
||||
|
||||
else # BUILD_BOOTSTRAP
|
||||
|
||||
ifndef TEXT_BASE
|
||||
$(info redefine TEXT_BASE = 0x80040000 )
|
||||
TEXT_BASE = 0x80040000
|
||||
endif
|
||||
|
||||
endif # BUILD_BOOTSTRAP
|
||||
|
||||
else
|
||||
|
||||
ifdef BUILD_BOOTSTRAP
|
||||
$(error BUILD_BOOTSTRAP but not enabled in config)
|
||||
endif
|
||||
|
||||
ifndef TEXT_BASE
|
||||
## Standard: boot from ebu
|
||||
$(info redefine TEXT_BASE = 0xB0000000 )
|
||||
TEXT_BASE = 0xB0000000
|
||||
## For testing: boot from RAM
|
||||
# TEXT_BASE = 0x80100000
|
||||
endif
|
||||
|
||||
endif # CONFIG_LZMA_BOOTSTRAP
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/* Settings for Denali DDR SDRAM controller */
|
||||
/* Optimise for DDR PSC A3S12D40ETP for arv4518pw Danube Board DDR 166 Mhz - by Ngp 14th Sept. 2010 */
|
||||
|
||||
#define MC_DC0_VALUE 0x1B1B
|
||||
#define MC_DC1_VALUE 0x0
|
||||
#define MC_DC2_VALUE 0x0
|
||||
#define MC_DC3_VALUE 0x0
|
||||
#define MC_DC4_VALUE 0x0
|
||||
#define MC_DC5_VALUE 0x200
|
||||
#define MC_DC6_VALUE 0x605
|
||||
#define MC_DC7_VALUE 0x303
|
||||
#define MC_DC8_VALUE 0x102
|
||||
#define MC_DC9_VALUE 0x70a
|
||||
#define MC_DC10_VALUE 0x203
|
||||
#define MC_DC11_VALUE 0xc02
|
||||
#define MC_DC12_VALUE 0x1C8
|
||||
#define MC_DC13_VALUE 0x1
|
||||
#define MC_DC14_VALUE 0x0
|
||||
#define MC_DC15_VALUE 0x130 /* WDQS tuning for clk_wr*/
|
||||
#define MC_DC16_VALUE 0xC800
|
||||
#define MC_DC17_VALUE 0xd
|
||||
#define MC_DC18_VALUE 0x301
|
||||
#define MC_DC19_VALUE 0x200
|
||||
#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
|
||||
#define MC_DC21_VALUE 0x1b00
|
||||
#define MC_DC22_VALUE 0x1b1b
|
||||
#define MC_DC23_VALUE 0x0
|
||||
#define MC_DC24_VALUE 0x59 /* WDQS Tuning for DQS */
|
||||
#define MC_DC25_VALUE 0x0
|
||||
#define MC_DC26_VALUE 0x0
|
||||
#define MC_DC27_VALUE 0x0
|
||||
#define MC_DC28_VALUE 0x510
|
||||
#define MC_DC29_VALUE 0x4e20
|
||||
#define MC_DC30_VALUE 0x8235
|
||||
#define MC_DC31_VALUE 0x0
|
||||
#define MC_DC32_VALUE 0x0
|
||||
#define MC_DC33_VALUE 0x0
|
||||
#define MC_DC34_VALUE 0x0
|
||||
#define MC_DC35_VALUE 0x0
|
||||
#define MC_DC36_VALUE 0x0
|
||||
#define MC_DC37_VALUE 0x0
|
||||
#define MC_DC38_VALUE 0x0
|
||||
#define MC_DC39_VALUE 0x0
|
||||
#define MC_DC40_VALUE 0x0
|
||||
#define MC_DC41_VALUE 0x0
|
||||
#define MC_DC42_VALUE 0x0
|
||||
#define MC_DC43_VALUE 0x0
|
||||
#define MC_DC44_VALUE 0x0
|
||||
#define MC_DC45_VALUE 0x500
|
||||
#define MC_DC46_VALUE 0x0
|
||||
|
|
@ -0,0 +1,622 @@
|
|||
/*
|
||||
* Memory sub-system initialization code for Danube board.
|
||||
* Andre Messerschmidt
|
||||
* Copyright (c) 2005 Infineon Technologies AG
|
||||
*
|
||||
* Based on Inca-IP code
|
||||
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
/* History:
|
||||
peng liu May 25, 2006, for PLL setting after reset, 05252006
|
||||
*/
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/regdef.h>
|
||||
|
||||
#if 0
|
||||
|
||||
#if defined(CONFIG_USE_DDR_RAM)
|
||||
|
||||
#if defined(CONFIG_USE_DDR_RAM_CFG_111M)
|
||||
#include "ddr_settings_r111.h"
|
||||
#define DDR111
|
||||
#elif defined(CONFIG_USE_DDR_RAM_CFG_166M)
|
||||
#include "ddr_settings_r166.h"
|
||||
#define DDR166
|
||||
#elif defined(CONFIG_USE_DDR_RAM_CFG_e111M)
|
||||
#include "ddr_settings_e111.h"
|
||||
#define DDR111
|
||||
#elif defined(CONFIG_USE_DDR_RAM_CFG_e166M)
|
||||
#include "ddr_settings_e166.h"
|
||||
#define DDR166
|
||||
#elif defined(CONFIG_USE_DDR_RAM_CFG_promos400)
|
||||
#include "ddr_settings_PROMOSDDR400.h"
|
||||
#define DDR166
|
||||
#elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166)
|
||||
#include "ddr_settings_Samsung_166.h"
|
||||
#define DDR166
|
||||
#elif defined(CONFIG_USE_DDR_RAM_CFG_psc166)
|
||||
#include "ddr_settings_psc_166.h"
|
||||
#define DDR166
|
||||
#else
|
||||
#warning "missing definition for ddr_settings.h, use default!"
|
||||
#include "ddr_settings.h"
|
||||
#endif
|
||||
#endif /* CONFIG_USE_DDR_RAM */
|
||||
|
||||
#else
|
||||
|
||||
#include "ddr_settings.h"
|
||||
#define DDR166
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE)
|
||||
#error "missing include of ddr_settings.h"
|
||||
#endif
|
||||
|
||||
#define EBU_MODUL_BASE 0xBE105300
|
||||
#define EBU_CLC(value) 0x0000(value)
|
||||
#define EBU_CON(value) 0x0010(value)
|
||||
#define EBU_ADDSEL0(value) 0x0020(value)
|
||||
#define EBU_ADDSEL1(value) 0x0024(value)
|
||||
#define EBU_ADDSEL2(value) 0x0028(value)
|
||||
#define EBU_ADDSEL3(value) 0x002C(value)
|
||||
#define EBU_BUSCON0(value) 0x0060(value)
|
||||
#define EBU_BUSCON1(value) 0x0064(value)
|
||||
#define EBU_BUSCON2(value) 0x0068(value)
|
||||
#define EBU_BUSCON3(value) 0x006C(value)
|
||||
|
||||
#define MC_MODUL_BASE 0xBF800000
|
||||
#define MC_ERRCAUSE(value) 0x0010(value)
|
||||
#define MC_ERRADDR(value) 0x0020(value)
|
||||
#define MC_CON(value) 0x0060(value)
|
||||
|
||||
#define MC_SRAM_ENABLE 0x00000004
|
||||
#define MC_SDRAM_ENABLE 0x00000002
|
||||
#define MC_DDRRAM_ENABLE 0x00000001
|
||||
|
||||
#define MC_SDR_MODUL_BASE 0xBF800200
|
||||
#define MC_IOGP(value) 0x0000(value)
|
||||
#define MC_CTRLENA(value) 0x0010(value)
|
||||
#define MC_MRSCODE(value) 0x0020(value)
|
||||
#define MC_CFGDW(value) 0x0030(value)
|
||||
#define MC_CFGPB0(value) 0x0040(value)
|
||||
#define MC_LATENCY(value) 0x0080(value)
|
||||
#define MC_TREFRESH(value) 0x0090(value)
|
||||
#define MC_SELFRFSH(value) 0x00A0(value)
|
||||
|
||||
#define MC_DDR_MODUL_BASE 0xBF801000
|
||||
#define MC_DC00(value) 0x0000(value)
|
||||
#define MC_DC01(value) 0x0010(value)
|
||||
#define MC_DC02(value) 0x0020(value)
|
||||
#define MC_DC03(value) 0x0030(value)
|
||||
#define MC_DC04(value) 0x0040(value)
|
||||
#define MC_DC05(value) 0x0050(value)
|
||||
#define MC_DC06(value) 0x0060(value)
|
||||
#define MC_DC07(value) 0x0070(value)
|
||||
#define MC_DC08(value) 0x0080(value)
|
||||
#define MC_DC09(value) 0x0090(value)
|
||||
#define MC_DC10(value) 0x00A0(value)
|
||||
#define MC_DC11(value) 0x00B0(value)
|
||||
#define MC_DC12(value) 0x00C0(value)
|
||||
#define MC_DC13(value) 0x00D0(value)
|
||||
#define MC_DC14(value) 0x00E0(value)
|
||||
#define MC_DC15(value) 0x00F0(value)
|
||||
#define MC_DC16(value) 0x0100(value)
|
||||
#define MC_DC17(value) 0x0110(value)
|
||||
#define MC_DC18(value) 0x0120(value)
|
||||
#define MC_DC19(value) 0x0130(value)
|
||||
#define MC_DC20(value) 0x0140(value)
|
||||
#define MC_DC21(value) 0x0150(value)
|
||||
#define MC_DC22(value) 0x0160(value)
|
||||
#define MC_DC23(value) 0x0170(value)
|
||||
#define MC_DC24(value) 0x0180(value)
|
||||
#define MC_DC25(value) 0x0190(value)
|
||||
#define MC_DC26(value) 0x01A0(value)
|
||||
#define MC_DC27(value) 0x01B0(value)
|
||||
#define MC_DC28(value) 0x01C0(value)
|
||||
#define MC_DC29(value) 0x01D0(value)
|
||||
#define MC_DC30(value) 0x01E0(value)
|
||||
#define MC_DC31(value) 0x01F0(value)
|
||||
#define MC_DC32(value) 0x0200(value)
|
||||
#define MC_DC33(value) 0x0210(value)
|
||||
#define MC_DC34(value) 0x0220(value)
|
||||
#define MC_DC35(value) 0x0230(value)
|
||||
#define MC_DC36(value) 0x0240(value)
|
||||
#define MC_DC37(value) 0x0250(value)
|
||||
#define MC_DC38(value) 0x0260(value)
|
||||
#define MC_DC39(value) 0x0270(value)
|
||||
#define MC_DC40(value) 0x0280(value)
|
||||
#define MC_DC41(value) 0x0290(value)
|
||||
#define MC_DC42(value) 0x02A0(value)
|
||||
#define MC_DC43(value) 0x02B0(value)
|
||||
#define MC_DC44(value) 0x02C0(value)
|
||||
#define MC_DC45(value) 0x02D0(value)
|
||||
#define MC_DC46(value) 0x02E0(value)
|
||||
|
||||
#define RCU_OFFSET 0xBF203000
|
||||
#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
|
||||
#define RCU_STS (RCU_OFFSET + 0x0014)
|
||||
|
||||
#define CGU_OFFSET 0xBF103000
|
||||
#define PLL0_CFG (CGU_OFFSET + 0x0004)
|
||||
#define PLL1_CFG (CGU_OFFSET + 0x0008)
|
||||
#define PLL2_CFG (CGU_OFFSET + 0x000C)
|
||||
#define CGU_SYS (CGU_OFFSET + 0x0010)
|
||||
#define CGU_UPDATE (CGU_OFFSET + 0x0014)
|
||||
#define IF_CLK (CGU_OFFSET + 0x0018)
|
||||
#define CGU_SMD (CGU_OFFSET + 0x0020)
|
||||
#define CGU_CT1SR (CGU_OFFSET + 0x0028)
|
||||
#define CGU_CT2SR (CGU_OFFSET + 0x002C)
|
||||
#define CGU_PCMCR (CGU_OFFSET + 0x0030)
|
||||
#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
|
||||
#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
|
||||
#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
|
||||
#define CLK_MEASURE (CGU_OFFSET + 0x003C)
|
||||
|
||||
//05252006
|
||||
#define pll0_35MHz_CONFIG 0x9D861059
|
||||
#define pll1_35MHz_CONFIG 0x1A260CD9
|
||||
#define pll2_35MHz_CONFIG 0x8000f1e5
|
||||
#define pll0_36MHz_CONFIG 0x1000125D
|
||||
#define pll1_36MHz_CONFIG 0x1B1E0C99
|
||||
#define pll2_36MHz_CONFIG 0x8002f2a1
|
||||
//05252006
|
||||
|
||||
//06063001-joelin disable the PCI CFRAME mask -start
|
||||
/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
|
||||
But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
|
||||
|
||||
The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
|
||||
The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
|
||||
*/
|
||||
#define PCI_CR_PR_OFFSET 0xBE105400
|
||||
#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
|
||||
#define PCI_CONFIG_SPACE 0xB7000000
|
||||
#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
|
||||
//06063001-joelin disable the PCI CFRAME mask -end
|
||||
.set noreorder
|
||||
|
||||
|
||||
/*
|
||||
* void ebu_init(void)
|
||||
*/
|
||||
.globl ebu_init
|
||||
.ent ebu_init
|
||||
ebu_init:
|
||||
|
||||
#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
|
||||
defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
|
||||
defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
|
||||
defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
|
||||
|
||||
li t1, EBU_MODUL_BASE
|
||||
#if defined(CONFIG_EBU_ADDSEL0)
|
||||
li t2, CONFIG_EBU_ADDSEL0
|
||||
sw t2, EBU_ADDSEL0(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_ADDSEL1)
|
||||
li t2, CONFIG_EBU_ADDSEL1
|
||||
sw t2, EBU_ADDSEL1(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_ADDSEL2)
|
||||
li t2, CONFIG_EBU_ADDSEL2
|
||||
sw t2, EBU_ADDSEL2(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_ADDSEL3)
|
||||
li t2, CONFIG_EBU_ADDSEL3
|
||||
sw t2, EBU_ADDSEL3(t1)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_EBU_BUSCON0)
|
||||
li t2, CONFIG_EBU_BUSCON0
|
||||
sw t2, EBU_BUSCON0(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_BUSCON1)
|
||||
li t2, CONFIG_EBU_BUSCON1
|
||||
sw t2, EBU_BUSCON1(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_BUSCON2)
|
||||
li t2, CONFIG_EBU_BUSCON2
|
||||
sw t2, EBU_BUSCON2(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_BUSCON3)
|
||||
li t2, CONFIG_EBU_BUSCON3
|
||||
sw t2, EBU_BUSCON3(t1)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end ebu_init
|
||||
|
||||
|
||||
/*
|
||||
* void cgu_init(long)
|
||||
*
|
||||
* a0 has the clock value
|
||||
*/
|
||||
.globl cgu_init
|
||||
.ent cgu_init
|
||||
cgu_init:
|
||||
li t2, CGU_SYS
|
||||
lw t2,0(t2)
|
||||
beq t2,a0,freq_up2date
|
||||
nop
|
||||
|
||||
li t2, RCU_STS
|
||||
lw t2, 0(t2)
|
||||
and t2,0x00020000
|
||||
beq t2,0x00020000,boot_36MHZ
|
||||
nop
|
||||
//05252006
|
||||
li t1, PLL0_CFG
|
||||
li t2, pll0_35MHz_CONFIG
|
||||
sw t2,0(t1)
|
||||
li t1, PLL1_CFG
|
||||
li t2, pll1_35MHz_CONFIG
|
||||
sw t2,0(t1)
|
||||
li t1, PLL2_CFG
|
||||
li t2, pll2_35MHz_CONFIG
|
||||
sw t2,0(t1)
|
||||
li t1, CGU_SYS
|
||||
sw a0,0(t1)
|
||||
li t1, RCU_RST_REQ
|
||||
li t2, 0x40000008
|
||||
sw t2,0(t1)
|
||||
b wait_reset
|
||||
nop
|
||||
boot_36MHZ:
|
||||
li t1, PLL0_CFG
|
||||
li t2, pll0_36MHz_CONFIG
|
||||
sw t2,0(t1)
|
||||
li t1, PLL1_CFG
|
||||
li t2, pll1_36MHz_CONFIG
|
||||
sw t2,0(t1)
|
||||
li t1, PLL2_CFG
|
||||
li t2, pll2_36MHz_CONFIG
|
||||
sw t2,0(t1)
|
||||
li t1, CGU_SYS
|
||||
sw a0,0(t1)
|
||||
li t1, RCU_RST_REQ
|
||||
li t2, 0x40000008
|
||||
sw t2,0(t1)
|
||||
//05252006
|
||||
|
||||
wait_reset:
|
||||
b wait_reset
|
||||
nop
|
||||
freq_up2date:
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end cgu_init
|
||||
|
||||
#ifndef CONFIG_USE_DDR_RAM
|
||||
/*
|
||||
* void sdram_init(long)
|
||||
*
|
||||
* a0 has the clock value
|
||||
*/
|
||||
.globl sdram_init
|
||||
.ent sdram_init
|
||||
sdram_init:
|
||||
|
||||
/* SDRAM Initialization
|
||||
*/
|
||||
li t1, MC_MODUL_BASE
|
||||
|
||||
/* Clear Error log registers */
|
||||
sw zero, MC_ERRCAUSE(t1)
|
||||
sw zero, MC_ERRADDR(t1)
|
||||
|
||||
/* Enable SDRAM module in memory controller */
|
||||
li t3, MC_SDRAM_ENABLE
|
||||
lw t2, MC_CON(t1)
|
||||
or t3, t2, t3
|
||||
sw t3, MC_CON(t1)
|
||||
|
||||
li t1, MC_SDR_MODUL_BASE
|
||||
|
||||
/* disable the controller */
|
||||
li t2, 0
|
||||
sw t2, MC_CTRLENA(t1)
|
||||
|
||||
li t2, 0x822
|
||||
sw t2, MC_IOGP(t1)
|
||||
|
||||
li t2, 0x2
|
||||
sw t2, MC_CFGDW(t1)
|
||||
|
||||
/* Set CAS Latency */
|
||||
li t2, 0x00000020
|
||||
sw t2, MC_MRSCODE(t1)
|
||||
|
||||
/* Set CS0 to SDRAM parameters */
|
||||
li t2, 0x000014d8
|
||||
sw t2, MC_CFGPB0(t1)
|
||||
|
||||
/* Set SDRAM latency parameters */
|
||||
li t2, 0x00036325; /* BC PC100 */
|
||||
sw t2, MC_LATENCY(t1)
|
||||
|
||||
/* Set SDRAM refresh rate */
|
||||
li t2, 0x00000C30
|
||||
sw t2, MC_TREFRESH(t1)
|
||||
|
||||
/* Clear Power-down registers */
|
||||
sw zero, MC_SELFRFSH(t1)
|
||||
|
||||
/* Finally enable the controller */
|
||||
li t2, 1
|
||||
sw t2, MC_CTRLENA(t1)
|
||||
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end sdram_init
|
||||
|
||||
#endif /* !CONFIG_USE_DDR_RAM */
|
||||
|
||||
#ifdef CONFIG_USE_DDR_RAM
|
||||
/*
|
||||
* void ddrram_init(long)
|
||||
*
|
||||
* a0 has the clock value
|
||||
*/
|
||||
.globl ddrram_init
|
||||
.ent ddrram_init
|
||||
ddrram_init:
|
||||
|
||||
/* DDR-DRAM Initialization
|
||||
*/
|
||||
li t1, MC_MODUL_BASE
|
||||
|
||||
/* Clear Error log registers */
|
||||
sw zero, MC_ERRCAUSE(t1)
|
||||
sw zero, MC_ERRADDR(t1)
|
||||
|
||||
/* Enable DDR module in memory controller */
|
||||
li t3, MC_DDRRAM_ENABLE
|
||||
lw t2, MC_CON(t1)
|
||||
or t3, t2, t3
|
||||
sw t3, MC_CON(t1)
|
||||
|
||||
li t1, MC_DDR_MODUL_BASE
|
||||
|
||||
/* Write configuration to DDR controller registers */
|
||||
li t2, MC_DC0_VALUE
|
||||
sw t2, MC_DC00(t1)
|
||||
|
||||
li t2, MC_DC1_VALUE
|
||||
sw t2, MC_DC01(t1)
|
||||
|
||||
li t2, MC_DC2_VALUE
|
||||
sw t2, MC_DC02(t1)
|
||||
|
||||
li t2, MC_DC3_VALUE
|
||||
sw t2, MC_DC03(t1)
|
||||
|
||||
li t2, MC_DC4_VALUE
|
||||
sw t2, MC_DC04(t1)
|
||||
|
||||
li t2, MC_DC5_VALUE
|
||||
sw t2, MC_DC05(t1)
|
||||
|
||||
li t2, MC_DC6_VALUE
|
||||
sw t2, MC_DC06(t1)
|
||||
|
||||
li t2, MC_DC7_VALUE
|
||||
sw t2, MC_DC07(t1)
|
||||
|
||||
li t2, MC_DC8_VALUE
|
||||
sw t2, MC_DC08(t1)
|
||||
|
||||
li t2, MC_DC9_VALUE
|
||||
sw t2, MC_DC09(t1)
|
||||
|
||||
li t2, MC_DC10_VALUE
|
||||
sw t2, MC_DC10(t1)
|
||||
|
||||
li t2, MC_DC11_VALUE
|
||||
sw t2, MC_DC11(t1)
|
||||
|
||||
li t2, MC_DC12_VALUE
|
||||
sw t2, MC_DC12(t1)
|
||||
|
||||
li t2, MC_DC13_VALUE
|
||||
sw t2, MC_DC13(t1)
|
||||
|
||||
li t2, MC_DC14_VALUE
|
||||
sw t2, MC_DC14(t1)
|
||||
|
||||
li t2, MC_DC15_VALUE
|
||||
sw t2, MC_DC15(t1)
|
||||
|
||||
li t2, MC_DC16_VALUE
|
||||
sw t2, MC_DC16(t1)
|
||||
|
||||
li t2, MC_DC17_VALUE
|
||||
sw t2, MC_DC17(t1)
|
||||
|
||||
li t2, MC_DC18_VALUE
|
||||
sw t2, MC_DC18(t1)
|
||||
|
||||
li t2, MC_DC19_VALUE
|
||||
sw t2, MC_DC19(t1)
|
||||
|
||||
li t2, MC_DC20_VALUE
|
||||
sw t2, MC_DC20(t1)
|
||||
|
||||
li t2, MC_DC21_VALUE
|
||||
sw t2, MC_DC21(t1)
|
||||
|
||||
li t2, MC_DC22_VALUE
|
||||
sw t2, MC_DC22(t1)
|
||||
|
||||
li t2, MC_DC23_VALUE
|
||||
sw t2, MC_DC23(t1)
|
||||
|
||||
li t2, MC_DC24_VALUE
|
||||
sw t2, MC_DC24(t1)
|
||||
|
||||
li t2, MC_DC25_VALUE
|
||||
sw t2, MC_DC25(t1)
|
||||
|
||||
li t2, MC_DC26_VALUE
|
||||
sw t2, MC_DC26(t1)
|
||||
|
||||
li t2, MC_DC27_VALUE
|
||||
sw t2, MC_DC27(t1)
|
||||
|
||||
li t2, MC_DC28_VALUE
|
||||
sw t2, MC_DC28(t1)
|
||||
|
||||
li t2, MC_DC29_VALUE
|
||||
sw t2, MC_DC29(t1)
|
||||
|
||||
li t2, MC_DC30_VALUE
|
||||
sw t2, MC_DC30(t1)
|
||||
|
||||
li t2, MC_DC31_VALUE
|
||||
sw t2, MC_DC31(t1)
|
||||
|
||||
li t2, MC_DC32_VALUE
|
||||
sw t2, MC_DC32(t1)
|
||||
|
||||
li t2, MC_DC33_VALUE
|
||||
sw t2, MC_DC33(t1)
|
||||
|
||||
li t2, MC_DC34_VALUE
|
||||
sw t2, MC_DC34(t1)
|
||||
|
||||
li t2, MC_DC35_VALUE
|
||||
sw t2, MC_DC35(t1)
|
||||
|
||||
li t2, MC_DC36_VALUE
|
||||
sw t2, MC_DC36(t1)
|
||||
|
||||
li t2, MC_DC37_VALUE
|
||||
sw t2, MC_DC37(t1)
|
||||
|
||||
li t2, MC_DC38_VALUE
|
||||
sw t2, MC_DC38(t1)
|
||||
|
||||
li t2, MC_DC39_VALUE
|
||||
sw t2, MC_DC39(t1)
|
||||
|
||||
li t2, MC_DC40_VALUE
|
||||
sw t2, MC_DC40(t1)
|
||||
|
||||
li t2, MC_DC41_VALUE
|
||||
sw t2, MC_DC41(t1)
|
||||
|
||||
li t2, MC_DC42_VALUE
|
||||
sw t2, MC_DC42(t1)
|
||||
|
||||
li t2, MC_DC43_VALUE
|
||||
sw t2, MC_DC43(t1)
|
||||
|
||||
li t2, MC_DC44_VALUE
|
||||
sw t2, MC_DC44(t1)
|
||||
|
||||
li t2, MC_DC45_VALUE
|
||||
sw t2, MC_DC45(t1)
|
||||
|
||||
li t2, MC_DC46_VALUE
|
||||
sw t2, MC_DC46(t1)
|
||||
|
||||
li t2, 0x00000100
|
||||
sw t2, MC_DC03(t1)
|
||||
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end ddrram_init
|
||||
#endif /* CONFIG_USE_DDR_RAM */
|
||||
|
||||
.globl lowlevel_init
|
||||
.ent lowlevel_init
|
||||
lowlevel_init:
|
||||
/* EBU, CGU and SDRAM/DDR-RAM Initialization.
|
||||
*/
|
||||
move t0, ra
|
||||
/* We rely on the fact that non of the following ..._init() functions
|
||||
* modify t0
|
||||
*/
|
||||
#if defined(CONFIG_SYS_EBU_BOOT)
|
||||
#if defined(DDR166)
|
||||
/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
|
||||
li a0,0xe8
|
||||
#elif defined(DDR133)
|
||||
/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
|
||||
li a0,0xe9
|
||||
#else /* defined(DDR111) */
|
||||
/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
|
||||
li a0,0xea
|
||||
#endif
|
||||
bal cgu_init
|
||||
nop
|
||||
#endif /* CONFIG_SYS_EBU_BOOT */
|
||||
|
||||
bal ebu_init
|
||||
nop
|
||||
|
||||
//06063001-joelin disable the PCI CFRAME mask-start
|
||||
#ifdef DISABLE_CFRAME
|
||||
li t1, PCI_CR_PCI //mw bf103034 80000000
|
||||
li t2, 0x80000000
|
||||
sw t2,0(t1)
|
||||
|
||||
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
|
||||
li t2, 0x103
|
||||
sw t2,0(t1)
|
||||
|
||||
li t1, CS_CFM //mw b700006c 0
|
||||
li t2, 0x00
|
||||
sw t2, 0(t1)
|
||||
|
||||
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
|
||||
li t2, 0x1000103
|
||||
sw t2, 0(t1)
|
||||
#endif
|
||||
//06063001-joelin disable the PCI CFRAME mask-end
|
||||
|
||||
#ifdef CONFIG_SYS_EBU_BOOT
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
#ifdef CONFIG_USE_DDR_RAM
|
||||
bal ddrram_init
|
||||
nop
|
||||
#else
|
||||
bal sdram_init
|
||||
nop
|
||||
#endif
|
||||
#endif /* CONFIG_SYS_RAMBOOT */
|
||||
#endif /* CONFIG_SYS_EBU_BOOT */
|
||||
|
||||
move ra, t0
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end lowlevel_init
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Power Management unit initialization code for AMAZON development board.
|
||||
*
|
||||
* Copyright (c) 2003 Ou Ke, Infineon.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/regdef.h>
|
||||
|
||||
#define PMU_PWDCR 0xBF10201C
|
||||
#define PMU_SR 0xBF102020
|
||||
|
||||
.globl pmuenable
|
||||
|
||||
pmuenable:
|
||||
li t0, PMU_PWDCR
|
||||
li t1, 0x2 /* enable everything */
|
||||
sw t1, 0(t0)
|
||||
#if 0
|
||||
1:
|
||||
li t0, PMU_SR
|
||||
lw t2, 0(t0)
|
||||
bne t1, t2, 1b
|
||||
nop
|
||||
#endif
|
||||
j ra
|
||||
nop
|
||||
|
||||
|
||||
70
package/uboot-lantiq/files/board/arcadyan/arv4518/u-boot.lds
Normal file
70
package/uboot-lantiq/files/board/arcadyan/arv4518/u-boot.lds
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk Engineering, <wd@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
|
||||
*/
|
||||
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = .;
|
||||
_gp = ALIGN(16) + 0x7ff0;
|
||||
|
||||
.got : {
|
||||
__got_start = .;
|
||||
*(.got)
|
||||
__got_end = .;
|
||||
}
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
.u_boot_cmd : {
|
||||
__u_boot_cmd_start = .;
|
||||
*(.u_boot_cmd)
|
||||
__u_boot_cmd_end = .;
|
||||
}
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss (NOLOAD) : { *(.sbss) }
|
||||
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
|
||||
uboot_end = .;
|
||||
}
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# (C) Copyright 2003-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
#COBJS := $(BOARD).o
|
||||
COBJS-y += arv752.o athrs26_phy.o
|
||||
|
||||
SOBJS = lowlevel_init.o pmuenable.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
325
package/uboot-lantiq/files/board/arcadyan/arv752DWP22/arv752.c
Normal file
325
package/uboot-lantiq/files/board/arcadyan/arv752DWP22/arv752.c
Normal file
|
|
@ -0,0 +1,325 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Thomas Langer, Ralph Hempel
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <netdev.h>
|
||||
#include <miiphy.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/danube.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/io.h>
|
||||
#if defined(CONFIG_CMD_HTTPD)
|
||||
#include <httpd.h>
|
||||
#endif
|
||||
#if defined(CONFIG_PCI)
|
||||
#include <pci.h>
|
||||
#endif
|
||||
#include "athrs26_phy.h"
|
||||
|
||||
extern ulong ifx_get_ddr_hz(void);
|
||||
extern ulong ifx_get_cpuclk(void);
|
||||
|
||||
/* IDs and registers of known external switches */
|
||||
void _machine_restart(void)
|
||||
{
|
||||
*DANUBE_RCU_RST_REQ |=1<<30;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_RAMBOOT
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
|
||||
}
|
||||
#elif defined(CONFIG_USE_DDR_RAM)
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
return (CONFIG_SYS_MAX_RAM);
|
||||
}
|
||||
#else
|
||||
|
||||
static ulong max_sdram_size(void) /* per Chip Select */
|
||||
{
|
||||
/* The only supported SDRAM data width is 16bit.
|
||||
*/
|
||||
#define CFG_DW 4
|
||||
|
||||
/* The only supported number of SDRAM banks is 4.
|
||||
*/
|
||||
#define CFG_NB 4
|
||||
|
||||
ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
|
||||
int cols = cfgpb0 & 0xF;
|
||||
int rows = (cfgpb0 & 0xF0) >> 4;
|
||||
ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check memory range for valid RAM. A simple memory test determines
|
||||
* the actually available RAM size between addresses `base' and
|
||||
* `base + maxsize'.
|
||||
*/
|
||||
|
||||
static long int dram_size(long int *base, long int maxsize)
|
||||
{
|
||||
volatile long int *addr;
|
||||
ulong cnt, val;
|
||||
ulong save[32]; /* to make test non-destructive */
|
||||
unsigned char i = 0;
|
||||
|
||||
for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
|
||||
addr = base + cnt; /* pointer arith! */
|
||||
|
||||
save[i++] = *addr;
|
||||
*addr = ~cnt;
|
||||
}
|
||||
|
||||
/* write 0 to base address */
|
||||
addr = base;
|
||||
save[i] = *addr;
|
||||
*addr = 0;
|
||||
|
||||
/* check at base address */
|
||||
if ((val = *addr) != 0) {
|
||||
*addr = save[i];
|
||||
return (0);
|
||||
}
|
||||
|
||||
for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
|
||||
addr = base + cnt; /* pointer arith! */
|
||||
|
||||
val = *addr;
|
||||
*addr = save[--i];
|
||||
|
||||
if (val != (~cnt)) {
|
||||
return (cnt * sizeof (long));
|
||||
}
|
||||
}
|
||||
return (maxsize);
|
||||
}
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
|
||||
ulong size, max_size = 0;
|
||||
ulong our_address;
|
||||
|
||||
/* load t9 into our_address */
|
||||
asm volatile ("move %0, $25" : "=r" (our_address) :);
|
||||
|
||||
/* Can't probe for RAM size unless we are running from Flash.
|
||||
* find out whether running from DRAM or Flash.
|
||||
*/
|
||||
if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
|
||||
{
|
||||
return max_sdram_size();
|
||||
}
|
||||
|
||||
for (cols = 0x8; cols <= 0xC; cols++)
|
||||
{
|
||||
for (rows = 0xB; rows <= 0xD; rows++)
|
||||
{
|
||||
*DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
|
||||
(rows << 4) | cols;
|
||||
size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
|
||||
max_sdram_size());
|
||||
|
||||
if (size > max_size)
|
||||
{
|
||||
best_val = *DANUBE_SDRAM_MC_CFGPB0;
|
||||
max_size = size;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
*DANUBE_SDRAM_MC_CFGPB0 = best_val;
|
||||
return max_size;
|
||||
}
|
||||
#endif
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
unsigned long chipid = *DANUBE_MPS_CHIPID;
|
||||
int part_num;
|
||||
|
||||
puts ("Board: ARV75DW22 - Easybox 803\n");
|
||||
puts ("SoC: ");
|
||||
|
||||
part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
|
||||
switch (part_num)
|
||||
{
|
||||
case 0x129:
|
||||
case 0x12D:
|
||||
case 0x12b:
|
||||
puts("Danube/Twinpass/Vinax-VE ");
|
||||
break;
|
||||
default:
|
||||
printf ("unknown, chip part number 0x%03X ", part_num);
|
||||
break;
|
||||
}
|
||||
printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
|
||||
|
||||
printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
|
||||
printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
#ifdef CONFIG_EBU_ADDSEL0
|
||||
(*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
|
||||
#endif
|
||||
#ifdef CONFIG_EBU_ADDSEL1
|
||||
(*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
|
||||
#endif
|
||||
#ifdef CONFIG_EBU_ADDSEL2
|
||||
(*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
|
||||
#endif
|
||||
#ifdef CONFIG_EBU_ADDSEL3
|
||||
(*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
|
||||
#endif
|
||||
#ifdef CONFIG_EBU_BUSCON0
|
||||
(*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
|
||||
#endif
|
||||
#ifdef CONFIG_EBU_BUSCON1
|
||||
(*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
|
||||
#endif
|
||||
#ifdef CONFIG_EBU_BUSCON2
|
||||
(*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
|
||||
#endif
|
||||
#ifdef CONFIG_EBU_BUSCON3
|
||||
(*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
|
||||
|
||||
#ifdef CONFIG_EXTRA_SWITCH
|
||||
static int external_switch_init(void)
|
||||
{
|
||||
// switch reset pin on arv752
|
||||
*DANUBE_GPIO_P1_ALTSEL0 &= ~8;
|
||||
*DANUBE_GPIO_P1_ALTSEL1 &= ~8;
|
||||
*DANUBE_GPIO_P1_OD |= 8;
|
||||
*DANUBE_GPIO_P1_DIR |= 8;
|
||||
*DANUBE_GPIO_P1_OUT |= 8;
|
||||
|
||||
puts("initializing ar8216 switch... ");
|
||||
if (athrs26_phy_setup(0)==0) {
|
||||
printf("initialized\n");
|
||||
return 0;
|
||||
}
|
||||
puts("failed ... \n");
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_EXTRA_SWITCH */
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#if defined(CONFIG_IFX_ETOP)
|
||||
uchar enetaddr[6];
|
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr))
|
||||
eth_setenv_enetaddr("ethaddr", (uchar *)0xb03f0016);
|
||||
|
||||
*DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
|
||||
*DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
|
||||
|
||||
if (lq_eth_initialize(bis))
|
||||
return -1;
|
||||
|
||||
*DANUBE_RCU_RST_REQ |=1;
|
||||
udelay(200000);
|
||||
*DANUBE_RCU_RST_REQ &=(unsigned long)~1;
|
||||
udelay(1000);
|
||||
|
||||
#ifdef CONFIG_EXTRA_SWITCH
|
||||
if (external_switch_init()<0)
|
||||
return -1;
|
||||
#endif /* CONFIG_EXTRA_SWITCH */
|
||||
#endif /* CONFIG_IFX_ETOP */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_HTTPD)
|
||||
int do_http_upgrade(const unsigned char *data, const ulong size)
|
||||
{
|
||||
char buf[128];
|
||||
|
||||
if(getenv ("ram_addr") == NULL)
|
||||
return -1;
|
||||
if(getenv ("kernel_addr") == NULL)
|
||||
return -1;
|
||||
/* check the image */
|
||||
if(run_command("imi ${ram_addr}", 0) < 0) {
|
||||
return -1;
|
||||
}
|
||||
/* write the image to the flash */
|
||||
puts("http ugrade ...\n");
|
||||
sprintf(buf, "era ${kernel_addr} +0x%lx; cp.b ${ram_addr} ${kernel_addr} 0x%lx", size, size);
|
||||
return run_command(buf, 0);
|
||||
}
|
||||
|
||||
int do_http_progress(const int state)
|
||||
{
|
||||
/* toggle LED's here */
|
||||
switch(state) {
|
||||
case HTTP_PROGRESS_START:
|
||||
puts("http start\n");
|
||||
break;
|
||||
case HTTP_PROGRESS_TIMEOUT:
|
||||
puts(".");
|
||||
break;
|
||||
case HTTP_PROGRESS_UPLOAD_READY:
|
||||
puts("http upload ready\n");
|
||||
break;
|
||||
case HTTP_PROGRESS_UGRADE_READY:
|
||||
puts("http ugrade ready\n");
|
||||
break;
|
||||
case HTTP_PROGRESS_UGRADE_FAILED:
|
||||
puts("http ugrade failed\n");
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long do_http_tmp_address(void)
|
||||
{
|
||||
char *s = getenv ("ram_addr");
|
||||
if (s) {
|
||||
ulong tmp = simple_strtoul (s, NULL, 16);
|
||||
return tmp;
|
||||
}
|
||||
return 0 /*0x80a00000*/;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,814 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright © 2003 Atheros Communications, Inc., All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Manage the atheros ethernet PHY.
|
||||
*
|
||||
* All definitions in this file are operating system independent!
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <linux/types.h>
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
//#include "phy.h"
|
||||
//#include "ar7100_soc.h"
|
||||
#include "athrs26_phy.h"
|
||||
|
||||
#define phy_reg_read(base, addr, reg, datap) \
|
||||
miiphy_read("lq_cpe_eth", addr, reg, datap);
|
||||
#define phy_reg_write(base, addr, reg, data) \
|
||||
miiphy_write("lq_cpe_eth", addr, reg, data);
|
||||
|
||||
|
||||
/* PHY selections and access functions */
|
||||
|
||||
typedef enum {
|
||||
PHY_SRCPORT_INFO,
|
||||
PHY_PORTINFO_SIZE,
|
||||
} PHY_CAP_TYPE;
|
||||
|
||||
typedef enum {
|
||||
PHY_SRCPORT_NONE,
|
||||
PHY_SRCPORT_VLANTAG,
|
||||
PHY_SRCPORT_TRAILER,
|
||||
} PHY_SRCPORT_TYPE;
|
||||
|
||||
#ifdef DEBUG
|
||||
#define DRV_DEBUG 1
|
||||
#endif
|
||||
//#define DRV_DEBUG 1
|
||||
|
||||
#define DRV_DEBUG_PHYERROR 0x00000001
|
||||
#define DRV_DEBUG_PHYCHANGE 0x00000002
|
||||
#define DRV_DEBUG_PHYSETUP 0x00000004
|
||||
|
||||
#if DRV_DEBUG
|
||||
int athrPhyDebug = DRV_DEBUG_PHYERROR|DRV_DEBUG_PHYCHANGE|DRV_DEBUG_PHYSETUP;
|
||||
|
||||
#define DRV_LOG(FLG, X0, X1, X2, X3, X4, X5, X6) \
|
||||
{ \
|
||||
if (athrPhyDebug & (FLG)) { \
|
||||
logMsg(X0, X1, X2, X3, X4, X5, X6); \
|
||||
} \
|
||||
}
|
||||
|
||||
#define DRV_MSG(x,a,b,c,d,e,f) \
|
||||
logMsg(x,a,b,c,d,e,f)
|
||||
|
||||
#define DRV_PRINT(FLG, X) \
|
||||
{ \
|
||||
if (athrPhyDebug & (FLG)) { \
|
||||
printf X; \
|
||||
} \
|
||||
}
|
||||
|
||||
#else /* !DRV_DEBUG */
|
||||
#define DRV_LOG(DBG_SW, X0, X1, X2, X3, X4, X5, X6)
|
||||
#define DRV_MSG(x,a,b,c,d,e,f)
|
||||
#define DRV_PRINT(DBG_SW,X)
|
||||
#endif
|
||||
|
||||
#define ATHR_LAN_PORT_VLAN 1
|
||||
#define ATHR_WAN_PORT_VLAN 2
|
||||
|
||||
#define ENET_UNIT_LAN 0
|
||||
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
|
||||
#define ATHR_PHY0_ADDR 0x0
|
||||
#define ATHR_PHY1_ADDR 0x1
|
||||
#define ATHR_PHY2_ADDR 0x2
|
||||
#define ATHR_PHY3_ADDR 0x3
|
||||
#define ATHR_PHY4_ADDR 0x4
|
||||
|
||||
/*
|
||||
* Track per-PHY port information.
|
||||
*/
|
||||
typedef struct {
|
||||
BOOL isEnetPort; /* normal enet port */
|
||||
BOOL isPhyAlive; /* last known state of link */
|
||||
int ethUnit; /* MAC associated with this phy port */
|
||||
uint32_t phyBase;
|
||||
uint32_t phyAddr; /* PHY registers associated with this phy port */
|
||||
uint32_t VLANTableSetting; /* Value to be written to VLAN table */
|
||||
} athrPhyInfo_t;
|
||||
|
||||
/*
|
||||
* Per-PHY information, indexed by PHY unit number.
|
||||
*/
|
||||
static athrPhyInfo_t athrPhyInfo[] = {
|
||||
{TRUE, /* phy port 0 -- LAN port 0 */
|
||||
FALSE,
|
||||
ENET_UNIT_LAN,
|
||||
0,
|
||||
ATHR_PHY0_ADDR,
|
||||
ATHR_LAN_PORT_VLAN
|
||||
},
|
||||
|
||||
{TRUE, /* phy port 1 -- LAN port 1 */
|
||||
FALSE,
|
||||
ENET_UNIT_LAN,
|
||||
0,
|
||||
ATHR_PHY1_ADDR,
|
||||
ATHR_LAN_PORT_VLAN
|
||||
},
|
||||
|
||||
{TRUE, /* phy port 2 -- LAN port 2 */
|
||||
FALSE,
|
||||
ENET_UNIT_LAN,
|
||||
0,
|
||||
ATHR_PHY2_ADDR,
|
||||
ATHR_LAN_PORT_VLAN
|
||||
},
|
||||
|
||||
{TRUE, /* phy port 3 -- LAN port 3 */
|
||||
FALSE,
|
||||
ENET_UNIT_LAN,
|
||||
0,
|
||||
ATHR_PHY3_ADDR,
|
||||
ATHR_LAN_PORT_VLAN
|
||||
},
|
||||
|
||||
{TRUE, /* phy port 4 -- WAN port or LAN port 4 */
|
||||
FALSE,
|
||||
1,
|
||||
0,
|
||||
ATHR_PHY4_ADDR,
|
||||
ATHR_LAN_PORT_VLAN /* Send to all ports */
|
||||
},
|
||||
|
||||
{FALSE, /* phy port 5 -- CPU port (no RJ45 connector) */
|
||||
TRUE,
|
||||
ENET_UNIT_LAN,
|
||||
0,
|
||||
0x00,
|
||||
ATHR_LAN_PORT_VLAN /* Send to all ports */
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CFG_ATHRHDR_EN
|
||||
typedef struct {
|
||||
uint8_t data[ATHRHDR_MAX_DATA];
|
||||
uint8_t len;
|
||||
uint32_t seq;
|
||||
} cmd_resp_t;
|
||||
|
||||
typedef struct {
|
||||
uint16_t reg_addr;
|
||||
uint16_t cmd_len;
|
||||
uint8_t *reg_data;
|
||||
}cmd_write_t;
|
||||
|
||||
static cmd_write_t cmd_write,cmd_read;
|
||||
static cmd_resp_t cmd_resp;
|
||||
static struct eth_device *lan_mac;
|
||||
//static atomic_t seqcnt = ATOMIC_INIT(0);
|
||||
static int seqcnt = 0;
|
||||
static int cmd = 1;
|
||||
//volatile uchar AthrHdrPkt[60];
|
||||
#endif
|
||||
|
||||
#define ATHR_GLOBALREGBASE 0
|
||||
|
||||
//#define ATHR_PHY_MAX (sizeof(athrPhyInfo) / sizeof(athrPhyInfo[0]))
|
||||
#define ATHR_PHY_MAX 5
|
||||
|
||||
/* Range of valid PHY IDs is [MIN..MAX] */
|
||||
#define ATHR_ID_MIN 0
|
||||
#define ATHR_ID_MAX (ATHR_PHY_MAX-1)
|
||||
|
||||
/* Convenience macros to access myPhyInfo */
|
||||
#define ATHR_IS_ENET_PORT(phyUnit) (athrPhyInfo[phyUnit].isEnetPort)
|
||||
#define ATHR_IS_PHY_ALIVE(phyUnit) (athrPhyInfo[phyUnit].isPhyAlive)
|
||||
#define ATHR_ETHUNIT(phyUnit) (athrPhyInfo[phyUnit].ethUnit)
|
||||
#define ATHR_PHYBASE(phyUnit) (athrPhyInfo[phyUnit].phyBase)
|
||||
#define ATHR_PHYADDR(phyUnit) (athrPhyInfo[phyUnit].phyAddr)
|
||||
#define ATHR_VLAN_TABLE_SETTING(phyUnit) (athrPhyInfo[phyUnit].VLANTableSetting)
|
||||
|
||||
|
||||
#define ATHR_IS_ETHUNIT(phyUnit, ethUnit) \
|
||||
(ATHR_IS_ENET_PORT(phyUnit) && \
|
||||
ATHR_ETHUNIT(phyUnit) == (ethUnit))
|
||||
|
||||
#define ATHR_IS_WAN_PORT(phyUnit) (!(ATHR_ETHUNIT(phyUnit)==ENET_UNIT_LAN))
|
||||
|
||||
/* Forward references */
|
||||
BOOL athrs26_phy_is_link_alive(int phyUnit);
|
||||
static uint32_t athrs26_reg_read(uint16_t reg_addr);
|
||||
static void athrs26_reg_write(uint16_t reg_addr,
|
||||
uint32_t reg_val);
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* athrs26_phy_is_link_alive - test to see if the specified link is alive
|
||||
*
|
||||
* RETURNS:
|
||||
* TRUE --> link is alive
|
||||
* FALSE --> link is down
|
||||
*/
|
||||
|
||||
void athrs26_reg_init()
|
||||
{
|
||||
|
||||
athrs26_reg_write(0x200, 0x200);
|
||||
athrs26_reg_write(0x300, 0x200);
|
||||
athrs26_reg_write(0x400, 0x200);
|
||||
athrs26_reg_write(0x500, 0x200);
|
||||
athrs26_reg_write(0x600, 0x7d);
|
||||
|
||||
#ifdef S26_VER_1_0
|
||||
phy_reg_write(0, 0, 29, 41);
|
||||
phy_reg_write(0, 0, 30, 0);
|
||||
phy_reg_write(0, 1, 29, 41);
|
||||
phy_reg_write(0, 1, 30, 0);
|
||||
phy_reg_write(0, 2, 29, 41);
|
||||
phy_reg_write(0, 2, 30, 0);
|
||||
phy_reg_write(0, 3, 29, 41);
|
||||
phy_reg_write(0, 3, 30, 0);
|
||||
phy_reg_write(0, 4, 29, 41);
|
||||
phy_reg_write(0, 4, 30, 0);
|
||||
#endif
|
||||
|
||||
athrs26_reg_write(0x38, 0xc000050e);
|
||||
|
||||
#ifdef CFG_ATHRHDR_EN
|
||||
athrs26_reg_write(0x104, 0x4804);
|
||||
#else
|
||||
athrs26_reg_write(0x104, 0x4004);
|
||||
#endif
|
||||
|
||||
athrs26_reg_write(0x60, 0xffffffff);
|
||||
athrs26_reg_write(0x64, 0xaaaaaaaa);
|
||||
athrs26_reg_write(0x68, 0x55555555);
|
||||
athrs26_reg_write(0x6c, 0x0);
|
||||
|
||||
athrs26_reg_write(0x70, 0x41af);
|
||||
}
|
||||
|
||||
BOOL
|
||||
athrs26_phy_is_link_alive(int phyUnit)
|
||||
{
|
||||
uint16_t phyHwStatus;
|
||||
uint32_t phyBase;
|
||||
uint32_t phyAddr;
|
||||
|
||||
phyBase = ATHR_PHYBASE(phyUnit);
|
||||
phyAddr = ATHR_PHYADDR(phyUnit);
|
||||
|
||||
phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus);
|
||||
|
||||
if (phyHwStatus & ATHR_STATUS_LINK_PASS)
|
||||
return TRUE;
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* athrs26_phy_setup - reset and setup the PHY associated with
|
||||
* the specified MAC unit number.
|
||||
*
|
||||
* Resets the associated PHY port.
|
||||
*
|
||||
* RETURNS:
|
||||
* TRUE --> associated PHY is alive
|
||||
* FALSE --> no LINKs on this ethernet unit
|
||||
*/
|
||||
|
||||
BOOL
|
||||
athrs26_phy_setup(int ethUnit)
|
||||
{
|
||||
int phyUnit;
|
||||
uint16_t phyHwStatus;
|
||||
uint16_t timeout;
|
||||
int liveLinks = 0;
|
||||
uint32_t phyBase = 0;
|
||||
BOOL foundPhy = FALSE;
|
||||
uint32_t phyAddr = 0;
|
||||
uint32_t regVal;
|
||||
|
||||
|
||||
/* See if there's any configuration data for this enet */
|
||||
/* start auto negogiation on each phy */
|
||||
for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
|
||||
if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
|
||||
foundPhy = TRUE;
|
||||
phyBase = ATHR_PHYBASE(phyUnit);
|
||||
phyAddr = ATHR_PHYADDR(phyUnit);
|
||||
|
||||
phy_reg_write(phyBase, phyAddr, ATHR_AUTONEG_ADVERT,
|
||||
ATHR_ADVERTISE_ALL);
|
||||
|
||||
/* Reset PHYs*/
|
||||
phy_reg_write(phyBase, phyAddr, ATHR_PHY_CONTROL,
|
||||
ATHR_CTRL_AUTONEGOTIATION_ENABLE
|
||||
| ATHR_CTRL_SOFTWARE_RESET);
|
||||
|
||||
}
|
||||
|
||||
if (!foundPhy) {
|
||||
return FALSE; /* No PHY's configured for this ethUnit */
|
||||
}
|
||||
|
||||
/*
|
||||
* After the phy is reset, it takes a little while before
|
||||
* it can respond properly.
|
||||
*/
|
||||
sysMsDelay(1000);
|
||||
|
||||
/*
|
||||
* Wait up to .75 seconds for ALL associated PHYs to finish
|
||||
* autonegotiation. The only way we get out of here sooner is
|
||||
* if ALL PHYs are connected AND finish autonegotiation.
|
||||
*/
|
||||
for (phyUnit=0; (phyUnit < ATHR_PHY_MAX) /*&& (timeout > 0) */; phyUnit++) {
|
||||
if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
timeout=20;
|
||||
for (;;) {
|
||||
phyHwStatus = 0;
|
||||
phy_reg_read(phyBase, phyAddr, ATHR_PHY_CONTROL, &phyHwStatus);
|
||||
|
||||
if (ATHR_RESET_DONE(phyHwStatus)) {
|
||||
DRV_PRINT(DRV_DEBUG_PHYSETUP,
|
||||
("Port %d, Neg Success\n", phyUnit));
|
||||
break;
|
||||
}
|
||||
if (timeout == 0) {
|
||||
DRV_PRINT(DRV_DEBUG_PHYSETUP,
|
||||
("Port %d, Negogiation timeout\n", phyUnit));
|
||||
break;
|
||||
}
|
||||
if (--timeout == 0) {
|
||||
DRV_PRINT(DRV_DEBUG_PHYSETUP,
|
||||
("Port %d, Negogiation timeout\n", phyUnit));
|
||||
break;
|
||||
}
|
||||
|
||||
sysMsDelay(150);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* All PHYs have had adequate time to autonegotiate.
|
||||
* Now initialize software status.
|
||||
*
|
||||
* It's possible that some ports may take a bit longer
|
||||
* to autonegotiate; but we can't wait forever. They'll
|
||||
* get noticed by mv_phyCheckStatusChange during regular
|
||||
* polling activities.
|
||||
*/
|
||||
for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
|
||||
if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if (athrs26_phy_is_link_alive(phyUnit)) {
|
||||
liveLinks++;
|
||||
ATHR_IS_PHY_ALIVE(phyUnit) = TRUE;
|
||||
} else {
|
||||
ATHR_IS_PHY_ALIVE(phyUnit) = FALSE;
|
||||
}
|
||||
|
||||
phy_reg_read(ATHR_PHYBASE(phyUnit), ATHR_PHYADDR(phyUnit),
|
||||
ATHR_PHY_SPEC_STATUS, ®Val);
|
||||
DRV_PRINT(DRV_DEBUG_PHYSETUP,
|
||||
("eth%d: Phy Specific Status=%4.4x\n", ethUnit, regVal));
|
||||
}
|
||||
#if 0
|
||||
/* if using header for register configuration, we have to */
|
||||
/* configure s26 register after frame transmission is enabled */
|
||||
|
||||
athrs26_reg_write(0x200, 0x200);
|
||||
athrs26_reg_write(0x300, 0x200);
|
||||
athrs26_reg_write(0x400, 0x200);
|
||||
athrs26_reg_write(0x500, 0x200);
|
||||
athrs26_reg_write(0x600, 0x200);
|
||||
athrs26_reg_write(0x38, 0x50e);
|
||||
#endif
|
||||
#ifndef CFG_ATHRHDR_EN
|
||||
/* if using header for register configuration, we have to */
|
||||
/* configure s26 register after frame transmission is enabled */
|
||||
athrs26_reg_init();
|
||||
#endif
|
||||
|
||||
return (liveLinks > 0);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* athrs26_phy_is_fdx - Determines whether the phy ports associated with the
|
||||
* specified device are FULL or HALF duplex.
|
||||
*
|
||||
* RETURNS:
|
||||
* 1 --> FULL
|
||||
* 0 --> HALF
|
||||
*/
|
||||
int
|
||||
athrs26_phy_is_fdx(int ethUnit)
|
||||
{
|
||||
int phyUnit;
|
||||
uint32_t phyBase;
|
||||
uint32_t phyAddr;
|
||||
uint16_t phyHwStatus;
|
||||
int ii = 200;
|
||||
|
||||
if (ethUnit == ENET_UNIT_LAN)
|
||||
return TRUE;
|
||||
|
||||
for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
|
||||
if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if (athrs26_phy_is_link_alive(phyUnit)) {
|
||||
|
||||
phyBase = ATHR_PHYBASE(phyUnit);
|
||||
phyAddr = ATHR_PHYADDR(phyUnit);
|
||||
|
||||
do {
|
||||
phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus);
|
||||
sysMsDelay(10);
|
||||
} while((!(phyHwStatus & ATHR_STATUS_RESOVLED)) && --ii);
|
||||
|
||||
if (phyHwStatus & ATHER_STATUS_FULL_DEPLEX)
|
||||
return TRUE;
|
||||
}
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* athrs26_phy_speed - Determines the speed of phy ports associated with the
|
||||
* specified device.
|
||||
*
|
||||
* RETURNS:
|
||||
* AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX;
|
||||
* AG7100_PHY_SPEED_1000T;
|
||||
*/
|
||||
|
||||
BOOL
|
||||
athrs26_phy_speed(int ethUnit)
|
||||
{
|
||||
int phyUnit;
|
||||
uint16_t phyHwStatus;
|
||||
uint32_t phyBase;
|
||||
uint32_t phyAddr;
|
||||
int ii = 200;
|
||||
|
||||
if (ethUnit == ENET_UNIT_LAN)
|
||||
return _100BASET;
|
||||
|
||||
for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
|
||||
if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if (athrs26_phy_is_link_alive(phyUnit)) {
|
||||
|
||||
phyBase = ATHR_PHYBASE(phyUnit);
|
||||
phyAddr = ATHR_PHYADDR(phyUnit);
|
||||
|
||||
do {
|
||||
phy_reg_read(phyBase, phyAddr,
|
||||
ATHR_PHY_SPEC_STATUS, &phyHwStatus);
|
||||
sysMsDelay(10);
|
||||
}while((!(phyHwStatus & ATHR_STATUS_RESOVLED)) && --ii);
|
||||
|
||||
phyHwStatus = ((phyHwStatus & ATHER_STATUS_LINK_MASK) >>
|
||||
ATHER_STATUS_LINK_SHIFT);
|
||||
|
||||
switch(phyHwStatus) {
|
||||
case 0:
|
||||
return _10BASET;
|
||||
case 1:
|
||||
return _100BASET;
|
||||
case 2:
|
||||
return _1000BASET;
|
||||
default:
|
||||
DRV_PRINT(DRV_DEBUG_PHYERROR, ("Unkown speed read!\n"));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return _10BASET;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* athr_phy_is_up -- checks for significant changes in PHY state.
|
||||
*
|
||||
* A "significant change" is:
|
||||
* dropped link (e.g. ethernet cable unplugged) OR
|
||||
* autonegotiation completed + link (e.g. ethernet cable plugged in)
|
||||
*
|
||||
* When a PHY is plugged in, phyLinkGained is called.
|
||||
* When a PHY is unplugged, phyLinkLost is called.
|
||||
*/
|
||||
|
||||
int
|
||||
athrs26_phy_is_up(int ethUnit)
|
||||
{
|
||||
int phyUnit;
|
||||
uint16_t phyHwStatus;
|
||||
athrPhyInfo_t *lastStatus;
|
||||
int linkCount = 0;
|
||||
int lostLinks = 0;
|
||||
int gainedLinks = 0;
|
||||
uint32_t phyBase;
|
||||
uint32_t phyAddr;
|
||||
#ifdef CFG_ATHRHDR_REG
|
||||
/* if using header to config s26, the link of MAC0 should always be up */
|
||||
if (ethUnit == ENET_UNIT_LAN)
|
||||
return 1;
|
||||
#endif
|
||||
|
||||
for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
|
||||
if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
phyBase = ATHR_PHYBASE(phyUnit);
|
||||
phyAddr = ATHR_PHYADDR(phyUnit);
|
||||
|
||||
|
||||
lastStatus = &athrPhyInfo[phyUnit];
|
||||
phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus);
|
||||
|
||||
if (lastStatus->isPhyAlive) { /* last known link status was ALIVE */
|
||||
/* See if we've lost link */
|
||||
if (phyHwStatus & ATHR_STATUS_LINK_PASS) {
|
||||
linkCount++;
|
||||
} else {
|
||||
lostLinks++;
|
||||
DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d down\n",
|
||||
ethUnit, phyUnit));
|
||||
lastStatus->isPhyAlive = FALSE;
|
||||
}
|
||||
} else { /* last known link status was DEAD */
|
||||
/* Check for reset complete */
|
||||
phy_reg_read(phyBase, phyAddr, ATHR_PHY_STATUS, &phyHwStatus);
|
||||
if (!ATHR_RESET_DONE(phyHwStatus))
|
||||
continue;
|
||||
|
||||
/* Check for AutoNegotiation complete */
|
||||
if (ATHR_AUTONEG_DONE(phyHwStatus)) {
|
||||
//printk("autoneg done\n");
|
||||
gainedLinks++;
|
||||
linkCount++;
|
||||
DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d up\n",
|
||||
ethUnit, phyUnit));
|
||||
lastStatus->isPhyAlive = TRUE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (linkCount);
|
||||
|
||||
#if 0
|
||||
if (linkCount == 0) {
|
||||
if (lostLinks) {
|
||||
/* We just lost the last link for this MAC */
|
||||
phyLinkLost(ethUnit);
|
||||
}
|
||||
} else {
|
||||
if (gainedLinks == linkCount) {
|
||||
/* We just gained our first link(s) for this MAC */
|
||||
phyLinkGained(ethUnit);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CFG_ATHRHDR_EN
|
||||
void athr_hdr_timeout(void){
|
||||
eth_halt();
|
||||
NetState = NETLOOP_FAIL;
|
||||
}
|
||||
|
||||
void athr_hdr_handler(uchar *recv_pkt, unsigned dest, unsigned src, unsigned len){
|
||||
header_receive_pkt(recv_pkt);
|
||||
NetState = NETLOOP_SUCCESS;
|
||||
}
|
||||
static int
|
||||
athrs26_header_config_reg (struct eth_device *dev, uint8_t wr_flag,
|
||||
uint16_t reg_addr, uint16_t cmd_len,
|
||||
uint8_t *val)
|
||||
{
|
||||
at_header_t at_header;
|
||||
reg_cmd_t reg_cmd;
|
||||
uchar *AthrHdrPkt;
|
||||
|
||||
AthrHdrPkt = NetTxPacket;
|
||||
|
||||
if(AthrHdrPkt == NULL) {
|
||||
printf("Null packet\n");
|
||||
return;
|
||||
}
|
||||
memset(AthrHdrPkt,0,60);
|
||||
|
||||
/*fill at_header*/
|
||||
at_header.reserved0 = 0x10; //default
|
||||
at_header.priority = 0;
|
||||
at_header.type = 0x5;
|
||||
at_header.broadcast = 0;
|
||||
at_header.from_cpu = 1;
|
||||
at_header.reserved1 = 0x01; //default
|
||||
at_header.port_num = 0;
|
||||
|
||||
AthrHdrPkt[0] = at_header.port_num;
|
||||
AthrHdrPkt[0] |= at_header.reserved1 << 4;
|
||||
AthrHdrPkt[0] |= at_header.from_cpu << 6;
|
||||
AthrHdrPkt[0] |= at_header.broadcast << 7;
|
||||
|
||||
AthrHdrPkt[1] = at_header.type;
|
||||
AthrHdrPkt[1] |= at_header.priority << 4;
|
||||
AthrHdrPkt[1] |= at_header.reserved0 << 6;
|
||||
|
||||
|
||||
/*fill reg cmd*/
|
||||
if(cmd_len > 4)
|
||||
cmd_len = 4;//only support 32bits register r/w
|
||||
|
||||
reg_cmd.reg_addr = reg_addr&0x3FFFC;
|
||||
reg_cmd.cmd_len = cmd_len;
|
||||
reg_cmd.cmd = wr_flag;
|
||||
reg_cmd.reserved2 = 0x5; //default
|
||||
reg_cmd.seq_num = seqcnt;
|
||||
|
||||
AthrHdrPkt[2] = reg_cmd.reg_addr & 0xff;
|
||||
AthrHdrPkt[3] = (reg_cmd.reg_addr & 0xff00) >> 8;
|
||||
AthrHdrPkt[4] = (reg_cmd.reg_addr & 0x30000) >> 16;
|
||||
AthrHdrPkt[4] |= reg_cmd.cmd_len << 4;
|
||||
AthrHdrPkt[5] = reg_cmd.cmd << 4;
|
||||
AthrHdrPkt[5] |= reg_cmd.reserved2 << 5;
|
||||
AthrHdrPkt[6] = (reg_cmd.seq_num & 0x7f) << 1;
|
||||
AthrHdrPkt[7] = (reg_cmd.seq_num & 0x7f80) >> 7;
|
||||
AthrHdrPkt[8] = (reg_cmd.seq_num & 0x7f8000) >> 15;
|
||||
AthrHdrPkt[9] = (reg_cmd.seq_num & 0x7f800000) >> 23;
|
||||
|
||||
/*fill reg data*/
|
||||
if(!wr_flag)//write
|
||||
memcpy((AthrHdrPkt + 10), val, cmd_len);
|
||||
|
||||
/*start xmit*/
|
||||
if(dev == NULL) {
|
||||
printf("ERROR device not found\n");
|
||||
return -1;
|
||||
}
|
||||
header_xmit(dev, AthrHdrPkt ,60);
|
||||
return 0;
|
||||
}
|
||||
void athr_hdr_func(void) {
|
||||
|
||||
NetSetTimeout (1 * CFG_HZ,athr_hdr_timeout );
|
||||
NetSetHandler (athr_hdr_handler);
|
||||
|
||||
if(cmd)
|
||||
athrs26_header_config_reg(lan_mac, cmd, cmd_read.reg_addr, cmd_read.cmd_len, cmd_read.reg_data);
|
||||
else
|
||||
athrs26_header_config_reg(lan_mac, cmd, cmd_write.reg_addr, cmd_write.cmd_len, cmd_write.reg_data);
|
||||
}
|
||||
static int
|
||||
athrs26_header_write_reg(uint16_t reg_addr, uint16_t cmd_len, uint8_t *reg_data)
|
||||
{
|
||||
int i = 2;
|
||||
cmd_write.reg_addr = reg_addr;
|
||||
cmd_write.cmd_len = cmd_len;
|
||||
cmd_write.reg_data = reg_data;
|
||||
cmd = 0;
|
||||
seqcnt++;
|
||||
|
||||
do {
|
||||
if (NetLoop(ATHRHDR) >= 0) /* polls for read/write ack from PHY */
|
||||
break;
|
||||
} while (i--);
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
static int
|
||||
athrs26_header_read_reg(uint16_t reg_addr, uint16_t cmd_len, uint8_t *reg_data)
|
||||
{
|
||||
int i = 2;
|
||||
|
||||
cmd_read.reg_addr = reg_addr;
|
||||
cmd_read.cmd_len = cmd_len;
|
||||
cmd_read.reg_data = reg_data;
|
||||
cmd = 1;
|
||||
seqcnt++;
|
||||
|
||||
do {
|
||||
if (NetLoop(ATHRHDR) >= 0) /* polls for read/write ack from PHY */
|
||||
break;
|
||||
} while (i--);
|
||||
|
||||
if ((i==0) || (seqcnt != cmd_resp.seq) || (cmd_len != cmd_resp.len)) {
|
||||
return -1;
|
||||
}
|
||||
memcpy (cmd_read.reg_data, cmd_resp.data, cmd_len);
|
||||
return 0;
|
||||
}
|
||||
int header_receive_pkt(uchar *recv_pkt)
|
||||
{
|
||||
cmd_resp.len = recv_pkt[4] >> 4;
|
||||
if (cmd_resp.len > 10)
|
||||
goto out;
|
||||
|
||||
cmd_resp.seq = recv_pkt[6] >> 1;
|
||||
cmd_resp.seq |= recv_pkt[7] << 7;
|
||||
cmd_resp.seq |= recv_pkt[8] << 15;
|
||||
cmd_resp.seq |= recv_pkt[9] << 23;
|
||||
|
||||
if (cmd_resp.seq < seqcnt)
|
||||
goto out;
|
||||
memcpy (cmd_resp.data, (recv_pkt + 10), cmd_resp.len);
|
||||
out:
|
||||
return 0;
|
||||
}
|
||||
|
||||
void athrs26_reg_dev(struct eth_device *mac)
|
||||
{
|
||||
lan_mac = mac;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static uint32_t
|
||||
athrs26_reg_read(uint16_t reg_addr)
|
||||
{
|
||||
#ifndef CFG_ATHRHDR_REG
|
||||
uint16_t reg_word_addr = reg_addr / 2, phy_val;
|
||||
uint32_t phy_addr;
|
||||
uint8_t phy_reg;
|
||||
|
||||
/* configure register high address */
|
||||
phy_addr = 0x18;
|
||||
phy_reg = 0x0;
|
||||
phy_val = (reg_word_addr >> 8) & 0x1ff; /* bit16-8 of reg address*/
|
||||
phy_reg_write (0, phy_addr, phy_reg, phy_val);
|
||||
|
||||
/* read register with low address */
|
||||
phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
|
||||
phy_reg = reg_word_addr & 0x1f; /* bit 4-0 of reg address*/
|
||||
phy_reg_read(0, phy_addr, phy_reg, &phy_val);
|
||||
|
||||
return phy_val;
|
||||
#else
|
||||
uint8_t reg_data[4];
|
||||
|
||||
memset (reg_data, 0, 4);
|
||||
athrs26_header_read_reg(reg_addr, 4, reg_data);
|
||||
return (reg_data[0] | (reg_data[1] << 8) | (reg_data[2] << 16) | (reg_data[3] << 24));
|
||||
#endif
|
||||
}
|
||||
|
||||
static void
|
||||
athrs26_reg_write(uint16_t reg_addr, uint32_t reg_val)
|
||||
{
|
||||
#ifndef CFG_ATHRHDR_REG
|
||||
uint16_t reg_word_addr = reg_addr / 2, phy_val;
|
||||
uint32_t phy_addr;
|
||||
uint8_t phy_reg;
|
||||
|
||||
/* configure register high address */
|
||||
phy_addr = 0x18;
|
||||
phy_reg = 0x0;
|
||||
phy_val = (reg_word_addr >> 8) & 0x1ff; /* bit16-8 of reg address*/
|
||||
phy_reg_write (0, phy_addr, phy_reg, phy_val);
|
||||
|
||||
/* read register with low address */
|
||||
phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
|
||||
phy_reg = reg_word_addr & 0x1f; /* bit 4-0 of reg address */
|
||||
phy_reg_write (0, phy_addr, phy_reg, reg_val);
|
||||
#else
|
||||
uint8_t reg_data[4];
|
||||
|
||||
memset (reg_data, 0, 4);
|
||||
reg_data[0] = (uint8_t)(0x00ff & reg_val);
|
||||
reg_data[1] = (uint8_t)((0xff00 & reg_val) >> 8);
|
||||
reg_data[2] = (uint8_t)((0xff0000 & reg_val) >> 16);
|
||||
reg_data[3] = (uint8_t)((0xff000000 & reg_val) >> 24);
|
||||
|
||||
athrs26_header_write_reg (reg_addr, 4, reg_data);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
#ifndef _ATHRS26_PHY_H
|
||||
#define _ATHRS26_PHY_H
|
||||
|
||||
/*****************/
|
||||
/* PHY Registers */
|
||||
/*****************/
|
||||
#define ATHR_PHY_CONTROL 0
|
||||
#define ATHR_PHY_STATUS 1
|
||||
#define ATHR_PHY_ID1 2
|
||||
#define ATHR_PHY_ID2 3
|
||||
#define ATHR_AUTONEG_ADVERT 4
|
||||
#define ATHR_LINK_PARTNER_ABILITY 5
|
||||
#define ATHR_AUTONEG_EXPANSION 6
|
||||
#define ATHR_NEXT_PAGE_TRANSMIT 7
|
||||
#define ATHR_LINK_PARTNER_NEXT_PAGE 8
|
||||
#define ATHR_1000BASET_CONTROL 9
|
||||
#define ATHR_1000BASET_STATUS 10
|
||||
#define ATHR_PHY_SPEC_CONTROL 16
|
||||
#define ATHR_PHY_SPEC_STATUS 17
|
||||
#define ATHR_DEBUG_PORT_ADDRESS 29
|
||||
#define ATHR_DEBUG_PORT_DATA 30
|
||||
|
||||
/* ATHR_PHY_CONTROL fields */
|
||||
#define ATHR_CTRL_SOFTWARE_RESET 0x8000
|
||||
#define ATHR_CTRL_SPEED_LSB 0x2000
|
||||
#define ATHR_CTRL_AUTONEGOTIATION_ENABLE 0x1000
|
||||
#define ATHR_CTRL_RESTART_AUTONEGOTIATION 0x0200
|
||||
#define ATHR_CTRL_SPEED_FULL_DUPLEX 0x0100
|
||||
#define ATHR_CTRL_SPEED_MSB 0x0040
|
||||
|
||||
#define ATHR_RESET_DONE(phy_control) \
|
||||
(((phy_control) & (ATHR_CTRL_SOFTWARE_RESET)) == 0)
|
||||
|
||||
/* Phy status fields */
|
||||
#define ATHR_STATUS_AUTO_NEG_DONE 0x0020
|
||||
|
||||
#define ATHR_AUTONEG_DONE(ip_phy_status) \
|
||||
(((ip_phy_status) & \
|
||||
(ATHR_STATUS_AUTO_NEG_DONE)) == \
|
||||
(ATHR_STATUS_AUTO_NEG_DONE))
|
||||
|
||||
/* Link Partner ability */
|
||||
#define ATHR_LINK_100BASETX_FULL_DUPLEX 0x0100
|
||||
#define ATHR_LINK_100BASETX 0x0080
|
||||
#define ATHR_LINK_10BASETX_FULL_DUPLEX 0x0040
|
||||
#define ATHR_LINK_10BASETX 0x0020
|
||||
|
||||
/* Advertisement register. */
|
||||
#define ATHR_ADVERTISE_NEXT_PAGE 0x8000
|
||||
#define ATHR_ADVERTISE_ASYM_PAUSE 0x0800
|
||||
#define ATHR_ADVERTISE_PAUSE 0x0400
|
||||
#define ATHR_ADVERTISE_100FULL 0x0100
|
||||
#define ATHR_ADVERTISE_100HALF 0x0080
|
||||
#define ATHR_ADVERTISE_10FULL 0x0040
|
||||
#define ATHR_ADVERTISE_10HALF 0x0020
|
||||
|
||||
#define ATHR_ADVERTISE_ALL (ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL | \
|
||||
ATHR_ADVERTISE_100HALF | ATHR_ADVERTISE_100FULL)
|
||||
|
||||
/* 1000BASET_CONTROL */
|
||||
#define ATHR_ADVERTISE_1000FULL 0x0200
|
||||
|
||||
/* Phy Specific status fields */
|
||||
#define ATHER_STATUS_LINK_MASK 0xC000
|
||||
#define ATHER_STATUS_LINK_SHIFT 14
|
||||
#define ATHER_STATUS_FULL_DEPLEX 0x2000
|
||||
#define ATHR_STATUS_LINK_PASS 0x0400
|
||||
#define ATHR_STATUS_RESOVLED 0x0800
|
||||
|
||||
/*phy debug port register */
|
||||
#define ATHER_DEBUG_SERDES_REG 5
|
||||
|
||||
/* Serdes debug fields */
|
||||
#define ATHER_SERDES_BEACON 0x0100
|
||||
|
||||
#ifndef BOOL
|
||||
#define BOOL int
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
#define sysMsDelay(_x) udelay((_x) * 1000)
|
||||
|
||||
#undef S26_VER_1_0
|
||||
|
||||
#ifdef CFG_ATHRHDR_EN
|
||||
|
||||
#include <net.h>
|
||||
#define header_xmit(dev,pkt,len) dev->send(dev,pkt,len) //dev_queue_xmit(skb)
|
||||
#define header_recv_ack(dev) dev->recv(dev) //dev_queue_xmit(skb)
|
||||
|
||||
typedef enum {
|
||||
NORMAL_PACKET,
|
||||
RESERVED0,
|
||||
MIB_1ST,
|
||||
RESERVED1,
|
||||
RESERVED2,
|
||||
READ_WRITE_REG,
|
||||
READ_WRITE_REG_ACK,
|
||||
RESERVED3
|
||||
} ATHR_HDR_TYPE;
|
||||
|
||||
typedef struct {
|
||||
uint16_t reserved0;
|
||||
uint16_t priority;
|
||||
uint16_t type ;
|
||||
uint16_t broadcast;
|
||||
uint16_t from_cpu;
|
||||
uint16_t reserved1;
|
||||
uint16_t port_num;
|
||||
}at_header_t;
|
||||
|
||||
typedef struct {
|
||||
uint64_t reg_addr;
|
||||
uint64_t reserved0;
|
||||
uint64_t cmd_len;
|
||||
uint64_t reserved1;
|
||||
uint64_t cmd;
|
||||
uint64_t reserved2;
|
||||
uint64_t seq_num;
|
||||
}reg_cmd_t;
|
||||
void athrs26_reg_init(void);
|
||||
int header_receive_pkt(uchar *pkt);
|
||||
void athrs26_reg_dev(struct eth_device *mac);
|
||||
|
||||
#endif
|
||||
|
||||
int athrs26_phy_is_up(int unit);
|
||||
int athrs26_phy_is_fdx(int unit);
|
||||
int athrs26_phy_speed(int unit);
|
||||
BOOL athrs26_phy_setup(int unit);
|
||||
|
||||
#endif /* _ATHRS26_PHY_H */
|
||||
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
#
|
||||
# (C) Copyright 2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# Danube board with MIPS 24Kc CPU core
|
||||
#
|
||||
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
|
||||
|
||||
ifdef CONFIG_LZMA_BOOTSTRAP
|
||||
|
||||
ifdef BUILD_BOOTSTRAP
|
||||
|
||||
$(info BUILD_BOOTSTRAP )
|
||||
#TEXT_BASE = 0xB0000000
|
||||
TEXT_BASE = 0x80010000
|
||||
|
||||
else # BUILD_BOOTSTRAP
|
||||
|
||||
ifndef TEXT_BASE
|
||||
$(info redefine TEXT_BASE = 0x80040000 )
|
||||
TEXT_BASE = 0x80040000
|
||||
endif
|
||||
|
||||
endif # BUILD_BOOTSTRAP
|
||||
|
||||
else
|
||||
|
||||
ifdef BUILD_BOOTSTRAP
|
||||
$(error BUILD_BOOTSTRAP but not enabled in config)
|
||||
endif
|
||||
|
||||
ifndef TEXT_BASE
|
||||
## Standard: boot from ebu
|
||||
$(info redefine TEXT_BASE = 0xB0000000 )
|
||||
TEXT_BASE = 0xB0000000
|
||||
## For testing: boot from RAM
|
||||
# TEXT_BASE = 0x80100000
|
||||
endif
|
||||
|
||||
endif # CONFIG_LZMA_BOOTSTRAP
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/* Settings for Denali DDR SDRAM controller */
|
||||
/* Optimise for DDR PSC A3S12D40ETP for arv4518pw Danube Board DDR 166 Mhz - by Ngp 14th Sept. 2010 */
|
||||
|
||||
#define MC_DC0_VALUE 0x1B1B
|
||||
#define MC_DC1_VALUE 0x0
|
||||
#define MC_DC2_VALUE 0x0
|
||||
#define MC_DC3_VALUE 0x0
|
||||
#define MC_DC4_VALUE 0x0
|
||||
#define MC_DC5_VALUE 0x200
|
||||
#define MC_DC6_VALUE 0x605
|
||||
#define MC_DC7_VALUE 0x303
|
||||
#define MC_DC8_VALUE 0x102
|
||||
#define MC_DC9_VALUE 0x70a
|
||||
#define MC_DC10_VALUE 0x203
|
||||
#define MC_DC11_VALUE 0xc02
|
||||
#define MC_DC12_VALUE 0x1C8
|
||||
#define MC_DC13_VALUE 0x1
|
||||
#define MC_DC14_VALUE 0x0
|
||||
#define MC_DC15_VALUE 0x130 /* WDQS tuning for clk_wr*/
|
||||
#define MC_DC16_VALUE 0xC800
|
||||
#define MC_DC17_VALUE 0xd
|
||||
#define MC_DC18_VALUE 0x301
|
||||
#define MC_DC19_VALUE 0x200
|
||||
#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
|
||||
#define MC_DC21_VALUE 0x1b00
|
||||
#define MC_DC22_VALUE 0x1b1b
|
||||
#define MC_DC23_VALUE 0x0
|
||||
#define MC_DC24_VALUE 0x59 /* WDQS Tuning for DQS */
|
||||
#define MC_DC25_VALUE 0x0
|
||||
#define MC_DC26_VALUE 0x0
|
||||
#define MC_DC27_VALUE 0x0
|
||||
#define MC_DC28_VALUE 0x510
|
||||
#define MC_DC29_VALUE 0x4e20
|
||||
#define MC_DC30_VALUE 0x8235
|
||||
#define MC_DC31_VALUE 0x0
|
||||
#define MC_DC32_VALUE 0x0
|
||||
#define MC_DC33_VALUE 0x0
|
||||
#define MC_DC34_VALUE 0x0
|
||||
#define MC_DC35_VALUE 0x0
|
||||
#define MC_DC36_VALUE 0x0
|
||||
#define MC_DC37_VALUE 0x0
|
||||
#define MC_DC38_VALUE 0x0
|
||||
#define MC_DC39_VALUE 0x0
|
||||
#define MC_DC40_VALUE 0x0
|
||||
#define MC_DC41_VALUE 0x0
|
||||
#define MC_DC42_VALUE 0x0
|
||||
#define MC_DC43_VALUE 0x0
|
||||
#define MC_DC44_VALUE 0x0
|
||||
#define MC_DC45_VALUE 0x500
|
||||
#define MC_DC46_VALUE 0x0
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
/* Settings for Denali DDR SDRAM controller */
|
||||
/* Optimise for PSC DDR A2S56D40CTP for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
|
||||
|
||||
#define MC_DC0_VALUE 0x1B1B
|
||||
#define MC_DC1_VALUE 0x0
|
||||
#define MC_DC2_VALUE 0x0
|
||||
#define MC_DC3_VALUE 0x0
|
||||
#define MC_DC4_VALUE 0x0
|
||||
#define MC_DC5_VALUE 0x200
|
||||
#define MC_DC6_VALUE 0x605
|
||||
#define MC_DC7_VALUE 0x303
|
||||
#define MC_DC8_VALUE 0x102
|
||||
#define MC_DC9_VALUE 0x70a
|
||||
#define MC_DC10_VALUE 0x203
|
||||
#define MC_DC11_VALUE 0xc02
|
||||
#define MC_DC12_VALUE 0x1C8
|
||||
#define MC_DC13_VALUE 0x1
|
||||
#define MC_DC14_VALUE 0x0
|
||||
#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/
|
||||
#define MC_DC16_VALUE 0xC800
|
||||
#define MC_DC17_VALUE 0xd
|
||||
#define MC_DC18_VALUE 0x301
|
||||
#define MC_DC19_VALUE 0x200
|
||||
#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
|
||||
#define MC_DC21_VALUE 0x1700
|
||||
#define MC_DC22_VALUE 0x1717
|
||||
#define MC_DC23_VALUE 0x0
|
||||
#define MC_DC24_VALUE 0x52 /* WDQS Tuning for DQS */
|
||||
#define MC_DC25_VALUE 0x0
|
||||
#define MC_DC26_VALUE 0x0
|
||||
#define MC_DC27_VALUE 0x0
|
||||
#define MC_DC28_VALUE 0x510
|
||||
#define MC_DC29_VALUE 0x4e20
|
||||
#define MC_DC30_VALUE 0x8235
|
||||
#define MC_DC31_VALUE 0x0
|
||||
#define MC_DC32_VALUE 0x0
|
||||
#define MC_DC33_VALUE 0x0
|
||||
#define MC_DC34_VALUE 0x0
|
||||
#define MC_DC35_VALUE 0x0
|
||||
#define MC_DC36_VALUE 0x0
|
||||
#define MC_DC37_VALUE 0x0
|
||||
#define MC_DC38_VALUE 0x0
|
||||
#define MC_DC39_VALUE 0x0
|
||||
#define MC_DC40_VALUE 0x0
|
||||
#define MC_DC41_VALUE 0x0
|
||||
#define MC_DC42_VALUE 0x0
|
||||
#define MC_DC43_VALUE 0x0
|
||||
#define MC_DC44_VALUE 0x0
|
||||
#define MC_DC45_VALUE 0x500
|
||||
//#define MC_DC45_VALUE 0x400
|
||||
#define MC_DC46_VALUE 0x0
|
||||
|
|
@ -0,0 +1,622 @@
|
|||
/*
|
||||
* Memory sub-system initialization code for Danube board.
|
||||
* Andre Messerschmidt
|
||||
* Copyright (c) 2005 Infineon Technologies AG
|
||||
*
|
||||
* Based on Inca-IP code
|
||||
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
/* History:
|
||||
peng liu May 25, 2006, for PLL setting after reset, 05252006
|
||||
*/
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/regdef.h>
|
||||
|
||||
#if 0
|
||||
|
||||
#if defined(CONFIG_USE_DDR_RAM)
|
||||
|
||||
#if defined(CONFIG_USE_DDR_RAM_CFG_111M)
|
||||
#include "ddr_settings_r111.h"
|
||||
#define DDR111
|
||||
#elif defined(CONFIG_USE_DDR_RAM_CFG_166M)
|
||||
#include "ddr_settings_r166.h"
|
||||
#define DDR166
|
||||
#elif defined(CONFIG_USE_DDR_RAM_CFG_e111M)
|
||||
#include "ddr_settings_e111.h"
|
||||
#define DDR111
|
||||
#elif defined(CONFIG_USE_DDR_RAM_CFG_e166M)
|
||||
#include "ddr_settings_e166.h"
|
||||
#define DDR166
|
||||
#elif defined(CONFIG_USE_DDR_RAM_CFG_promos400)
|
||||
#include "ddr_settings_PROMOSDDR400.h"
|
||||
#define DDR166
|
||||
#elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166)
|
||||
#include "ddr_settings_Samsung_166.h"
|
||||
#define DDR166
|
||||
#elif defined(CONFIG_USE_DDR_RAM_CFG_psc166)
|
||||
#include "ddr_settings_psc_166.h"
|
||||
#define DDR166
|
||||
#else
|
||||
#warning "missing definition for ddr_settings.h, use default!"
|
||||
#include "ddr_settings.h"
|
||||
#endif
|
||||
#endif /* CONFIG_USE_DDR_RAM */
|
||||
|
||||
#else
|
||||
|
||||
#include "ddr_settings_psc_166.h"
|
||||
#define DDR166
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE)
|
||||
#error "missing include of ddr_settings.h"
|
||||
#endif
|
||||
|
||||
#define EBU_MODUL_BASE 0xBE105300
|
||||
#define EBU_CLC(value) 0x0000(value)
|
||||
#define EBU_CON(value) 0x0010(value)
|
||||
#define EBU_ADDSEL0(value) 0x0020(value)
|
||||
#define EBU_ADDSEL1(value) 0x0024(value)
|
||||
#define EBU_ADDSEL2(value) 0x0028(value)
|
||||
#define EBU_ADDSEL3(value) 0x002C(value)
|
||||
#define EBU_BUSCON0(value) 0x0060(value)
|
||||
#define EBU_BUSCON1(value) 0x0064(value)
|
||||
#define EBU_BUSCON2(value) 0x0068(value)
|
||||
#define EBU_BUSCON3(value) 0x006C(value)
|
||||
|
||||
#define MC_MODUL_BASE 0xBF800000
|
||||
#define MC_ERRCAUSE(value) 0x0010(value)
|
||||
#define MC_ERRADDR(value) 0x0020(value)
|
||||
#define MC_CON(value) 0x0060(value)
|
||||
|
||||
#define MC_SRAM_ENABLE 0x00000004
|
||||
#define MC_SDRAM_ENABLE 0x00000002
|
||||
#define MC_DDRRAM_ENABLE 0x00000001
|
||||
|
||||
#define MC_SDR_MODUL_BASE 0xBF800200
|
||||
#define MC_IOGP(value) 0x0000(value)
|
||||
#define MC_CTRLENA(value) 0x0010(value)
|
||||
#define MC_MRSCODE(value) 0x0020(value)
|
||||
#define MC_CFGDW(value) 0x0030(value)
|
||||
#define MC_CFGPB0(value) 0x0040(value)
|
||||
#define MC_LATENCY(value) 0x0080(value)
|
||||
#define MC_TREFRESH(value) 0x0090(value)
|
||||
#define MC_SELFRFSH(value) 0x00A0(value)
|
||||
|
||||
#define MC_DDR_MODUL_BASE 0xBF801000
|
||||
#define MC_DC00(value) 0x0000(value)
|
||||
#define MC_DC01(value) 0x0010(value)
|
||||
#define MC_DC02(value) 0x0020(value)
|
||||
#define MC_DC03(value) 0x0030(value)
|
||||
#define MC_DC04(value) 0x0040(value)
|
||||
#define MC_DC05(value) 0x0050(value)
|
||||
#define MC_DC06(value) 0x0060(value)
|
||||
#define MC_DC07(value) 0x0070(value)
|
||||
#define MC_DC08(value) 0x0080(value)
|
||||
#define MC_DC09(value) 0x0090(value)
|
||||
#define MC_DC10(value) 0x00A0(value)
|
||||
#define MC_DC11(value) 0x00B0(value)
|
||||
#define MC_DC12(value) 0x00C0(value)
|
||||
#define MC_DC13(value) 0x00D0(value)
|
||||
#define MC_DC14(value) 0x00E0(value)
|
||||
#define MC_DC15(value) 0x00F0(value)
|
||||
#define MC_DC16(value) 0x0100(value)
|
||||
#define MC_DC17(value) 0x0110(value)
|
||||
#define MC_DC18(value) 0x0120(value)
|
||||
#define MC_DC19(value) 0x0130(value)
|
||||
#define MC_DC20(value) 0x0140(value)
|
||||
#define MC_DC21(value) 0x0150(value)
|
||||
#define MC_DC22(value) 0x0160(value)
|
||||
#define MC_DC23(value) 0x0170(value)
|
||||
#define MC_DC24(value) 0x0180(value)
|
||||
#define MC_DC25(value) 0x0190(value)
|
||||
#define MC_DC26(value) 0x01A0(value)
|
||||
#define MC_DC27(value) 0x01B0(value)
|
||||
#define MC_DC28(value) 0x01C0(value)
|
||||
#define MC_DC29(value) 0x01D0(value)
|
||||
#define MC_DC30(value) 0x01E0(value)
|
||||
#define MC_DC31(value) 0x01F0(value)
|
||||
#define MC_DC32(value) 0x0200(value)
|
||||
#define MC_DC33(value) 0x0210(value)
|
||||
#define MC_DC34(value) 0x0220(value)
|
||||
#define MC_DC35(value) 0x0230(value)
|
||||
#define MC_DC36(value) 0x0240(value)
|
||||
#define MC_DC37(value) 0x0250(value)
|
||||
#define MC_DC38(value) 0x0260(value)
|
||||
#define MC_DC39(value) 0x0270(value)
|
||||
#define MC_DC40(value) 0x0280(value)
|
||||
#define MC_DC41(value) 0x0290(value)
|
||||
#define MC_DC42(value) 0x02A0(value)
|
||||
#define MC_DC43(value) 0x02B0(value)
|
||||
#define MC_DC44(value) 0x02C0(value)
|
||||
#define MC_DC45(value) 0x02D0(value)
|
||||
#define MC_DC46(value) 0x02E0(value)
|
||||
|
||||
#define RCU_OFFSET 0xBF203000
|
||||
#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
|
||||
#define RCU_STS (RCU_OFFSET + 0x0014)
|
||||
|
||||
#define CGU_OFFSET 0xBF103000
|
||||
#define PLL0_CFG (CGU_OFFSET + 0x0004)
|
||||
#define PLL1_CFG (CGU_OFFSET + 0x0008)
|
||||
#define PLL2_CFG (CGU_OFFSET + 0x000C)
|
||||
#define CGU_SYS (CGU_OFFSET + 0x0010)
|
||||
#define CGU_UPDATE (CGU_OFFSET + 0x0014)
|
||||
#define IF_CLK (CGU_OFFSET + 0x0018)
|
||||
#define CGU_SMD (CGU_OFFSET + 0x0020)
|
||||
#define CGU_CT1SR (CGU_OFFSET + 0x0028)
|
||||
#define CGU_CT2SR (CGU_OFFSET + 0x002C)
|
||||
#define CGU_PCMCR (CGU_OFFSET + 0x0030)
|
||||
#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
|
||||
#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
|
||||
#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
|
||||
#define CLK_MEASURE (CGU_OFFSET + 0x003C)
|
||||
|
||||
//05252006
|
||||
#define pll0_35MHz_CONFIG 0x9D861059
|
||||
#define pll1_35MHz_CONFIG 0x1A260CD9
|
||||
#define pll2_35MHz_CONFIG 0x8000f1e5
|
||||
#define pll0_36MHz_CONFIG 0x1000125D
|
||||
#define pll1_36MHz_CONFIG 0x1B1E0C99
|
||||
#define pll2_36MHz_CONFIG 0x8002f2a1
|
||||
//05252006
|
||||
|
||||
//06063001-joelin disable the PCI CFRAME mask -start
|
||||
/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
|
||||
But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
|
||||
|
||||
The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
|
||||
The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
|
||||
*/
|
||||
#define PCI_CR_PR_OFFSET 0xBE105400
|
||||
#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
|
||||
#define PCI_CONFIG_SPACE 0xB7000000
|
||||
#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
|
||||
//06063001-joelin disable the PCI CFRAME mask -end
|
||||
.set noreorder
|
||||
|
||||
|
||||
/*
|
||||
* void ebu_init(void)
|
||||
*/
|
||||
.globl ebu_init
|
||||
.ent ebu_init
|
||||
ebu_init:
|
||||
|
||||
#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
|
||||
defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
|
||||
defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
|
||||
defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
|
||||
|
||||
li t1, EBU_MODUL_BASE
|
||||
#if defined(CONFIG_EBU_ADDSEL0)
|
||||
li t2, CONFIG_EBU_ADDSEL0
|
||||
sw t2, EBU_ADDSEL0(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_ADDSEL1)
|
||||
li t2, CONFIG_EBU_ADDSEL1
|
||||
sw t2, EBU_ADDSEL1(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_ADDSEL2)
|
||||
li t2, CONFIG_EBU_ADDSEL2
|
||||
sw t2, EBU_ADDSEL2(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_ADDSEL3)
|
||||
li t2, CONFIG_EBU_ADDSEL3
|
||||
sw t2, EBU_ADDSEL3(t1)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_EBU_BUSCON0)
|
||||
li t2, CONFIG_EBU_BUSCON0
|
||||
sw t2, EBU_BUSCON0(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_BUSCON1)
|
||||
li t2, CONFIG_EBU_BUSCON1
|
||||
sw t2, EBU_BUSCON1(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_BUSCON2)
|
||||
li t2, CONFIG_EBU_BUSCON2
|
||||
sw t2, EBU_BUSCON2(t1)
|
||||
#endif
|
||||
#if defined(CONFIG_EBU_BUSCON3)
|
||||
li t2, CONFIG_EBU_BUSCON3
|
||||
sw t2, EBU_BUSCON3(t1)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end ebu_init
|
||||
|
||||
|
||||
/*
|
||||
* void cgu_init(long)
|
||||
*
|
||||
* a0 has the clock value
|
||||
*/
|
||||
.globl cgu_init
|
||||
.ent cgu_init
|
||||
cgu_init:
|
||||
li t2, CGU_SYS
|
||||
lw t2,0(t2)
|
||||
beq t2,a0,freq_up2date
|
||||
nop
|
||||
|
||||
li t2, RCU_STS
|
||||
lw t2, 0(t2)
|
||||
and t2,0x00020000
|
||||
beq t2,0x00020000,boot_36MHZ
|
||||
nop
|
||||
//05252006
|
||||
li t1, PLL0_CFG
|
||||
li t2, pll0_35MHz_CONFIG
|
||||
sw t2,0(t1)
|
||||
li t1, PLL1_CFG
|
||||
li t2, pll1_35MHz_CONFIG
|
||||
sw t2,0(t1)
|
||||
li t1, PLL2_CFG
|
||||
li t2, pll2_35MHz_CONFIG
|
||||
sw t2,0(t1)
|
||||
li t1, CGU_SYS
|
||||
sw a0,0(t1)
|
||||
li t1, RCU_RST_REQ
|
||||
li t2, 0x40000008
|
||||
sw t2,0(t1)
|
||||
b wait_reset
|
||||
nop
|
||||
boot_36MHZ:
|
||||
li t1, PLL0_CFG
|
||||
li t2, pll0_36MHz_CONFIG
|
||||
sw t2,0(t1)
|
||||
li t1, PLL1_CFG
|
||||
li t2, pll1_36MHz_CONFIG
|
||||
sw t2,0(t1)
|
||||
li t1, PLL2_CFG
|
||||
li t2, pll2_36MHz_CONFIG
|
||||
sw t2,0(t1)
|
||||
li t1, CGU_SYS
|
||||
sw a0,0(t1)
|
||||
li t1, RCU_RST_REQ
|
||||
li t2, 0x40000008
|
||||
sw t2,0(t1)
|
||||
//05252006
|
||||
|
||||
wait_reset:
|
||||
b wait_reset
|
||||
nop
|
||||
freq_up2date:
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end cgu_init
|
||||
|
||||
#ifndef CONFIG_USE_DDR_RAM
|
||||
/*
|
||||
* void sdram_init(long)
|
||||
*
|
||||
* a0 has the clock value
|
||||
*/
|
||||
.globl sdram_init
|
||||
.ent sdram_init
|
||||
sdram_init:
|
||||
|
||||
/* SDRAM Initialization
|
||||
*/
|
||||
li t1, MC_MODUL_BASE
|
||||
|
||||
/* Clear Error log registers */
|
||||
sw zero, MC_ERRCAUSE(t1)
|
||||
sw zero, MC_ERRADDR(t1)
|
||||
|
||||
/* Enable SDRAM module in memory controller */
|
||||
li t3, MC_SDRAM_ENABLE
|
||||
lw t2, MC_CON(t1)
|
||||
or t3, t2, t3
|
||||
sw t3, MC_CON(t1)
|
||||
|
||||
li t1, MC_SDR_MODUL_BASE
|
||||
|
||||
/* disable the controller */
|
||||
li t2, 0
|
||||
sw t2, MC_CTRLENA(t1)
|
||||
|
||||
li t2, 0x822
|
||||
sw t2, MC_IOGP(t1)
|
||||
|
||||
li t2, 0x2
|
||||
sw t2, MC_CFGDW(t1)
|
||||
|
||||
/* Set CAS Latency */
|
||||
li t2, 0x00000020
|
||||
sw t2, MC_MRSCODE(t1)
|
||||
|
||||
/* Set CS0 to SDRAM parameters */
|
||||
li t2, 0x000014d8
|
||||
sw t2, MC_CFGPB0(t1)
|
||||
|
||||
/* Set SDRAM latency parameters */
|
||||
li t2, 0x00036325; /* BC PC100 */
|
||||
sw t2, MC_LATENCY(t1)
|
||||
|
||||
/* Set SDRAM refresh rate */
|
||||
li t2, 0x00000C30
|
||||
sw t2, MC_TREFRESH(t1)
|
||||
|
||||
/* Clear Power-down registers */
|
||||
sw zero, MC_SELFRFSH(t1)
|
||||
|
||||
/* Finally enable the controller */
|
||||
li t2, 1
|
||||
sw t2, MC_CTRLENA(t1)
|
||||
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end sdram_init
|
||||
|
||||
#endif /* !CONFIG_USE_DDR_RAM */
|
||||
|
||||
#ifdef CONFIG_USE_DDR_RAM
|
||||
/*
|
||||
* void ddrram_init(long)
|
||||
*
|
||||
* a0 has the clock value
|
||||
*/
|
||||
.globl ddrram_init
|
||||
.ent ddrram_init
|
||||
ddrram_init:
|
||||
|
||||
/* DDR-DRAM Initialization
|
||||
*/
|
||||
li t1, MC_MODUL_BASE
|
||||
|
||||
/* Clear Error log registers */
|
||||
sw zero, MC_ERRCAUSE(t1)
|
||||
sw zero, MC_ERRADDR(t1)
|
||||
|
||||
/* Enable DDR module in memory controller */
|
||||
li t3, MC_DDRRAM_ENABLE
|
||||
lw t2, MC_CON(t1)
|
||||
or t3, t2, t3
|
||||
sw t3, MC_CON(t1)
|
||||
|
||||
li t1, MC_DDR_MODUL_BASE
|
||||
|
||||
/* Write configuration to DDR controller registers */
|
||||
li t2, MC_DC0_VALUE
|
||||
sw t2, MC_DC00(t1)
|
||||
|
||||
li t2, MC_DC1_VALUE
|
||||
sw t2, MC_DC01(t1)
|
||||
|
||||
li t2, MC_DC2_VALUE
|
||||
sw t2, MC_DC02(t1)
|
||||
|
||||
li t2, MC_DC3_VALUE
|
||||
sw t2, MC_DC03(t1)
|
||||
|
||||
li t2, MC_DC4_VALUE
|
||||
sw t2, MC_DC04(t1)
|
||||
|
||||
li t2, MC_DC5_VALUE
|
||||
sw t2, MC_DC05(t1)
|
||||
|
||||
li t2, MC_DC6_VALUE
|
||||
sw t2, MC_DC06(t1)
|
||||
|
||||
li t2, MC_DC7_VALUE
|
||||
sw t2, MC_DC07(t1)
|
||||
|
||||
li t2, MC_DC8_VALUE
|
||||
sw t2, MC_DC08(t1)
|
||||
|
||||
li t2, MC_DC9_VALUE
|
||||
sw t2, MC_DC09(t1)
|
||||
|
||||
li t2, MC_DC10_VALUE
|
||||
sw t2, MC_DC10(t1)
|
||||
|
||||
li t2, MC_DC11_VALUE
|
||||
sw t2, MC_DC11(t1)
|
||||
|
||||
li t2, MC_DC12_VALUE
|
||||
sw t2, MC_DC12(t1)
|
||||
|
||||
li t2, MC_DC13_VALUE
|
||||
sw t2, MC_DC13(t1)
|
||||
|
||||
li t2, MC_DC14_VALUE
|
||||
sw t2, MC_DC14(t1)
|
||||
|
||||
li t2, MC_DC15_VALUE
|
||||
sw t2, MC_DC15(t1)
|
||||
|
||||
li t2, MC_DC16_VALUE
|
||||
sw t2, MC_DC16(t1)
|
||||
|
||||
li t2, MC_DC17_VALUE
|
||||
sw t2, MC_DC17(t1)
|
||||
|
||||
li t2, MC_DC18_VALUE
|
||||
sw t2, MC_DC18(t1)
|
||||
|
||||
li t2, MC_DC19_VALUE
|
||||
sw t2, MC_DC19(t1)
|
||||
|
||||
li t2, MC_DC20_VALUE
|
||||
sw t2, MC_DC20(t1)
|
||||
|
||||
li t2, MC_DC21_VALUE
|
||||
sw t2, MC_DC21(t1)
|
||||
|
||||
li t2, MC_DC22_VALUE
|
||||
sw t2, MC_DC22(t1)
|
||||
|
||||
li t2, MC_DC23_VALUE
|
||||
sw t2, MC_DC23(t1)
|
||||
|
||||
li t2, MC_DC24_VALUE
|
||||
sw t2, MC_DC24(t1)
|
||||
|
||||
li t2, MC_DC25_VALUE
|
||||
sw t2, MC_DC25(t1)
|
||||
|
||||
li t2, MC_DC26_VALUE
|
||||
sw t2, MC_DC26(t1)
|
||||
|
||||
li t2, MC_DC27_VALUE
|
||||
sw t2, MC_DC27(t1)
|
||||
|
||||
li t2, MC_DC28_VALUE
|
||||
sw t2, MC_DC28(t1)
|
||||
|
||||
li t2, MC_DC29_VALUE
|
||||
sw t2, MC_DC29(t1)
|
||||
|
||||
li t2, MC_DC30_VALUE
|
||||
sw t2, MC_DC30(t1)
|
||||
|
||||
li t2, MC_DC31_VALUE
|
||||
sw t2, MC_DC31(t1)
|
||||
|
||||
li t2, MC_DC32_VALUE
|
||||
sw t2, MC_DC32(t1)
|
||||
|
||||
li t2, MC_DC33_VALUE
|
||||
sw t2, MC_DC33(t1)
|
||||
|
||||
li t2, MC_DC34_VALUE
|
||||
sw t2, MC_DC34(t1)
|
||||
|
||||
li t2, MC_DC35_VALUE
|
||||
sw t2, MC_DC35(t1)
|
||||
|
||||
li t2, MC_DC36_VALUE
|
||||
sw t2, MC_DC36(t1)
|
||||
|
||||
li t2, MC_DC37_VALUE
|
||||
sw t2, MC_DC37(t1)
|
||||
|
||||
li t2, MC_DC38_VALUE
|
||||
sw t2, MC_DC38(t1)
|
||||
|
||||
li t2, MC_DC39_VALUE
|
||||
sw t2, MC_DC39(t1)
|
||||
|
||||
li t2, MC_DC40_VALUE
|
||||
sw t2, MC_DC40(t1)
|
||||
|
||||
li t2, MC_DC41_VALUE
|
||||
sw t2, MC_DC41(t1)
|
||||
|
||||
li t2, MC_DC42_VALUE
|
||||
sw t2, MC_DC42(t1)
|
||||
|
||||
li t2, MC_DC43_VALUE
|
||||
sw t2, MC_DC43(t1)
|
||||
|
||||
li t2, MC_DC44_VALUE
|
||||
sw t2, MC_DC44(t1)
|
||||
|
||||
li t2, MC_DC45_VALUE
|
||||
sw t2, MC_DC45(t1)
|
||||
|
||||
li t2, MC_DC46_VALUE
|
||||
sw t2, MC_DC46(t1)
|
||||
|
||||
li t2, 0x00000100
|
||||
sw t2, MC_DC03(t1)
|
||||
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end ddrram_init
|
||||
#endif /* CONFIG_USE_DDR_RAM */
|
||||
|
||||
.globl lowlevel_init
|
||||
.ent lowlevel_init
|
||||
lowlevel_init:
|
||||
/* EBU, CGU and SDRAM/DDR-RAM Initialization.
|
||||
*/
|
||||
move t0, ra
|
||||
/* We rely on the fact that non of the following ..._init() functions
|
||||
* modify t0
|
||||
*/
|
||||
#if defined(CONFIG_SYS_EBU_BOOT)
|
||||
#if defined(DDR166)
|
||||
/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
|
||||
li a0,0xe8
|
||||
#elif defined(DDR133)
|
||||
/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
|
||||
li a0,0xe9
|
||||
#else /* defined(DDR111) */
|
||||
/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
|
||||
li a0,0xea
|
||||
#endif
|
||||
bal cgu_init
|
||||
nop
|
||||
#endif /* CONFIG_SYS_EBU_BOOT */
|
||||
|
||||
bal ebu_init
|
||||
nop
|
||||
|
||||
//06063001-joelin disable the PCI CFRAME mask-start
|
||||
#ifdef DISABLE_CFRAME
|
||||
li t1, PCI_CR_PCI //mw bf103034 80000000
|
||||
li t2, 0x80000000
|
||||
sw t2,0(t1)
|
||||
|
||||
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
|
||||
li t2, 0x103
|
||||
sw t2,0(t1)
|
||||
|
||||
li t1, CS_CFM //mw b700006c 0
|
||||
li t2, 0x00
|
||||
sw t2, 0(t1)
|
||||
|
||||
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
|
||||
li t2, 0x1000103
|
||||
sw t2, 0(t1)
|
||||
#endif
|
||||
//06063001-joelin disable the PCI CFRAME mask-end
|
||||
|
||||
#ifdef CONFIG_SYS_EBU_BOOT
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
#ifdef CONFIG_USE_DDR_RAM
|
||||
bal ddrram_init
|
||||
nop
|
||||
#else
|
||||
bal sdram_init
|
||||
nop
|
||||
#endif
|
||||
#endif /* CONFIG_SYS_RAMBOOT */
|
||||
#endif /* CONFIG_SYS_EBU_BOOT */
|
||||
|
||||
move ra, t0
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end lowlevel_init
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Power Management unit initialization code for AMAZON development board.
|
||||
*
|
||||
* Copyright (c) 2003 Ou Ke, Infineon.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/regdef.h>
|
||||
|
||||
#define PMU_PWDCR 0xBF10201C
|
||||
#define PMU_SR 0xBF102020
|
||||
|
||||
.globl pmuenable
|
||||
|
||||
pmuenable:
|
||||
li t0, PMU_PWDCR
|
||||
li t1, 0x2 /* enable everything */
|
||||
sw t1, 0(t0)
|
||||
#if 0
|
||||
1:
|
||||
li t0, PMU_SR
|
||||
lw t2, 0(t0)
|
||||
bne t1, t2, 1b
|
||||
nop
|
||||
#endif
|
||||
j ra
|
||||
nop
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk Engineering, <wd@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
|
||||
*/
|
||||
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = .;
|
||||
_gp = ALIGN(16) + 0x7ff0;
|
||||
|
||||
.got : {
|
||||
__got_start = .;
|
||||
*(.got)
|
||||
__got_end = .;
|
||||
}
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
.u_boot_cmd : {
|
||||
__u_boot_cmd_start = .;
|
||||
*(.u_boot_cmd)
|
||||
__u_boot_cmd_end = .;
|
||||
}
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss (NOLOAD) : { *(.sbss) }
|
||||
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
|
||||
uboot_end = .;
|
||||
}
|
||||
152
package/uboot-lantiq/files/include/configs/arv4518.h
Normal file
152
package/uboot-lantiq/files/include/configs/arv4518.h
Normal file
|
|
@ -0,0 +1,152 @@
|
|||
/*
|
||||
* (C) Copyright 2003-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file contains the configuration parameters for the Danube reference board.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* #define DEBUG */
|
||||
|
||||
#define CONFIG_MIPS32 1 /* MIPS32 CPU compatible */
|
||||
#define CONFIG_MIPS24KEC 1 /* MIPS 24KEc CPU core */
|
||||
#define CONFIG_DANUBE 1 /* in a Danube/Twinpass Chip */
|
||||
#define CONFIG_ARV4518 1 /* on the arv4518 Board */
|
||||
|
||||
#define CONFIG_SYS_MIPS_MULTI_CPU 1 /* This is a multi cpu system */
|
||||
|
||||
#define CONFIG_USE_DDR_RAM
|
||||
#define CONFIG_SYS_MAX_RAM 64*1024*1024
|
||||
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK_MIPS
|
||||
|
||||
#ifdef CONFIG_SYS_RAMBOOT
|
||||
//#warning CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#else /* CONFIG_SYS_RAMBOOT */
|
||||
#define CONFIG_SYS_EBU_BOOT
|
||||
#define INFINEON_EBU_BOOTCFG 0x688C688C /* CMULT = 8 for 150 MHz */
|
||||
#endif /* CONFIG_SYS_RAMBOOT */
|
||||
|
||||
#if 1
|
||||
#ifndef CPU_CLOCK_RATE
|
||||
#define CPU_CLOCK_RATE (ifx_get_cpuclk())
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_PROMPT "ARV4518 => " /* Monitor Command Prompt */
|
||||
|
||||
#undef CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
|
||||
|
||||
/*
|
||||
* Include common defines/options for all Infineon boards
|
||||
*/
|
||||
#include "ifx-common.h"
|
||||
|
||||
|
||||
#undef CONFIG_EXTRA_ENV_SETTINGS
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"ram_addr=0x80500000\0" \
|
||||
"kernel_addr=0xb0050000\0" \
|
||||
"mtdparts=mtdparts=ifx-nor:256k(uboot)ro,64k(uboot_env)ro,64k(kernel),-(rootfs)\0" \
|
||||
"flashargs=setenv bootargs rootfstype=squashfs,jffs2\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath} \0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off\0" \
|
||||
"addmisc=setenv bootargs ${bootargs} init=/etc/preinit " \
|
||||
"console=ttyS1,115200 ethaddr=${ethaddr} " \
|
||||
"${mtdparts}\0" \
|
||||
"flash_flash=run flashargs addip addmisc;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_nfs=run nfsargs addip addmisc;bootm ${kernel_addr}\0" \
|
||||
"net_flash=run load_kernel flashargs addip addmisc;" \
|
||||
"bootm ${ram_addr}\0" \
|
||||
"net_nfs=run load_kernel nfsargs addip addmisc;" \
|
||||
"bootm ${ram_addr}\0" \
|
||||
"load_kernel=tftp ${ram_addr} " \
|
||||
"${tftppath}openwrt-ifxmips-uImage\0" \
|
||||
"update_uboot=tftp 0x80500000 ${tftppath}u-boot.bin;era 0xb0000000 +${filesize};" \
|
||||
"cp.b 0x80500000 0xb0000000 ${filesize}\0" \
|
||||
"update_openwrt=tftp ${ram_addr} " \
|
||||
"${tftppath}openwrt-ifxmips-squashfs.image;" \
|
||||
"era ${kernel_addr} +${filesize};" \
|
||||
"cp.b ${ram_addr} ${kernel_addr} ${filesize}\0"
|
||||
|
||||
/*
|
||||
* Cache Configuration (cpu/chip specific, Danube)
|
||||
*/
|
||||
#define CONFIG_SYS_DCACHE_SIZE 16384
|
||||
#define CONFIG_SYS_ICACHE_SIZE 16384
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
#define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NO_WA
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#if 0
|
||||
#define CONFIG_M4530_ETH
|
||||
#define CONFIG_M4530_FPGA
|
||||
#endif
|
||||
|
||||
#define CONFIG_IFX_ETOP
|
||||
//#define CLK_OUT2_25MHZ
|
||||
#define CONFIG_EXTRA_SWITCH
|
||||
|
||||
//#define CONFIG_RMII /* use interface in RMII mode */
|
||||
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_CMD_MII
|
||||
|
||||
#define CONFIG_IFX_ASC
|
||||
|
||||
#ifdef CONFIG_USE_ASC0
|
||||
#define CONFIG_SYS_IFX_ASC_BASE 0x1E100400
|
||||
#else
|
||||
#define CONFIG_SYS_IFX_ASC_BASE 0x1E100C00
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_RAMBOOT
|
||||
/* Configuration of EBU: */
|
||||
/* starting address from 0xb0000000 */
|
||||
/* make the flash available from RAM boot */
|
||||
# define CONFIG_EBU_ADDSEL0 0x10000031
|
||||
# define CONFIG_EBU_BUSCON0 0x0001D7FF
|
||||
# define CONFIG_EBU_ADDSEL1 0x14000001
|
||||
# define CONFIG_EBU_BUSCON1 0x4041D7FD
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMD_HTTPD /* enable upgrade via HTTPD */
|
||||
|
||||
//#define CONFIG_ETHADDR 00:13:f7:df:1c:80
|
||||
//#define CONFIG_ETHADDR 11:22:33:44:55:66
|
||||
#define CONFIG_IPADDR 192.168.2.1
|
||||
#define CONFIG_SERVERIP 192.168.2.101
|
||||
#define CONFIG_GATEWAYIP 192.168.2.254
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_ROOTPATH "/export"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
152
package/uboot-lantiq/files/include/configs/arv752DWP22.h
Normal file
152
package/uboot-lantiq/files/include/configs/arv752DWP22.h
Normal file
|
|
@ -0,0 +1,152 @@
|
|||
/*
|
||||
* (C) Copyright 2003-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file contains the configuration parameters for the Danube reference board.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* #define DEBUG */
|
||||
|
||||
#define CONFIG_MIPS32 1 /* MIPS32 CPU compatible */
|
||||
#define CONFIG_MIPS24KEC 1 /* MIPS 24KEc CPU core */
|
||||
#define CONFIG_DANUBE 1 /* in a Danube/Twinpass Chip */
|
||||
#define CONFIG_ARV752DWP22 1 /* on the arv752DWP22 Board */
|
||||
|
||||
#define CONFIG_SYS_MIPS_MULTI_CPU 1 /* This is a multi cpu system */
|
||||
|
||||
#define CONFIG_USE_DDR_RAM
|
||||
#define CONFIG_SYS_MAX_RAM 64*1024*1024
|
||||
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK_MIPS
|
||||
|
||||
#ifdef CONFIG_SYS_RAMBOOT
|
||||
//#warning CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#else /* CONFIG_SYS_RAMBOOT */
|
||||
#define CONFIG_SYS_EBU_BOOT
|
||||
#define INFINEON_EBU_BOOTCFG 0x688C688C /* CMULT = 8 for 150 MHz */
|
||||
#endif /* CONFIG_SYS_RAMBOOT */
|
||||
|
||||
#if 1
|
||||
#ifndef CPU_CLOCK_RATE
|
||||
#define CPU_CLOCK_RATE (ifx_get_cpuclk())
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_PROMPT "ARV752DWP22 => " /* Monitor Command Prompt */
|
||||
|
||||
#undef CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
|
||||
|
||||
/*
|
||||
* Include common defines/options for all Infineon boards
|
||||
*/
|
||||
#include "ifx-common.h"
|
||||
|
||||
|
||||
#undef CONFIG_EXTRA_ENV_SETTINGS
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"ram_addr=0x80500000\0" \
|
||||
"kernel_addr=0xb0050000\0" \
|
||||
"mtdparts=mtdparts=ifx-nor:256k(uboot)ro,64k(uboot_env)ro,64k(kernel),-(rootfs)\0" \
|
||||
"flashargs=setenv bootargs rootfstype=squashfs,jffs2\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath} \0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off\0" \
|
||||
"addmisc=setenv bootargs ${bootargs} init=/etc/preinit " \
|
||||
"console=ttyS1,115200 ethaddr=${ethaddr} " \
|
||||
"${mtdparts}\0" \
|
||||
"flash_flash=run flashargs addip addmisc;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_nfs=run nfsargs addip addmisc;bootm ${kernel_addr}\0" \
|
||||
"net_flash=run load_kernel flashargs addip addmisc;" \
|
||||
"bootm ${ram_addr}\0" \
|
||||
"net_nfs=run load_kernel nfsargs addip addmisc;" \
|
||||
"bootm ${ram_addr}\0" \
|
||||
"load_kernel=tftp ${ram_addr} " \
|
||||
"${tftppath}openwrt-ifxmips-uImage\0" \
|
||||
"update_uboot=tftp 0x80500000 ${tftppath}u-boot.bin;era 0xb0000000 +${filesize};" \
|
||||
"cp.b 0x80500000 0xb0000000 ${filesize}\0" \
|
||||
"update_openwrt=tftp ${ram_addr} " \
|
||||
"${tftppath}openwrt-ifxmips-squashfs.image;" \
|
||||
"era ${kernel_addr} +${filesize};" \
|
||||
"cp.b ${ram_addr} ${kernel_addr} ${filesize}\0"
|
||||
|
||||
/*
|
||||
* Cache Configuration (cpu/chip specific, Danube)
|
||||
*/
|
||||
#define CONFIG_SYS_DCACHE_SIZE 16384
|
||||
#define CONFIG_SYS_ICACHE_SIZE 16384
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
#define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NO_WA
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#if 0
|
||||
#define CONFIG_M4530_ETH
|
||||
#define CONFIG_M4530_FPGA
|
||||
#endif
|
||||
|
||||
#define CONFIG_IFX_ETOP
|
||||
//#define CLK_OUT2_25MHZ
|
||||
#define CONFIG_EXTRA_SWITCH
|
||||
|
||||
//#define CONFIG_RMII /* use interface in RMII mode */
|
||||
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_CMD_MII
|
||||
|
||||
#define CONFIG_IFX_ASC
|
||||
|
||||
#ifdef CONFIG_USE_ASC0
|
||||
#define CONFIG_SYS_IFX_ASC_BASE 0x1E100400
|
||||
#else
|
||||
#define CONFIG_SYS_IFX_ASC_BASE 0x1E100C00
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_RAMBOOT
|
||||
/* Configuration of EBU: */
|
||||
/* starting address from 0xb0000000 */
|
||||
/* make the flash available from RAM boot */
|
||||
# define CONFIG_EBU_ADDSEL0 0x10000031
|
||||
# define CONFIG_EBU_BUSCON0 0x0001D7FF
|
||||
# define CONFIG_EBU_ADDSEL1 0x14000001
|
||||
# define CONFIG_EBU_BUSCON1 0x4041D7FD
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMD_HTTPD /* enable upgrade via HTTPD */
|
||||
|
||||
//#define CONFIG_ETHADDR 00:13:f7:df:1c:80
|
||||
//#define CONFIG_ETHADDR 11:22:33:44:55:66
|
||||
#define CONFIG_IPADDR 192.168.2.1
|
||||
#define CONFIG_SERVERIP 192.168.2.101
|
||||
#define CONFIG_GATEWAYIP 192.168.2.254
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_ROOTPATH "/export"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
102
package/uboot-lantiq/patches/500-arcadyan.patch
Normal file
102
package/uboot-lantiq/patches/500-arcadyan.patch
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
--- a/common/Makefile
|
||||
+++ b/common/Makefile
|
||||
@@ -127,7 +127,9 @@
|
||||
ifdef CONFIG_PCI
|
||||
COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o
|
||||
endif
|
||||
+ifdef CONFIG_CMD_PCMCIA
|
||||
COBJS-y += cmd_pcmcia.o
|
||||
+endif
|
||||
COBJS-$(CONFIG_CMD_PORTIO) += cmd_portio.o
|
||||
COBJS-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o
|
||||
COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o
|
||||
--- a/drivers/pcmcia/Makefile
|
||||
+++ b/drivers/pcmcia/Makefile
|
||||
@@ -28,9 +28,11 @@
|
||||
COBJS-$(CONFIG_I82365) += i82365.o
|
||||
COBJS-$(CONFIG_8xx) += mpc8xx_pcmcia.o
|
||||
COBJS-$(CONFIG_PXA_PCMCIA) += pxa_pcmcia.o
|
||||
-COBJS-y += rpx_pcmcia.o
|
||||
+#COBJS-y += rpx_pcmcia.o
|
||||
+COBJS-$(CONFIG_RPX_PCMCIA) += rpx_pcmcia.o
|
||||
COBJS-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o
|
||||
-COBJS-y += tqm8xx_pcmcia.o
|
||||
+#COBJS-y += tqm8xx_pcmcia.o
|
||||
+COBJS-$(CONFIG_TQM8XX_PCMCIA) += tqm8xx_pcmcia.o
|
||||
COBJS-$(CONFIG_MARUBUN_PCCARD) += marubun_pcmcia.o
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
--- a/drivers/usb/phy/Makefile
|
||||
+++ b/drivers/usb/phy/Makefile
|
||||
@@ -23,7 +23,7 @@
|
||||
LIB := $(obj)libusb_phy.a
|
||||
|
||||
COBJS-$(CONFIG_TWL4030_USB) += twl4030.o
|
||||
-COBJS-y := twl4030.o
|
||||
+#COBJS-y := twl4030.o
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
--- a/Makefile
|
||||
+++ b/Makefile
|
||||
@@ -3414,6 +3414,46 @@
|
||||
## MIPS32 ifxcpe
|
||||
#########################################################################
|
||||
|
||||
+arv752DWP22%config : unconfig
|
||||
+ @mkdir -p $(obj)include
|
||||
+ @mkdir -p $(obj)board/arcadyan/arv752DWP22
|
||||
+ @[ -z "$(findstring brnboot,$@)" ] || \
|
||||
+ { echo "TEXT_BASE = 0x80002000" >$(obj)board/arcadyan/arv752DWP22/config.tmp ; \
|
||||
+ echo "#define CONFIG_SYS_RAMBOOT" >>$(obj)include/config.h ; \
|
||||
+ echo "#define CONFIG_SYS_BRNBOOT" >>$(obj)include/config.h ; \
|
||||
+ $(XECHO) "... with brnboot configuration" ; \
|
||||
+ }
|
||||
+ @[ -z "$(findstring ramboot,$@)" ] || \
|
||||
+ { echo "TEXT_BASE = 0xA0400000" >$(obj)board/arcadyan/arv752DWP22/config.tmp ; \
|
||||
+ echo "#define CONFIG_SYS_RAMBOOT" >>$(obj)include/config.h ; \
|
||||
+ $(XECHO) "... with ramboot configuration" ; \
|
||||
+ }
|
||||
+ @if [ "$(findstring flash,$@)" ] ; then \
|
||||
+ echo "#define CONFIG_USE_DDR_RAM" >>$(obj)include/config.h ; \
|
||||
+ echo "#define CONFIG_USE_DDR_RAM_CFG_DDR_psc166" >>$(obj)include/config.h ; \
|
||||
+ fi
|
||||
+ @$(MKCONFIG) -a $(word 1,$(subst _, ,$@)) mips mips arv752DWP22 arcadyan danube
|
||||
+
|
||||
+arv4518%config : unconfig
|
||||
+ @mkdir -p $(obj)include
|
||||
+ @mkdir -p $(obj)board/arcadyan/arv4518
|
||||
+ @[ -z "$(findstring brnboot,$@)" ] || \
|
||||
+ { echo "TEXT_BASE = 0x80002000" >$(obj)board/arcadyan/arv4518/config.tmp ; \
|
||||
+ echo "#define CONFIG_SYS_RAMBOOT" >>$(obj)include/config.h ; \
|
||||
+ echo "#define CONFIG_SYS_BRNBOOT" >>$(obj)include/config.h ; \
|
||||
+ $(XECHO) "... with brnboot configuration" ; \
|
||||
+ }
|
||||
+ @[ -z "$(findstring ramboot,$@)" ] || \
|
||||
+ { echo "TEXT_BASE = 0xA0400000" >$(obj)board/arcadyan/arv4518/config.tmp ; \
|
||||
+ echo "#define CONFIG_SYS_RAMBOOT" >>$(obj)include/config.h ; \
|
||||
+ $(XECHO) "... with ramboot configuration" ; \
|
||||
+ }
|
||||
+ @if [ "$(findstring flash,$@)" ] ; then \
|
||||
+ echo "#define CONFIG_USE_DDR_RAM" >>$(obj)include/config.h ; \
|
||||
+ echo "#define CONFIG_USE_DDR_RAM_CFG_DDR_psc166" >>$(obj)include/config.h ; \
|
||||
+ fi
|
||||
+ @$(MKCONFIG) -a $(word 1,$(subst _, ,$@)) mips mips arv4518 arcadyan danube
|
||||
+
|
||||
easy50712%config : unconfig
|
||||
@mkdir -p $(obj)include
|
||||
@mkdir -p $(obj)board/infineon/easy50712
|
||||
--- a/net/tftp.c
|
||||
+++ b/net/tftp.c
|
||||
@@ -11,9 +11,9 @@
|
||||
#include "bootp.h"
|
||||
|
||||
#define WELL_KNOWN_PORT 69 /* Well known TFTP port # */
|
||||
-#define TIMEOUT 5000UL /* Millisecs to timeout for lost pkt */
|
||||
+#define TIMEOUT 10000UL /* Millisecs to timeout for lost pkt */
|
||||
#ifndef CONFIG_NET_RETRY_COUNT
|
||||
-# define TIMEOUT_COUNT 10 /* # of timeouts before giving up */
|
||||
+# define TIMEOUT_COUNT 200 /* # of timeouts before giving up */
|
||||
#else
|
||||
# define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT * 2)
|
||||
#endif
|
||||
Loading…
Reference in a new issue