ar71xx: fix lan ports on archer C59 and C60

Signed-off-by: Henryk Heisig <hyniu@o2.pl>
This commit is contained in:
Henryk Heisig 2017-02-16 15:22:49 +01:00 committed by John Crispin
parent ab20c638b6
commit d6baeb5c48
4 changed files with 40 additions and 15 deletions

View file

@ -51,8 +51,8 @@ antrouter-r1)
;; ;;
archer-c59-v1|\ archer-c59-v1|\
archer-c60-v1) archer-c60-v1)
ucidef_set_led_switch "lan" "LAN" "$board:green:lan" "switch0" "0x3C" ucidef_set_led_switch "lan" "LAN" "$board:green:lan" "switch0" "0x1E"
ucidef_set_led_switch "wan" "WAN" "$board:green:wan" "switch0" "0x02" ucidef_set_led_netdev "wan" "WAN" "$board:green:wan" "eth0"
ucidef_set_led_wlan "wlan" "WLAN" "$board:green:wlan2g" "phy1tpt" ucidef_set_led_wlan "wlan" "WLAN" "$board:green:wlan2g" "phy1tpt"
ucidef_set_led_wlan "wlan5g" "WLAN5G" "$board:green:wlan5g" "phy0tpt" ucidef_set_led_wlan "wlan5g" "WLAN5G" "$board:green:wlan5g" "phy0tpt"

View file

@ -206,9 +206,15 @@ ar71xx_setup_interfaces()
"0@eth1" "2:lan" "3:lan" "4:lan" "5:lan" "6@eth0" "1:wan" "0@eth1" "2:lan" "3:lan" "4:lan" "5:lan" "6@eth0" "1:wan"
;; ;;
archer-c59-v1|\ archer-c59-v1|\
archer-c60-v1) rb-450g)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0"
ucidef_add_switch "switch0" \ ucidef_add_switch "switch0" \
"0@eth0" "2:lan:4" "3:lan:3" "4:lan:2" "5:lan:1" "1:wan" "0@eth1" "1:lan:1" "2:lan:4" "3:lan:3" "4:lan:2"
;;
archer-c60-v1)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0"
ucidef_add_switch "switch0" \
"0@eth1" "1:lan:1" "2:lan:2" "3:lan:3" "4:lan:4"
;; ;;
arduino-yun|\ arduino-yun|\
dir-505-a1|\ dir-505-a1|\
@ -374,11 +380,6 @@ ar71xx_setup_interfaces()
ucidef_add_switch "switch0" \ ucidef_add_switch "switch0" \
"0:lan:4" "1:lan:3" "2:lan:2" "3:lan:1" "5@eth1" "0:lan:4" "1:lan:3" "2:lan:2" "3:lan:1" "5@eth1"
;; ;;
rb-450g)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0"
ucidef_add_switch "switch0" \
"0@eth1" "1:lan:1" "2:lan:4" "3:lan:3" "4:lan:2"
;;
routerstation-pro) routerstation-pro)
ucidef_set_interfaces_lan_wan "eth1.1" "eth0" ucidef_set_interfaces_lan_wan "eth1.1" "eth0"
ucidef_add_switch "switch0" \ ucidef_add_switch "switch0" \

View file

@ -194,19 +194,33 @@ static void __init archer_c59_v1_setup(void)
ARRAY_SIZE(archer_c59_v1_gpio_keys), ARRAY_SIZE(archer_c59_v1_gpio_keys),
archer_c59_v1_gpio_keys); archer_c59_v1_gpio_keys);
ath79_setup_qca956x_eth_cfg(QCA956X_ETH_CFG_SW_PHY_SWAP |
QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(1, 0x0); ath79_register_mdio(1, 0x0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
/* WAN port */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(0);
ath79_register_eth(0);
/* LAN ports */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000; ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL; ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_data.phy_mask = BIT(4); ath79_switch_data.phy_poll_mask |= BIT(4);
ath79_switch_data.phy4_mii_en = 1;
ath79_register_eth(1); ath79_register_eth(1);
ath79_register_wmac(art + ARCHER_C59_V1_WMAC_CALDATA_OFFSET, mac); ath79_register_wmac(art + ARCHER_C59_V1_WMAC_CALDATA_OFFSET, mac);
ap91_pci_init(art + ARCHER_C59_V1_PCI_CALDATA_OFFSET, NULL); ap91_pci_init(art + ARCHER_C59_V1_PCI_CALDATA_OFFSET, NULL);
ath79_register_usb(); ath79_register_usb();
gpio_request_one(ARCHER_C59_V1_GPIO_USB_POWER, gpio_request_one(ARCHER_C59_V1_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,

View file

@ -116,15 +116,25 @@ static void __init archer_c60_v1_setup(void)
ARRAY_SIZE(archer_c60_v1_gpio_keys), ARRAY_SIZE(archer_c60_v1_gpio_keys),
archer_c60_v1_gpio_keys); archer_c60_v1_gpio_keys);
ath79_setup_qca956x_eth_cfg(QCA956X_ETH_CFG_SW_PHY_SWAP | ath79_register_mdio(0, 0x0);
QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP);
ath79_register_mdio(1, 0x0); ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
/* WAN port */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(4);
ath79_register_eth(0);
/* LAN ports */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000; ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL; ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_switch_data.phy_poll_mask |= BIT(4);
ath79_switch_data.phy4_mii_en = 1;
ath79_register_eth(1); ath79_register_eth(1);
ath79_register_wmac(art + ARCHER_C60_V1_WMAC_CALDATA_OFFSET, mac); ath79_register_wmac(art + ARCHER_C60_V1_WMAC_CALDATA_OFFSET, mac);