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ath79: ar913x: fix eth pll register

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PLL for eth0 internal clock on ar913x is at 0x18050014
and AR913X_ETH0_PLL_SHIFT is 20 instead of 17

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
This commit is contained in:
Chuanhong Guo 2018-08-12 21:13:31 +08:00 committed by Mathias Kresin
parent 42b3fdf981
commit cf50f72069
1 changed files with 1 additions and 1 deletions
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2
target/linux/ath79/dts/ar9132.dtsi
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@ -189,7 +189,7 @@
reg = <0x19000000 0x200 reg = <0x19000000 0x200
0x18070000 0x4>; 0x18070000 0x4>;
pll-data = <0x1a000000 0x13000a44 0x00441099>; pll-data = <0x1a000000 0x13000a44 0x00441099>;
pll-reg = <0x4 0x10 17>; pll-reg = <0x4 0x14 20>;
pll-handle = <&pll>; pll-handle = <&pll>;
resets = <&rst 9>; resets = <&rst 9>;
reset-names = "mac"; reset-names = "mac";