ath79: ar913x: fix eth pll register
PLL for eth0 internal clock on ar913x is at 0x18050014 and AR913X_ETH0_PLL_SHIFT is 20 instead of 17 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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@ -189,7 +189,7 @@
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reg = <0x19000000 0x200
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0x18070000 0x4>;
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pll-data = <0x1a000000 0x13000a44 0x00441099>;
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pll-reg = <0x4 0x10 17>;
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pll-reg = <0x4 0x14 20>;
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pll-handle = <&pll>;
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resets = <&rst 9>;
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reset-names = "mac";
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