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ath9k: add back missing fixes from the last version

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Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 42701
This commit is contained in:
Felix Fietkau 2014-09-29 18:51:25 +00:00
parent 6e2262898f
commit cbc069f9c1
7 changed files with 193 additions and 15 deletions
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180
package/kernel/mac80211/patches/300-pending_work.patch
View file

@ -1,3 +1,53 @@
commit fdf9a4517b60d847b9bc0a30249efd96559fa450
Author: Felix Fietkau <nbd@openwrt.org>
Date: Tue Sep 9 09:48:30 2014 +0200
ath9k_hw: fix PLL clock initialization for newer SoC
On AR934x and newer SoC devices, the layout of the AR_RTC_PLL_CONTROL
register changed. This currently breaks at least 5/10 MHz operation.
AR933x uses the old layout.
It might also have been causing other stability issues because of the
different location of the PLL_BYPASS bit which needs to be set during
PLL clock initialization.
This patch also removes more instances of hardcoded register values in
favor of properly computed ones with the PLL_BYPASS bit added.
Reported-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
commit b6d1f51cd8bdc9d952147a960fbf1f261d8e4188
Author: Felix Fietkau <nbd@openwrt.org>
Date: Mon Sep 8 18:35:08 2014 +0200
ath9k_hw: reduce ANI spur immunity setting on HT40 extension channel
The cycpwr_thr1 value needs to be lower on the extension channel than on
the control channel, similar to how the register settings are programmed
in the initvals.
Also drop the unnecessary check for HT40 - this register can always be
written. This patch has been reported to improve HT40 stability and
throughput in some environments.
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
commit 5ad2dfbaa19aa45d29184d30c8c5dae0e110074a
Author: Felix Fietkau <nbd@openwrt.org>
Date: Mon Sep 8 18:31:26 2014 +0200
Revert "ath9k_hw: reduce ANI firstep range for older chips"
This reverts commit 09efc56345be4146ab9fc87a55c837ed5d6ea1ab
I've received reports that this change is decreasing throughput in some
rare conditions on an AR9280 based device
Cc: stable@vger.kernel.org
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
commit 4c82fc569cf2f29e6c66d98ef4a1b0f3b6a98e9d
Author: Felix Fietkau <nbd@openwrt.org>
Date: Sat Sep 27 22:39:27 2014 +0200
@ -476,7 +526,44 @@ Date: Sat Sep 27 15:57:09 2014 +0200
return;
}
@@ -1192,9 +1189,12 @@ static void ath9k_hw_set_operating_mode(
@@ -704,6 +701,8 @@ static void ath9k_hw_init_pll(struct ath
{
u32 pll;
+ pll = ath9k_hw_compute_pll_control(ah, chan);
+
if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
/* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
@@ -754,7 +753,8 @@ static void ath9k_hw_init_pll(struct ath
REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
- REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
+ REG_WRITE(ah, AR_RTC_PLL_CONTROL,
+ pll | AR_RTC_9300_PLL_BYPASS);
udelay(1000);
/* program refdiv, nint, frac to RTC register */
@@ -770,7 +770,8 @@ static void ath9k_hw_init_pll(struct ath
} else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
u32 regval, pll2_divint, pll2_divfrac, refdiv;
- REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
+ REG_WRITE(ah, AR_RTC_PLL_CONTROL,
+ pll | AR_RTC_9300_SOC_PLL_BYPASS);
udelay(1000);
REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
@@ -843,7 +844,6 @@ static void ath9k_hw_init_pll(struct ath
udelay(1000);
}
- pll = ath9k_hw_compute_pll_control(ah, chan);
if (AR_SREV_9565(ah))
pll |= 0x40000;
REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
@@ -1192,9 +1192,12 @@ static void ath9k_hw_set_operating_mode(
switch (opmode) {
case NL80211_IFTYPE_ADHOC:
@ -505,3 +592,94 @@ Date: Sat Sep 27 15:57:09 2014 +0200
#define AR_SREV_9340_13_OR_LATER(_ah) \
(AR_SREV_9340((_ah)) && \
((_ah)->hw_version.macRev >= AR_SREV_REVISION_9340_13))
@@ -1240,12 +1244,23 @@ enum {
#define AR_CH0_DPLL3_PHASE_SHIFT_S 23
#define AR_PHY_CCA_NOM_VAL_2GHZ -118
+#define AR_RTC_9300_SOC_PLL_DIV_INT 0x0000003f
+#define AR_RTC_9300_SOC_PLL_DIV_INT_S 0
+#define AR_RTC_9300_SOC_PLL_DIV_FRAC 0x000fffc0
+#define AR_RTC_9300_SOC_PLL_DIV_FRAC_S 6
+#define AR_RTC_9300_SOC_PLL_REFDIV 0x01f00000
+#define AR_RTC_9300_SOC_PLL_REFDIV_S 20
+#define AR_RTC_9300_SOC_PLL_CLKSEL 0x06000000
+#define AR_RTC_9300_SOC_PLL_CLKSEL_S 25
+#define AR_RTC_9300_SOC_PLL_BYPASS 0x08000000
+
#define AR_RTC_9300_PLL_DIV 0x000003ff
#define AR_RTC_9300_PLL_DIV_S 0
#define AR_RTC_9300_PLL_REFDIV 0x00003C00
#define AR_RTC_9300_PLL_REFDIV_S 10
#define AR_RTC_9300_PLL_CLKSEL 0x0000C000
#define AR_RTC_9300_PLL_CLKSEL_S 14
+#define AR_RTC_9300_PLL_BYPASS 0x00010000
#define AR_RTC_9160_PLL_DIV 0x000003ff
#define AR_RTC_9160_PLL_DIV_S 0
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -1004,9 +1004,11 @@ static bool ar5008_hw_ani_control_new(st
case ATH9K_ANI_FIRSTEP_LEVEL:{
u32 level = param;
- value = level;
+ value = level * 2;
REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
AR_PHY_FIND_SIG_FIRSTEP, value);
+ REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
+ AR_PHY_FIND_SIG_FIRSTEP_LOW, value);
if (level != aniState->firstepLevel) {
ath_dbg(common, ANI,
@@ -1040,9 +1042,8 @@ static bool ar5008_hw_ani_control_new(st
REG_RMW_FIELD(ah, AR_PHY_TIMING5,
AR_PHY_TIMING5_CYCPWR_THR1, value);
- if (IS_CHAN_HT40(ah->curchan))
- REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
- AR_PHY_EXT_TIMING5_CYCPWR_THR1, value);
+ REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
+ AR_PHY_EXT_TIMING5_CYCPWR_THR1, value - 1);
if (level != aniState->spurImmunityLevel) {
ath_dbg(common, ANI,
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -517,6 +517,23 @@ static void ar9003_hw_spur_mitigate(stru
ar9003_hw_spur_mitigate_ofdm(ah, chan);
}
+static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah,
+ struct ath9k_channel *chan)
+{
+ u32 pll;
+
+ pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV);
+
+ if (chan && IS_CHAN_HALF_RATE(chan))
+ pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL);
+ else if (chan && IS_CHAN_QUARTER_RATE(chan))
+ pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL);
+
+ pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT);
+
+ return pll;
+}
+
static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
struct ath9k_channel *chan)
{
@@ -1781,7 +1798,12 @@ void ar9003_hw_attach_phy_ops(struct ath
priv_ops->rf_set_freq = ar9003_hw_set_channel;
priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
- priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
+
+ if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah))
+ priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc;
+ else
+ priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
+
priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
priv_ops->init_bb = ar9003_hw_init_bb;
priv_ops->process_ini = ar9003_hw_process_ini;

4
package/kernel/mac80211/patches/542-ath9k_debugfs_diag.patch
View file

@ -94,7 +94,7 @@
struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1763,6 +1763,20 @@ u32 ath9k_hw_get_tsf_offset(struct times
@@ -1766,6 +1766,20 @@ u32 ath9k_hw_get_tsf_offset(struct times
}
EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
@ -115,7 +115,7 @@
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
struct ath9k_hw_cal_data *caldata, bool fastcc)
{
@@ -1965,6 +1979,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
@@ -1968,6 +1982,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st
ar9003_hw_disable_phy_restart(ah);
ath9k_hw_apply_gpio_override(ah);

2
package/kernel/mac80211/patches/543-ath9k-allow-to-disable-bands-via-platform-data.patch
View file

@ -11,7 +11,7 @@
int (*external_reset)(void);
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -2359,17 +2359,25 @@ int ath9k_hw_fill_cap_info(struct ath_hw
@@ -2362,17 +2362,25 @@ int ath9k_hw_fill_cap_info(struct ath_hw
}
eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);

8
package/kernel/mac80211/patches/550-ath9k_entropy_from_adc.patch
View file

@ -18,7 +18,7 @@
void (*spectral_scan_trigger)(struct ath_hw *ah);
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -1766,6 +1766,26 @@ static void ar9003_hw_tx99_set_txpower(s
@@ -1783,6 +1783,26 @@ static void ar9003_hw_tx99_set_txpower(s
ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_14], 0));
}
@ -45,7 +45,7 @@
void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
{
struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
@@ -1796,6 +1816,7 @@ void ar9003_hw_attach_phy_ops(struct ath
@@ -1818,6 +1838,7 @@ void ar9003_hw_attach_phy_ops(struct ath
priv_ops->set_radar_params = ar9003_hw_set_radar_params;
priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
@ -110,7 +110,7 @@
static inline void ath9k_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -1231,9 +1231,30 @@ static void ar5008_hw_set_radar_conf(str
@@ -1232,9 +1232,30 @@ static void ar5008_hw_set_radar_conf(str
conf->radar_inband = 8;
}
@ -141,7 +141,7 @@
static const u32 ar5416_cca_regs[6] = {
AR_PHY_CCA,
AR_PHY_CH1_CCA,
@@ -1248,6 +1269,8 @@ int ar5008_hw_attach_phy_ops(struct ath_
@@ -1249,6 +1270,8 @@ int ar5008_hw_attach_phy_ops(struct ath_
if (ret)
return ret;

8
package/kernel/mac80211/patches/551-ath9k-ar933x-usb-hang-workaround.patch
View file

@ -20,7 +20,7 @@
/******************/
/* Chip Revisions */
/******************/
@@ -1348,6 +1361,9 @@ static bool ath9k_hw_set_reset(struct at
@@ -1351,6 +1364,9 @@ static bool ath9k_hw_set_reset(struct at
if (AR_SREV_9100(ah))
udelay(50);
@ -30,7 +30,7 @@
return true;
}
@@ -1447,6 +1463,9 @@ static bool ath9k_hw_chip_reset(struct a
@@ -1450,6 +1466,9 @@ static bool ath9k_hw_chip_reset(struct a
ar9003_hw_internal_regulator_apply(ah);
ath9k_hw_init_pll(ah, chan);
@ -40,7 +40,7 @@
return true;
}
@@ -1741,8 +1760,14 @@ static int ath9k_hw_do_fastcc(struct ath
@@ -1744,8 +1763,14 @@ static int ath9k_hw_do_fastcc(struct ath
if (AR_SREV_9271(ah))
ar9002_hw_load_ani_reg(ah, chan);
@ -55,7 +55,7 @@
return -EINVAL;
}
@@ -1990,6 +2015,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
@@ -1993,6 +2018,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
ath9k_hw_set_radar_params(ah);
}

4
package/kernel/mac80211/patches/562-ath9k_ani_ws_detect.patch
View file

@ -79,7 +79,7 @@
/**
* ar9003_hw_set_channel - set channel on single-chip device
* @ah: atheros hardware structure
@@ -954,11 +940,6 @@ static bool ar9003_hw_ani_control(struct
@@ -971,11 +957,6 @@ static bool ar9003_hw_ani_control(struct
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_channel *chan = ah->curchan;
struct ar5416AniState *aniState = &ah->ani;
@ -91,7 +91,7 @@
s32 value, value2;
switch (cmd & ah->ani_function) {
@@ -972,61 +953,6 @@ static bool ar9003_hw_ani_control(struct
@@ -989,61 +970,6 @@ static bool ar9003_hw_ani_control(struct
*/
u32 on = param ? 1 : 0;

2
package/kernel/mac80211/patches/567-ath9k_fix_init_nfcal.patch
View file

@ -10,7 +10,7 @@
set_bit(NFCAL_PENDING, &ah->caldata->cal_flags);
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1994,8 +1994,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st
@@ -1997,8 +1997,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st
if (ath9k_hw_mci_is_enabled(ah))
ar9003_mci_check_bt(ah);