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ipq40xx: cleanup USB support

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remove the 2 USB PHY drivers and add a generic PHY driver instead

Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin 2018-07-24 14:34:01 +02:00
parent 3d456a50f4
commit c913288844
3 changed files with 227 additions and 462 deletions
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235
target/linux/ipq40xx/patches-4.14/306-qcom-ipq4019-add-USB-nodes-to-ipq4019-SoC-device-tre.patch
View file

@ -51,13 +51,14 @@ Changes:
};
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -539,5 +539,76 @@
@@ -539,5 +539,79 @@
"legacy";
status = "disabled";
};
+
+ usb3_ss_phy: ssphy@9a000 {
+ compatible = "qca,uni-ssphy";
+ compatible = "qcom,usb-ss-ipq4019-phy";
+ #phy-cells = <0>;
+ reg = <0x9a000 0x800>;
+ reg-names = "phy_base";
+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
@ -66,7 +67,8 @@ Changes:
+ };
+
+ usb3_hs_phy: hsphy@a6000 {
+ compatible = "qca,baldur-usb3-hsphy";
+ compatible = "qcom,usb-hs-ipq4019-phy";
+ #phy-cells = <0>;
+ reg = <0xa6000 0x40>;
+ reg-names = "phy_base";
+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
@ -75,7 +77,7 @@ Changes:
+ };
+
+ usb3@8af8800 {
+ compatible = "qca,ipq4019-dwc3";
+ compatible = "qcom,dwc3";
+ reg = <0x8af8800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
@ -90,14 +92,15 @@ Changes:
+ compatible = "snps,dwc3";
+ reg = <0x8a00000 0xf8000>;
+ interrupts = <0 132 0>;
+ usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+ };
+ };
+
+ usb2_hs_phy: hsphy@a8000 {
+ compatible = "qca,baldur-usb2-hsphy";
+ compatible = "qcom,usb-hs-ipq4019-phy";
+ #phy-cells = <0>;
+ reg = <0xa8000 0x40>;
+ reg-names = "phy_base";
+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
@ -106,7 +109,7 @@ Changes:
+ };
+
+ usb2@60f8800 {
+ compatible = "qca,ipq4019-dwc3";
+ compatible = "qcom,dwc3";
+ reg = <0x60f8800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
@ -121,10 +124,226 @@ Changes:
+ compatible = "snps,dwc3";
+ reg = <0x6000000 0xf8000>;
+ interrupts = <0 136 0>;
+ usb-phy = <&usb2_hs_phy>;
+ phys = <&usb2_hs_phy>;
+ phy-names = "usb2-phy";
+ dr_mode = "host";
+ };
+ };
};
};
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -8,6 +8,13 @@ config PHY_QCOM_APQ8064_SATA
depends on OF
select GENERIC_PHY
+config PHY_QCOM_IPQ4019_USB
+ tristate "Qualcomm IPQ4019 USB PHY module"
+ depends on OF && ARCH_QCOM
+ select GENERIC_PHY
+ help
+ Support for the USB PHY on QCOM IPQ4019/Dakota chipsets.
+
config PHY_QCOM_IPQ806X_SATA
tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
depends on ARCH_QCOM
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
+obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2018 John Crispin <john@phrozen.org>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_platform.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+/*
+ * Magic registers copied from the SDK driver code
+ */
+#define PHY_CTRL0_ADDR 0x000
+#define PHY_CTRL1_ADDR 0x004
+#define PHY_CTRL2_ADDR 0x008
+#define PHY_CTRL3_ADDR 0x00C
+#define PHY_CTRL4_ADDR 0x010
+#define PHY_MISC_ADDR 0x024
+#define PHY_IPG_ADDR 0x030
+
+#define PHY_CTRL0_VAL 0xA4600015
+#define PHY_CTRL1_VAL 0x09500000
+#define PHY_CTRL2_VAL 0x00058180
+#define PHY_CTRL3_VAL 0x6DB6DCD6
+#define PHY_CTRL4_VAL 0x836DB6DB
+#define PHY_MISC_VAL 0x3803FB0C
+#define PHY_IPG_VAL 0x47323232
+
+struct ipq4019_usb_phy {
+ struct device *dev;
+ struct phy *phy;
+ void __iomem *base;
+ struct reset_control *por_rst;
+ struct reset_control *srif_rst;
+};
+
+static int ipq4019_ss_phy_power_off(struct phy *_phy)
+{
+ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+ reset_control_assert(phy->por_rst);
+ msleep(10);
+
+ return 0;
+}
+
+static int ipq4019_ss_phy_power_on(struct phy *_phy)
+{
+ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+ ipq4019_ss_phy_power_off(_phy);
+
+ reset_control_deassert(phy->por_rst);
+
+ return 0;
+}
+
+static struct phy_ops ipq4019_usb_ss_phy_ops = {
+ .power_on = ipq4019_ss_phy_power_on,
+ .power_off = ipq4019_ss_phy_power_off,
+};
+
+static int ipq4019_hs_phy_power_off(struct phy *_phy)
+{
+ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+ reset_control_assert(phy->por_rst);
+ msleep(10);
+
+ reset_control_assert(phy->srif_rst);
+ msleep(10);
+
+ return 0;
+}
+
+static int ipq4019_hs_phy_power_on(struct phy *_phy)
+{
+ struct ipq4019_usb_phy *phy = phy_get_drvdata(_phy);
+
+ ipq4019_hs_phy_power_off(_phy);
+
+ reset_control_deassert(phy->srif_rst);
+ msleep(10);
+
+ writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
+ writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
+ writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR);
+ writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR);
+ writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
+ writel(PHY_MISC_VAL, phy->base + PHY_MISC_ADDR);
+ writel(PHY_IPG_VAL, phy->base + PHY_IPG_ADDR);
+ msleep(10);
+
+ reset_control_deassert(phy->por_rst);
+
+ return 0;
+}
+
+static struct phy_ops ipq4019_usb_hs_phy_ops = {
+ .power_on = ipq4019_hs_phy_power_on,
+ .power_off = ipq4019_hs_phy_power_off,
+};
+
+static const struct of_device_id ipq4019_usb_phy_of_match[] = {
+ { .compatible = "qcom,usb-hs-ipq4019-phy", .data = &ipq4019_usb_hs_phy_ops},
+ { .compatible = "qcom,usb-ss-ipq4019-phy", .data = &ipq4019_usb_ss_phy_ops},
+ { },
+};
+MODULE_DEVICE_TABLE(of, ipq4019_usb_phy_of_match);
+
+static int ipq4019_usb_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct phy_provider *phy_provider;
+ struct ipq4019_usb_phy *phy;
+ const struct of_device_id *match;
+
+ match = of_match_device(ipq4019_usb_phy_of_match, &pdev->dev);
+ if (!match)
+ return -ENODEV;
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ phy->dev = &pdev->dev;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ phy->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(phy->base)) {
+ dev_err(dev, "failed to remap register memory\n");
+ return PTR_ERR(phy->base);
+ }
+
+ phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
+ if (IS_ERR(phy->por_rst)) {
+ if (PTR_ERR(phy->por_rst) != -EPROBE_DEFER)
+ dev_err(dev, "POR reset is missing\n");
+ return PTR_ERR(phy->por_rst);
+ }
+
+ phy->srif_rst = devm_reset_control_get_optional(phy->dev, "srif_rst");
+ if (IS_ERR(phy->srif_rst))
+ return PTR_ERR(phy->srif_rst);
+
+ phy->phy = devm_phy_create(dev, NULL, match->data);
+ if (IS_ERR(phy->phy)) {
+ dev_err(dev, "failed to create PHY\n");
+ return PTR_ERR(phy->phy);
+ }
+ phy_set_drvdata(phy->phy, phy);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static struct platform_driver ipq4019_usb_phy_driver = {
+ .probe = ipq4019_usb_phy_probe,
+ .driver = {
+ .of_match_table = ipq4019_usb_phy_of_match,
+ .name = "ipq4019-usb-phy",
+ }
+};
+module_platform_driver(ipq4019_usb_phy_driver);
+
+MODULE_DESCRIPTION("QCOM/IPQ4019 USB phy driver");
+MODULE_AUTHOR("John Crispin <john@phrozen.org>");
+MODULE_LICENSE("GPL v2");

429
target/linux/ipq40xx/patches-4.14/820-qcom-ipq4019-Add-IPQ4019-USB-HS-SS-PHY-drivers.patch
View file

@ -1,429 +0,0 @@
From e73682ec4455c34f3f3edc7f40d90ed297521012 Mon Sep 17 00:00:00 2001
From: Senthilkumar N L <snlakshm@codeaurora.org>
Date: Tue, 6 Jan 2015 12:52:23 +0530
Subject: [PATCH] qcom: ipq4019: Add IPQ4019 USB HS/SS PHY drivers
These drivers handles control and configuration of the HS
and SS USB PHY transceivers.
Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
Changed:
- replaced spaces with tabs
- remove emulation and host variables
---
drivers/usb/phy/Kconfig | 11 ++
drivers/usb/phy/Makefile | 2 +
drivers/usb/phy/phy-qca-baldur.c | 233 +++++++++++++++++++++++++++++++++++++++
drivers/usb/phy/phy-qca-uniphy.c | 141 +++++++++++++++++++++++
4 files changed, 387 insertions(+)
create mode 100644 drivers/usb/phy/phy-qca-baldur.c
create mode 100644 drivers/usb/phy/phy-qca-uniphy.c
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -188,6 +188,17 @@ config USB_MXS_PHY
MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
+config USB_IPQ4019_PHY
+ tristate "IPQ4019 PHY wrappers support"
+ depends on (USB || USB_GADGET) && ARCH_QCOM
+ select USB_PHY
+ help
+ Enable this to support the USB PHY transceivers on QCA961x chips.
+ It handles PHY initialization, clock management required after
+ resetting the hardware and power management.
+ This driver is required even for peripheral only or host only
+ mode configurations.
+
config USB_ULPI
bool "Generic ULPI Transceiver Driver"
depends on ARM || ARM64
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -21,6 +21,8 @@ obj-$(CONFIG_USB_GPIO_VBUS) += phy-gpio
obj-$(CONFIG_USB_ISP1301) += phy-isp1301.o
obj-$(CONFIG_USB_MSM_OTG) += phy-msm-usb.o
obj-$(CONFIG_USB_QCOM_8X16_PHY) += phy-qcom-8x16-usb.o
+obj-$(CONFIG_USB_IPQ4019_PHY) += phy-qca-baldur.o
+obj-$(CONFIG_USB_IPQ4019_PHY) += phy-qca-uniphy.o
obj-$(CONFIG_USB_MV_OTG) += phy-mv-usb.o
obj-$(CONFIG_USB_MXS_PHY) += phy-mxs-usb.o
obj-$(CONFIG_USB_ULPI) += phy-ulpi.o
--- /dev/null
+++ b/drivers/usb/phy/phy-qca-baldur.c
@@ -0,0 +1,233 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/usb/phy.h>
+#include <linux/reset.h>
+#include <linux/of_device.h>
+
+/**
+ * USB Hardware registers
+ */
+#define PHY_CTRL0_ADDR 0x000
+#define PHY_CTRL1_ADDR 0x004
+#define PHY_CTRL2_ADDR 0x008
+#define PHY_CTRL3_ADDR 0x00C
+#define PHY_CTRL4_ADDR 0x010
+#define PHY_MISC_ADDR 0x024
+#define PHY_IPG_ADDR 0x030
+
+#define PHY_CTRL0_VAL 0xA4600015
+#define PHY_CTRL1_VAL 0x09500000
+#define PHY_CTRL2_VAL 0x00058180
+#define PHY_CTRL3_VAL 0x6DB6DCD6
+#define PHY_CTRL4_VAL 0x836DB6DB
+#define PHY_MISC_VAL 0x3803FB0C
+#define PHY_IPG_VAL 0x47323232
+
+#define USB30_HS_PHY_HOST_MODE (0x01 << 21)
+#define USB20_HS_PHY_HOST_MODE (0x01 << 5)
+
+/* used to differentiate between USB3 HS and USB2 HS PHY */
+struct qca_baldur_hs_data {
+ unsigned int usb3_hs_phy;
+ unsigned int phy_config_offset;
+};
+
+struct qca_baldur_hs_phy {
+ struct device *dev;
+ struct usb_phy phy;
+
+ void __iomem *base;
+ void __iomem *qscratch_base;
+
+ struct reset_control *por_rst;
+ struct reset_control *srif_rst;
+
+ const struct qca_baldur_hs_data *data;
+};
+
+#define phy_to_dw_phy(x) container_of((x), struct qca_baldur_hs_phy, phy)
+
+static int qca_baldur_phy_read(struct usb_phy *x, u32 reg)
+{
+ struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
+
+ return readl(phy->base + reg);
+}
+
+static int qca_baldur_phy_write(struct usb_phy *x, u32 val, u32 reg)
+{
+ struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
+
+ writel(val, phy->base + reg);
+ return 0;
+}
+
+static int qca_baldur_hs_phy_init(struct usb_phy *x)
+{
+ struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
+
+ /* assert HS PHY POR reset */
+ reset_control_assert(phy->por_rst);
+ msleep(10);
+
+ /* assert HS PHY SRIF reset */
+ reset_control_assert(phy->srif_rst);
+ msleep(10);
+
+ /* deassert HS PHY SRIF reset and program HS PHY registers */
+ reset_control_deassert(phy->srif_rst);
+ msleep(10);
+
+ /* perform PHY register writes */
+ writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
+ writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
+ writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR);
+ writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR);
+ writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
+ writel(PHY_MISC_VAL, phy->base + PHY_MISC_ADDR);
+ writel(PHY_IPG_VAL, phy->base + PHY_IPG_ADDR);
+
+ msleep(10);
+
+ /* de-assert USB3 HS PHY POR reset */
+ reset_control_deassert(phy->por_rst);
+
+ return 0;
+}
+
+static int qca_baldur_hs_get_resources(struct qca_baldur_hs_phy *phy)
+{
+ struct platform_device *pdev = to_platform_device(phy->dev);
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ phy->base = devm_ioremap_resource(phy->dev, res);
+ if (IS_ERR(phy->base))
+ return PTR_ERR(phy->base);
+
+ phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
+ if (IS_ERR(phy->por_rst))
+ return PTR_ERR(phy->por_rst);
+
+ phy->srif_rst = devm_reset_control_get(phy->dev, "srif_rst");
+ if (IS_ERR(phy->srif_rst))
+ return PTR_ERR(phy->srif_rst);
+
+ return 0;
+}
+
+static void qca_baldur_hs_put_resources(struct qca_baldur_hs_phy *phy)
+{
+ reset_control_assert(phy->srif_rst);
+ reset_control_assert(phy->por_rst);
+}
+
+static int qca_baldur_hs_remove(struct platform_device *pdev)
+{
+ struct qca_baldur_hs_phy *phy = platform_get_drvdata(pdev);
+
+ usb_remove_phy(&phy->phy);
+ return 0;
+}
+
+static void qca_baldur_hs_phy_shutdown(struct usb_phy *x)
+{
+ struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
+
+ qca_baldur_hs_put_resources(phy);
+}
+
+static struct usb_phy_io_ops qca_baldur_io_ops = {
+ .read = qca_baldur_phy_read,
+ .write = qca_baldur_phy_write,
+};
+
+static const struct qca_baldur_hs_data usb3_hs_data = {
+ .usb3_hs_phy = 1,
+ .phy_config_offset = USB30_HS_PHY_HOST_MODE,
+};
+
+static const struct qca_baldur_hs_data usb2_hs_data = {
+ .usb3_hs_phy = 0,
+ .phy_config_offset = USB20_HS_PHY_HOST_MODE,
+};
+
+static const struct of_device_id qca_baldur_hs_id_table[] = {
+ { .compatible = "qca,baldur-usb3-hsphy", .data = &usb3_hs_data },
+ { .compatible = "qca,baldur-usb2-hsphy", .data = &usb2_hs_data },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, qca_baldur_hs_id_table);
+
+static int qca_baldur_hs_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match;
+ struct qca_baldur_hs_phy *phy;
+ int err;
+
+ match = of_match_device(qca_baldur_hs_id_table, &pdev->dev);
+ if (!match)
+ return -ENODEV;
+
+ phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, phy);
+ phy->dev = &pdev->dev;
+
+ phy->data = match->data;
+
+ err = qca_baldur_hs_get_resources(phy);
+ if (err < 0) {
+ dev_err(&pdev->dev, "failed to request resources: %d\n", err);
+ return err;
+ }
+
+ phy->phy.dev = phy->dev;
+ phy->phy.label = "qca-baldur-hsphy";
+ phy->phy.init = qca_baldur_hs_phy_init;
+ phy->phy.shutdown = qca_baldur_hs_phy_shutdown;
+ phy->phy.type = USB_PHY_TYPE_USB2;
+ phy->phy.io_ops = &qca_baldur_io_ops;
+
+ err = usb_add_phy_dev(&phy->phy);
+ return err;
+}
+
+static struct platform_driver qca_baldur_hs_driver = {
+ .probe = qca_baldur_hs_probe,
+ .remove = qca_baldur_hs_remove,
+ .driver = {
+ .name = "qca-baldur-hsphy",
+ .owner = THIS_MODULE,
+ .of_match_table = qca_baldur_hs_id_table,
+ },
+};
+
+module_platform_driver(qca_baldur_hs_driver);
+
+MODULE_ALIAS("platform:qca-baldur-hsphy");
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("USB3 QCA BALDUR HSPHY driver");
--- /dev/null
+++ b/drivers/usb/phy/phy-qca-uniphy.c
@@ -0,0 +1,135 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/usb/phy.h>
+#include <linux/reset.h>
+#include <linux/of_device.h>
+
+struct qca_uni_ss_phy {
+ struct usb_phy phy;
+ struct device *dev;
+
+ void __iomem *base;
+
+ struct reset_control *por_rst;
+};
+
+#define phy_to_dw_phy(x) container_of((x), struct qca_uni_ss_phy, phy)
+
+static void qca_uni_ss_phy_shutdown(struct usb_phy *x)
+{
+ struct qca_uni_ss_phy *phy = phy_to_dw_phy(x);
+
+ /* assert SS PHY POR reset */
+ reset_control_assert(phy->por_rst);
+}
+
+static int qca_uni_ss_phy_init(struct usb_phy *x)
+{
+ struct qca_uni_ss_phy *phy = phy_to_dw_phy(x);
+
+ /* assert SS PHY POR reset */
+ reset_control_assert(phy->por_rst);
+
+ msleep(20);
+
+ /* deassert SS PHY POR reset */
+ reset_control_deassert(phy->por_rst);
+
+ return 0;
+}
+
+static int qca_uni_ss_get_resources(struct platform_device *pdev,
+ struct qca_uni_ss_phy *phy)
+{
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ phy->base = devm_ioremap_resource(phy->dev, res);
+ if (IS_ERR(phy->base))
+ return PTR_ERR(phy->base);
+
+ phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
+ if (IS_ERR(phy->por_rst))
+ return PTR_ERR(phy->por_rst);
+
+ return 0;
+}
+
+static int qca_uni_ss_remove(struct platform_device *pdev)
+{
+ struct qca_uni_ss_phy *phy = platform_get_drvdata(pdev);
+
+ usb_remove_phy(&phy->phy);
+ return 0;
+}
+
+static const struct of_device_id qca_uni_ss_id_table[] = {
+ { .compatible = "qca,uni-ssphy" },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, qca_uni_ss_id_table);
+
+static int qca_uni_ss_probe(struct platform_device *pdev)
+{
+ struct qca_uni_ss_phy *phy;
+ int ret;
+
+ phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, phy);
+ phy->dev = &pdev->dev;
+
+ ret = qca_uni_ss_get_resources(pdev, phy);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to request resources: %d\n", ret);
+ return ret;
+ }
+
+ phy->phy.dev = phy->dev;
+ phy->phy.label = "qca-uni-ssphy";
+ phy->phy.init = qca_uni_ss_phy_init;
+ phy->phy.shutdown = qca_uni_ss_phy_shutdown;
+ phy->phy.type = USB_PHY_TYPE_USB3;
+
+ ret = usb_add_phy_dev(&phy->phy);
+ return ret;
+}
+
+static struct platform_driver qca_uni_ss_driver = {
+ .probe = qca_uni_ss_probe,
+ .remove = qca_uni_ss_remove,
+ .driver = {
+ .name = "qca-uni-ssphy",
+ .owner = THIS_MODULE,
+ .of_match_table = qca_uni_ss_id_table,
+ },
+};
+
+module_platform_driver(qca_uni_ss_driver);
+
+MODULE_ALIAS("platform:qca-uni-ssphy");
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("USB3 QCA UNI SSPHY driver");

25
target/linux/ipq40xx/patches-4.14/830-usb-dwc3-register-qca-ipq4019-dwc3-in-dwc3-of-simple.patch
View file

@ -1,25 +0,0 @@
From 08c18ab774368feb610d1eb952957bb1bb35129f Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sat, 19 Nov 2016 00:52:35 +0100
Subject: [PATCH 37/38] usb: dwc3: register qca,ipq4019-dwc3 in dwc3-of-simple
For host mode, the dwc3 found in the IPQ4019 can be driven
by the dwc3-of-simple module. It will get more tricky for
OTG since they'll need to enable VBUS and reconfigure the
registers.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
drivers/usb/dwc3/dwc3-of-simple.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -176,6 +176,7 @@ static const struct dev_pm_ops dwc3_of_s
static const struct of_device_id of_dwc3_simple_match[] = {
{ .compatible = "qcom,dwc3" },
+ { .compatible = "qca,ipq4019-dwc3" },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "xlnx,zynqmp-dwc3" },
{ .compatible = "cavium,octeon-7130-usb-uctl" },