add selection of console driver for ifxmips
SVN-Revision: 9936
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parent
6bdd0ef590
commit
c61b903d05
3 changed files with 29 additions and 20 deletions
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@ -60,12 +60,13 @@ CONFIG_IFXMIPS=y
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CONFIG_IFXMIPS_ASC_UART=y
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CONFIG_IFXMIPS_EEPROM=y
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CONFIG_IFXMIPS_GPIO=y
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CONFIG_IFXMIPS_GPIO_RST_BTN=y
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CONFIG_IFXMIPS_LED=y
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CONFIG_IFXMIPS_MEI=y
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CONFIG_IFXMIPS_MII0=y
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# CONFIG_IFXMIPS_MII1 is not set
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CONFIG_IFXMIPS_SSC=y
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# CONFIG_IFXMIPS_USE_CONSOLE0 is not set
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CONFIG_IFXMIPS_USE_CONSOLE1=y
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CONFIG_IFXMIPS_WDT=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IRQ_CPU=y
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@ -29,6 +29,13 @@
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#include <asm/bootinfo.h>
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#include <asm/ifxmips/ifxmips.h>
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#ifdef CONFIG_IFXMIPS_USE_CONSOLE0
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#define ASC_OFFSET 0
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#elif CONFIG_IFXMIPS_USE_CONSOLE1
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#define ASC_OFFSET IFXMIPS_ASC1_BASE_OFFSET
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#else
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#error a tty for the console must be selected
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#endif
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static char buf[1024];
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void
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@ -39,11 +46,11 @@ prom_free_prom_memory (void)
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void
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prom_putchar (char c)
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{
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while ((readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
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while ((readl(IFXMIPS_ASC0_FSTAT + ASC_OFFSET) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
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if (c == '\n')
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writel('\r', IFXMIPS_ASC1_TBUF);
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writel(c, IFXMIPS_ASC1_TBUF);
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writel('\r', IFXMIPS_ASC0_TBUF + ASC_OFFSET);
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writel(c, IFXMIPS_ASC0_TBUF + ASC_OFFSET);
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}
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void
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@ -34,17 +34,18 @@
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#define IFXMIPS_FLASH_MAX 0x2000000
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/*------------ ASC1 */
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/*------------ ASC0 */
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#define IFXMIPS_ASC1_BASE_ADDR (KSEG1 + 0x1E100C00)
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#define IFXMIPS_ASC0_BASE_ADDR (KSEG1 + 0x1E400C00)
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#define IFXMIPS_ASC1_BASE_OFFSET ((0x1E100C00 - 0x1E400C00) / sizeof(u32))
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/* FIFO status register */
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#define IFXMIPS_ASC1_FSTAT ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0048))
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#define IFXMIPS_ASC0_FSTAT ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0048))
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#define ASCFSTAT_TXFFLMASK 0x3F00
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#define ASCFSTAT_TXFFLOFF 8
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/* ASC1 transmit buffer */
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#define IFXMIPS_ASC1_TBUF ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0020))
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#define IFXMIPS_ASC0_TBUF ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0020))
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/* channel operating modes */
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#define ASCOPT_CSIZE 0x3
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@ -56,43 +57,43 @@
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#define ASCOPT_CREAD 0x20
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/* hardware modified control register */
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#define IFXMIPS_ASC1_WHBSTATE ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0018))
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#define IFXMIPS_ASC0_WHBSTATE ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0018))
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/* receive buffer register */
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#define IFXMIPS_ASC1_RBUF ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0024))
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#define IFXMIPS_ASC0_RBUF ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0024))
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/* status register */
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#define IFXMIPS_ASC1_STATE ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0014))
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#define IFXMIPS_ASC0_STATE ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0014))
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/* interrupt control */
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#define IFXMIPS_ASC1_IRNCR ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x00F8))
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#define IFXMIPS_ASC0_IRNCR ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x00F8))
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#define ASC_IRNCR_TIR 0x4
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#define ASC_IRNCR_RIR 0x2
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#define ASC_IRNCR_EIR 0x4
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/* clock control */
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#define IFXMIPS_ASC1_CLC ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0000))
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#define IFXMIPS_ASC0_CLC ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0000))
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#define IFXMIPS_ASC1_CLC_DISS 0x2
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#define IFXMIPS_ASC0_CLC_DISS 0x2
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/* port input select register */
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#define IFXMIPS_ASC1_PISEL ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0004))
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#define IFXMIPS_ASC0_PISEL ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0004))
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/* tx fifo */
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#define IFXMIPS_ASC1_TXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0044))
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#define IFXMIPS_ASC0_TXFCON ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0044))
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/* rx fifo */
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#define IFXMIPS_ASC1_RXFCON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0040))
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#define IFXMIPS_ASC0_RXFCON ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0040))
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/* control */
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#define IFXMIPS_ASC1_CON ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0010))
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#define IFXMIPS_ASC0_CON ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0010))
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/* timer reload */
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#define IFXMIPS_ASC1_BG ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0050))
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#define IFXMIPS_ASC0_BG ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0050))
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/* int enable */
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#define IFXMIPS_ASC1_IRNREN ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x00F4))
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#define IFXMIPS_ASC0_IRNREN ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x00F4))
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#define ASC_IRNREN_RX_BUF 0x8
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#define ASC_IRNREN_TX_BUF 0x4
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