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Add rt2x00-mac80211 snapshot (#1916)

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SVN-Revision: 8184
This commit is contained in:
Florian Fainelli 2007-07-26 20:00:24 +00:00
parent 1a12e151ee
commit c43c4da559
29 changed files with 19615 additions and 0 deletions
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#
# Copyright (C) 2007 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
# $Id: $
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=kmod-rt2x00
PKG_VERSION:=git-200706018
include $(INCLUDE_DIR)/package.mk
define Package/rt2x00/Default
SUBMENU:=Wireless Drivers
DEPENDS:=@LINUX_2_6 +kmod-mac80211 @LINUX_2_6_X86||@LINUX_2_6_RDC
TITLE:=Ralink GPL Drivers
DESCRIPTION:=Ralink GPL Drivers for rt2x00 cards
VERSION:=$(LINUX_VERSION)+$(PKG_VERSION)-$(BOARD)-$(LINUX_RELEASE)
endef
define KernelPackage/rt2x00-lib
$(call Package/rt2x00/Default)
TITLE+= (LIB)
DESCRIPTION+= (LIB)
FILES:=$(PKG_BUILD_DIR)/rt2x00lib.$(LINUX_KMOD_SUFFIX)
AUTOLOAD:=$(call AutoLoad,25,rt2x00lib)
endef
define KernelPackage/rt2x00-pci
$(call Package/rt2x00/Default)
TITLE+= (PCI)
DESCRIPTION+= (PCI)
FILES:=$(PKG_BUILD_DIR)/rt2x00pci.$(LINUX_KMOD_SUFFIX)
AUTOLOAD:=$(call AutoLoad,26,rt2x00pci)
endef
define KernelPackage/rt2x00-usb
$(call Package/rt2x00/Default)
TITLE+= (USB)
DESCRIPTION+= (USB)
FILES:=$(PKG_BUILD_DIR)/rt2x00usb.$(LINUX_KMOD_SUFFIX)
AUTOLOAD:=$(call AutoLoad,26,rt2x00usb)
endef
define Build/Prepare
$(call Build/Prepare/Default)
$(CP) -r src/* $(PKG_BUILD_DIR)/
endef
define Build/Compile
$(MAKE) -C "$(LINUX_DIR)" \
CROSS_COMPILE="$(TARGET_CROSS)" \
ARCH="$(LINUX_KARCH)" \
SUBDIRS="$(PKG_BUILD_DIR)" \
KERNELVERSION="$(KERNEL)" \
KERNEL_SOURCE="$(LINUX_DIR)" \
EXTRA_CFLAGS="$(BUILDFLAGS) -include $(PKG_BUILD_DIR)/rt2x00_compat.h" \
KDIR="$(LINUX_DIR)"
endef
$(eval $(call KernelPackage,rt2x00-lib))
$(eval $(call KernelPackage,rt2x00-pci))
$(eval $(call KernelPackage,rt2x00-usb))

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rt2x00lib-objs := rt2x00dev.o rt2x00mac.o
EXTRA_CFLAGS += -DCONFIG_RT2X00_LIB_FIRMWARE
obj-m += rt2x00lib.o rt2x00pci.o rt2x00usb.o
obj-$(CONFIG_RT2400PCI) += rt2400pci.o
obj-$(CONFIG_RT2500PCI) += rt2500pci.o
obj-$(CONFIG_RT61PCI) += rt61pci.o
obj-$(CONFIG_RT2500USB) += rt2500usb.o
obj-$(CONFIG_RT73USB) += rt73usb.o

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package/rt2x00/src/rt2400pci.c Normal file
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/*
Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2400pci
Abstract: Data structures and registers for the rt2400pci module.
Supported chipsets: RT2460.
*/
#ifndef RT2400PCI_H
#define RT2400PCI_H
/*
* RF chip defines.
*/
#define RF2420 0x0000
#define RF2421 0x0001
/*
* Max RSSI value, required for RSSI <-> dBm conversion.
*/
#define MAX_RX_SSI 100
#define MAX_RX_NOISE -110
/*
* Register layout information.
*/
#define CSR_REG_BASE 0x0000
#define CSR_REG_SIZE 0x014c
#define EEPROM_BASE 0x0000
#define EEPROM_SIZE 0x0100
#define BBP_SIZE 0x0020
/*
* Control/Status Registers(CSR).
* Some values are set in TU, whereas 1 TU == 1024 us.
*/
/*
* CSR0: ASIC revision number.
*/
#define CSR0 0x0000
/*
* CSR1: System control register.
* SOFT_RESET: Software reset, 1: reset, 0: normal.
* BBP_RESET: Hardware reset, 1: reset, 0, release.
* HOST_READY: Host ready after initialization.
*/
#define CSR1 0x0004
#define CSR1_SOFT_RESET FIELD32(0x00000001)
#define CSR1_BBP_RESET FIELD32(0x00000002)
#define CSR1_HOST_READY FIELD32(0x00000004)
/*
* CSR2: System admin status register (invalid).
*/
#define CSR2 0x0008
/*
* CSR3: STA MAC address register 0.
*/
#define CSR3 0x000c
#define CSR3_BYTE0 FIELD32(0x000000ff)
#define CSR3_BYTE1 FIELD32(0x0000ff00)
#define CSR3_BYTE2 FIELD32(0x00ff0000)
#define CSR3_BYTE3 FIELD32(0xff000000)
/*
* CSR4: STA MAC address register 1.
*/
#define CSR4 0x0010
#define CSR4_BYTE4 FIELD32(0x000000ff)
#define CSR4_BYTE5 FIELD32(0x0000ff00)
/*
* CSR5: BSSID register 0.
*/
#define CSR5 0x0014
#define CSR5_BYTE0 FIELD32(0x000000ff)
#define CSR5_BYTE1 FIELD32(0x0000ff00)
#define CSR5_BYTE2 FIELD32(0x00ff0000)
#define CSR5_BYTE3 FIELD32(0xff000000)
/*
* CSR6: BSSID register 1.
*/
#define CSR6 0x0018
#define CSR6_BYTE4 FIELD32(0x000000ff)
#define CSR6_BYTE5 FIELD32(0x0000ff00)
/*
* CSR7: Interrupt source register.
* Write 1 to clear interrupt.
* TBCN_EXPIRE: Beacon timer expired interrupt.
* TWAKE_EXPIRE: Wakeup timer expired interrupt.
* TATIMW_EXPIRE: Timer of atim window expired interrupt.
* TXDONE_TXRING: Tx ring transmit done interrupt.
* TXDONE_ATIMRING: Atim ring transmit done interrupt.
* TXDONE_PRIORING: Priority ring transmit done interrupt.
* RXDONE: Receive done interrupt.
*/
#define CSR7 0x001c
#define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
#define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
#define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
#define CSR7_TXDONE_TXRING FIELD32(0x00000008)
#define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
#define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
#define CSR7_RXDONE FIELD32(0x00000040)
/*
* CSR8: Interrupt mask register.
* Write 1 to mask interrupt.
* TBCN_EXPIRE: Beacon timer expired interrupt.
* TWAKE_EXPIRE: Wakeup timer expired interrupt.
* TATIMW_EXPIRE: Timer of atim window expired interrupt.
* TXDONE_TXRING: Tx ring transmit done interrupt.
* TXDONE_ATIMRING: Atim ring transmit done interrupt.
* TXDONE_PRIORING: Priority ring transmit done interrupt.
* RXDONE: Receive done interrupt.
*/
#define CSR8 0x0020
#define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
#define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
#define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
#define CSR8_TXDONE_TXRING FIELD32(0x00000008)
#define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
#define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
#define CSR8_RXDONE FIELD32(0x00000040)
/*
* CSR9: Maximum frame length register.
* MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
*/
#define CSR9 0x0024
#define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
/*
* CSR11: Back-off control register.
* CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
* CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
* SLOT_TIME: Slot time, default is 20us for 802.11b.
* LONG_RETRY: Long retry count.
* SHORT_RETRY: Short retry count.
*/
#define CSR11 0x002c
#define CSR11_CWMIN FIELD32(0x0000000f)
#define CSR11_CWMAX FIELD32(0x000000f0)
#define CSR11_SLOT_TIME FIELD32(0x00001f00)
#define CSR11_LONG_RETRY FIELD32(0x00ff0000)
#define CSR11_SHORT_RETRY FIELD32(0xff000000)
/*
* CSR12: Synchronization configuration register 0.
* All units in 1/16 TU.
* BEACON_INTERVAL: Beacon interval, default is 100 TU.
* CFPMAX_DURATION: Cfp maximum duration, default is 100 TU.
*/
#define CSR12 0x0030
#define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
#define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
/*
* CSR13: Synchronization configuration register 1.
* All units in 1/16 TU.
* ATIMW_DURATION: Atim window duration.
* CFP_PERIOD: Cfp period, default is 0 TU.
*/
#define CSR13 0x0034
#define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
#define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
/*
* CSR14: Synchronization control register.
* TSF_COUNT: Enable tsf auto counting.
* TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
* TBCN: Enable tbcn with reload value.
* TCFP: Enable tcfp & cfp / cp switching.
* TATIMW: Enable tatimw & atim window switching.
* BEACON_GEN: Enable beacon generator.
* CFP_COUNT_PRELOAD: Cfp count preload value.
* TBCM_PRELOAD: Tbcn preload value in units of 64us.
*/
#define CSR14 0x0038
#define CSR14_TSF_COUNT FIELD32(0x00000001)
#define CSR14_TSF_SYNC FIELD32(0x00000006)
#define CSR14_TBCN FIELD32(0x00000008)
#define CSR14_TCFP FIELD32(0x00000010)
#define CSR14_TATIMW FIELD32(0x00000020)
#define CSR14_BEACON_GEN FIELD32(0x00000040)
#define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
#define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
/*
* CSR15: Synchronization status register.
* CFP: ASIC is in contention-free period.
* ATIMW: ASIC is in ATIM window.
* BEACON_SENT: Beacon is send.
*/
#define CSR15 0x003c
#define CSR15_CFP FIELD32(0x00000001)
#define CSR15_ATIMW FIELD32(0x00000002)
#define CSR15_BEACON_SENT FIELD32(0x00000004)
/*
* CSR16: TSF timer register 0.
*/
#define CSR16 0x0040
#define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
/*
* CSR17: TSF timer register 1.
*/
#define CSR17 0x0044
#define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
/*
* CSR18: IFS timer register 0.
* SIFS: Sifs, default is 10 us.
* PIFS: Pifs, default is 30 us.
*/
#define CSR18 0x0048
#define CSR18_SIFS FIELD32(0x0000ffff)
#define CSR18_PIFS FIELD32(0xffff0000)
/*
* CSR19: IFS timer register 1.
* DIFS: Difs, default is 50 us.
* EIFS: Eifs, default is 364 us.
*/
#define CSR19 0x004c
#define CSR19_DIFS FIELD32(0x0000ffff)
#define CSR19_EIFS FIELD32(0xffff0000)
/*
* CSR20: Wakeup timer register.
* DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
* TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
* AUTOWAKE: Enable auto wakeup / sleep mechanism.
*/
#define CSR20 0x0050
#define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
#define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
#define CSR20_AUTOWAKE FIELD32(0x01000000)
/*
* CSR21: EEPROM control register.
* RELOAD: Write 1 to reload eeprom content.
* TYPE_93C46: 1: 93c46, 0:93c66.
*/
#define CSR21 0x0054
#define CSR21_RELOAD FIELD32(0x00000001)
#define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
#define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
#define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
#define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
#define CSR21_TYPE_93C46 FIELD32(0x00000020)
/*
* CSR22: CFP control register.
* CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
* RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
*/
#define CSR22 0x0058
#define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
#define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
/*
* Transmit related CSRs.
* Some values are set in TU, whereas 1 TU == 1024 us.
*/
/*
* TXCSR0: TX Control Register.
* KICK_TX: Kick tx ring.
* KICK_ATIM: Kick atim ring.
* KICK_PRIO: Kick priority ring.
* ABORT: Abort all transmit related ring operation.
*/
#define TXCSR0 0x0060
#define TXCSR0_KICK_TX FIELD32(0x00000001)
#define TXCSR0_KICK_ATIM FIELD32(0x00000002)
#define TXCSR0_KICK_PRIO FIELD32(0x00000004)
#define TXCSR0_ABORT FIELD32(0x00000008)
/*
* TXCSR1: TX Configuration Register.
* ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
* ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
* TSF_OFFSET: Insert tsf offset.
* AUTORESPONDER: Enable auto responder which include ack & cts.
*/
#define TXCSR1 0x0064
#define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
#define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
#define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
#define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
/*
* TXCSR2: Tx descriptor configuration register.
* TXD_SIZE: Tx descriptor size, default is 48.
* NUM_TXD: Number of tx entries in ring.
* NUM_ATIM: Number of atim entries in ring.
* NUM_PRIO: Number of priority entries in ring.
*/
#define TXCSR2 0x0068
#define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
#define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
#define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
#define TXCSR2_NUM_PRIO FIELD32(0xff000000)
/*
* TXCSR3: TX Ring Base address register.
*/
#define TXCSR3 0x006c
#define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
/*
* TXCSR4: TX Atim Ring Base address register.
*/
#define TXCSR4 0x0070
#define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
/*
* TXCSR5: TX Prio Ring Base address register.
*/
#define TXCSR5 0x0074
#define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
/*
* TXCSR6: Beacon Base address register.
*/
#define TXCSR6 0x0078
#define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
/*
* TXCSR7: Auto responder control register.
* AR_POWERMANAGEMENT: Auto responder power management bit.
*/
#define TXCSR7 0x007c
#define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
/*
* Receive related CSRs.
* Some values are set in TU, whereas 1 TU == 1024 us.
*/
/*
* RXCSR0: RX Control Register.
* DISABLE_RX: Disable rx engine.
* DROP_CRC: Drop crc error.
* DROP_PHYSICAL: Drop physical error.
* DROP_CONTROL: Drop control frame.
* DROP_NOT_TO_ME: Drop not to me unicast frame.
* DROP_TODS: Drop frame tods bit is true.
* DROP_VERSION_ERROR: Drop version error frame.
* PASS_CRC: Pass all packets with crc attached.
*/
#define RXCSR0 0x0080
#define RXCSR0_DISABLE_RX FIELD32(0x00000001)
#define RXCSR0_DROP_CRC FIELD32(0x00000002)
#define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
#define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
#define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
#define RXCSR0_DROP_TODS FIELD32(0x00000020)
#define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
#define RXCSR0_PASS_CRC FIELD32(0x00000080)
/*
* RXCSR1: RX descriptor configuration register.
* RXD_SIZE: Rx descriptor size, default is 32b.
* NUM_RXD: Number of rx entries in ring.
*/
#define RXCSR1 0x0084
#define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
#define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
/*
* RXCSR2: RX Ring base address register.
*/
#define RXCSR2 0x0088
#define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
/*
* RXCSR3: BBP ID register for Rx operation.
* BBP_ID#: BBP register # id.
* BBP_ID#_VALID: BBP register # id is valid or not.
*/
#define RXCSR3 0x0090
#define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
#define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
#define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
#define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
#define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
#define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
#define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
#define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
/*
* RXCSR4: BBP ID register for Rx operation.
* BBP_ID#: BBP register # id.
* BBP_ID#_VALID: BBP register # id is valid or not.
*/
#define RXCSR4 0x0094
#define RXCSR4_BBP_ID4 FIELD32(0x0000007f)
#define RXCSR4_BBP_ID4_VALID FIELD32(0x00000080)
#define RXCSR4_BBP_ID5 FIELD32(0x00007f00)
#define RXCSR4_BBP_ID5_VALID FIELD32(0x00008000)
/*
* ARCSR0: Auto Responder PLCP config register 0.
* ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
* ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
*/
#define ARCSR0 0x0098
#define ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff)
#define ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00)
#define ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000)
#define ARCSR0_AR_BBP_ID1 FIELD32(0xff000000)
/*
* ARCSR1: Auto Responder PLCP config register 1.
* ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
* ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
*/
#define ARCSR1 0x009c
#define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
#define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
#define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
#define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
/*
* Miscellaneous Registers.
* Some values are set in TU, whereas 1 TU == 1024 us.
*/
/*
* PCICSR: PCI control register.
* BIG_ENDIAN: 1: big endian, 0: little endian.
* RX_TRESHOLD: Rx threshold in dw to start pci access
* 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
* TX_TRESHOLD: Tx threshold in dw to start pci access
* 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
* BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
* ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
*/
#define PCICSR 0x008c
#define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
#define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
#define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
#define PCICSR_BURST_LENTH FIELD32(0x00000060)
#define PCICSR_ENABLE_CLK FIELD32(0x00000080)
/*
* CNT0: FCS error count.
* FCS_ERROR: FCS error count, cleared when read.
*/
#define CNT0 0x00a0
#define CNT0_FCS_ERROR FIELD32(0x0000ffff)
/*
* Statistic Register.
* CNT1: PLCP error count.
* CNT2: Long error count.
* CNT3: CCA false alarm count.
* CNT4: Rx FIFO overflow count.
* CNT5: Tx FIFO underrun count.
*/
#define TIMECSR2 0x00a8
#define CNT1 0x00ac
#define CNT2 0x00b0
#define TIMECSR3 0x00b4
#define CNT3 0x00b8
#define CNT4 0x00bc
#define CNT5 0x00c0
/*
* Baseband Control Register.
*/
/*
* PWRCSR0: Power mode configuration register.
*/
#define PWRCSR0 0x00c4
/*
* Power state transition time registers.
*/
#define PSCSR0 0x00c8
#define PSCSR1 0x00cc
#define PSCSR2 0x00d0
#define PSCSR3 0x00d4
/*
* PWRCSR1: Manual power control / status register.
* Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
* SET_STATE: Set state. Write 1 to trigger, self cleared.
* BBP_DESIRE_STATE: BBP desired state.
* RF_DESIRE_STATE: RF desired state.
* BBP_CURR_STATE: BBP current state.
* RF_CURR_STATE: RF current state.
* PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
*/
#define PWRCSR1 0x00d8
#define PWRCSR1_SET_STATE FIELD32(0x00000001)
#define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
#define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
#define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
#define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
#define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
/*
* TIMECSR: Timer control register.
* US_COUNT: 1 us timer count in units of clock cycles.
* US_64_COUNT: 64 us timer count in units of 1 us timer.
* BEACON_EXPECT: Beacon expect window.
*/
#define TIMECSR 0x00dc
#define TIMECSR_US_COUNT FIELD32(0x000000ff)
#define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
#define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
/*
* MACCSR0: MAC configuration register 0.
*/
#define MACCSR0 0x00e0
/*
* MACCSR1: MAC configuration register 1.
* KICK_RX: Kick one-shot rx in one-shot rx mode.
* ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
* BBPRX_RESET_MODE: Ralink bbp rx reset mode.
* AUTO_TXBBP: Auto tx logic access bbp control register.
* AUTO_RXBBP: Auto rx logic access bbp control register.
* LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
* INTERSIL_IF: Intersil if calibration pin.
*/
#define MACCSR1 0x00e4
#define MACCSR1_KICK_RX FIELD32(0x00000001)
#define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
#define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
#define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
#define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
#define MACCSR1_LOOPBACK FIELD32(0x00000060)
#define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
/*
* RALINKCSR: Ralink Rx auto-reset BBCR.
* AR_BBP_DATA#: Auto reset BBP register # data.
* AR_BBP_ID#: Auto reset BBP register # id.
*/
#define RALINKCSR 0x00e8
#define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
#define RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00)
#define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
#define RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000)
/*
* BCNCSR: Beacon interval control register.
* CHANGE: Write one to change beacon interval.
* DELTATIME: The delta time value.
* NUM_BEACON: Number of beacon according to mode.
* MODE: Please refer to asic specs.
* PLUS: Plus or minus delta time value.
*/
#define BCNCSR 0x00ec
#define BCNCSR_CHANGE FIELD32(0x00000001)
#define BCNCSR_DELTATIME FIELD32(0x0000001e)
#define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
#define BCNCSR_MODE FIELD32(0x00006000)
#define BCNCSR_PLUS FIELD32(0x00008000)
/*
* BBP / RF / IF Control Register.
*/
/*
* BBPCSR: BBP serial control register.
* VALUE: Register value to program into BBP.
* REGNUM: Selected BBP register.
* BUSY: 1: asic is busy execute BBP programming.
* WRITE_CONTROL: 1: write BBP, 0: read BBP.
*/
#define BBPCSR 0x00f0
#define BBPCSR_VALUE FIELD32(0x000000ff)
#define BBPCSR_REGNUM FIELD32(0x00007f00)
#define BBPCSR_BUSY FIELD32(0x00008000)
#define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
/*
* RFCSR: RF serial control register.
* VALUE: Register value + id to program into rf/if.
* NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
* IF_SELECT: Chip to program: 0: rf, 1: if.
* PLL_LD: Rf pll_ld status.
* BUSY: 1: asic is busy execute rf programming.
*/
#define RFCSR 0x00f4
#define RFCSR_VALUE FIELD32(0x00ffffff)
#define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
#define RFCSR_IF_SELECT FIELD32(0x20000000)
#define RFCSR_PLL_LD FIELD32(0x40000000)
#define RFCSR_BUSY FIELD32(0x80000000)
/*
* LEDCSR: LED control register.
* ON_PERIOD: On period, default 70ms.
* OFF_PERIOD: Off period, default 30ms.
* LINK: 0: linkoff, 1: linkup.
* ACTIVITY: 0: idle, 1: active.
*/
#define LEDCSR 0x00f8
#define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
#define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
#define LEDCSR_LINK FIELD32(0x00010000)
#define LEDCSR_ACTIVITY FIELD32(0x00020000)
/*
* ASIC pointer information.
* RXPTR: Current RX ring address.
* TXPTR: Current Tx ring address.
* PRIPTR: Current Priority ring address.
* ATIMPTR: Current ATIM ring address.
*/
#define RXPTR 0x0100
#define TXPTR 0x0104
#define PRIPTR 0x0108
#define ATIMPTR 0x010c
/*
* GPIO and others.
*/
/*
* GPIOCSR: GPIO control register.
*/
#define GPIOCSR 0x0120
#define GPIOCSR_BIT0 FIELD32(0x00000001)
#define GPIOCSR_BIT1 FIELD32(0x00000002)
#define GPIOCSR_BIT2 FIELD32(0x00000004)
#define GPIOCSR_BIT3 FIELD32(0x00000008)
#define GPIOCSR_BIT4 FIELD32(0x00000010)
#define GPIOCSR_BIT5 FIELD32(0x00000020)
#define GPIOCSR_BIT6 FIELD32(0x00000040)
#define GPIOCSR_BIT7 FIELD32(0x00000080)
/*
* BBPPCSR: BBP Pin control register.
*/
#define BBPPCSR 0x0124
/*
* BCNCSR1: Tx BEACON offset time control register.
* PRELOAD: Beacon timer offset in units of usec.
*/
#define BCNCSR1 0x0130
#define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
/*
* MACCSR2: TX_PE to RX_PE turn-around time control register
* DELAY: RX_PE low width, in units of pci clock cycle.
*/
#define MACCSR2 0x0134
#define MACCSR2_DELAY FIELD32(0x000000ff)
/*
* ARCSR2: 1 Mbps ACK/CTS PLCP.
*/
#define ARCSR2 0x013c
#define ARCSR2_SIGNAL FIELD32(0x000000ff)
#define ARCSR2_SERVICE FIELD32(0x0000ff00)
#define ARCSR2_LENGTH_LOW FIELD32(0x00ff0000)
#define ARCSR2_LENGTH FIELD32(0xffff0000)
/*
* ARCSR3: 2 Mbps ACK/CTS PLCP.
*/
#define ARCSR3 0x0140
#define ARCSR3_SIGNAL FIELD32(0x000000ff)
#define ARCSR3_SERVICE FIELD32(0x0000ff00)
#define ARCSR3_LENGTH FIELD32(0xffff0000)
/*
* ARCSR4: 5.5 Mbps ACK/CTS PLCP.
*/
#define ARCSR4 0x0144
#define ARCSR4_SIGNAL FIELD32(0x000000ff)
#define ARCSR4_SERVICE FIELD32(0x0000ff00)
#define ARCSR4_LENGTH FIELD32(0xffff0000)
/*
* ARCSR5: 11 Mbps ACK/CTS PLCP.
*/
#define ARCSR5 0x0148
#define ARCSR5_SIGNAL FIELD32(0x000000ff)
#define ARCSR5_SERVICE FIELD32(0x0000ff00)
#define ARCSR5_LENGTH FIELD32(0xffff0000)
/*
* RF registers
*/
#define RF1_TUNER FIELD32(0x00020000)
#define RF3_TUNER FIELD32(0x00000100)
#define RF3_TXPOWER FIELD32(0x00003e00)
/*
* EEPROM content.
* The wordsize of the EEPROM is 16 bits.
*/
/*
* HW MAC address.
*/
#define EEPROM_MAC_ADDR_0 0x0002
#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
#define EEPROM_MAC_ADDR1 0x0003
#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
#define EEPROM_MAC_ADDR_2 0x0004
#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
/*
* EEPROM antenna.
* ANTENNA_NUM: Number of antenna's.
* TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
* RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
* RF_TYPE: Rf_type of this adapter.
* LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
* RX_AGCVGC: 0: disable, 1:enable BBP R13 tuning.
* HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
*/
#define EEPROM_ANTENNA 0x0b
#define EEPROM_ANTENNA_NUM FIELD16(0x0003)
#define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
#define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0040)
#define EEPROM_ANTENNA_LED_MODE FIELD16(0x0180)
#define EEPROM_ANTENNA_RX_AGCVGC_TUNING FIELD16(0x0200)
#define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
/*
* EEPROM BBP.
*/
#define EEPROM_BBP_START 0x0c
#define EEPROM_BBP_SIZE 7
#define EEPROM_BBP_VALUE FIELD16(0x00ff)
#define EEPROM_BBP_REG_ID FIELD16(0xff00)
/*
* EEPROM TXPOWER
*/
#define EEPROM_TXPOWER_START 0x13
#define EEPROM_TXPOWER_SIZE 7
#define EEPROM_TXPOWER_1 FIELD16(0x00ff)
#define EEPROM_TXPOWER_2 FIELD16(0xff00)
/*
* BBP content.
* The wordsize of the BBP is 8 bits.
*/
/*
* BBP_R1: TX antenna control
*/
#define BBP_R1_TX_ANTENNA FIELD8(0x03)
/*
* BBP_R4: RX antenna control
*/
#define BBP_R4_RX_ANTENNA FIELD8(0x06)
/*
* DMA descriptor defines.
*/
#define TXD_DESC_SIZE ( 8 * sizeof(struct data_desc) )
#define RXD_DESC_SIZE ( 8 * sizeof(struct data_desc) )
/*
* TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
*/
/*
* Word0
*/
#define TXD_W0_OWNER_NIC FIELD32(0x00000001)
#define TXD_W0_VALID FIELD32(0x00000002)
#define TXD_W0_RESULT FIELD32(0x0000001c)
#define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
#define TXD_W0_MORE_FRAG FIELD32(0x00000100)
#define TXD_W0_ACK FIELD32(0x00000200)
#define TXD_W0_TIMESTAMP FIELD32(0x00000400)
#define TXD_W0_RTS FIELD32(0x00000800)
#define TXD_W0_IFS FIELD32(0x00006000)
#define TXD_W0_RETRY_MODE FIELD32(0x00008000)
#define TXD_W0_AGC FIELD32(0x00ff0000)
#define TXD_W0_R2 FIELD32(0xff000000)
/*
* Word1
*/
#define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
/*
* Word2
*/
#define TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
#define TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000)
/*
* Word3 & 4: PLCP information
*/
#define TXD_W3_PLCP_SIGNAL FIELD32(0x0000ffff)
#define TXD_W3_PLCP_SERVICE FIELD32(0xffff0000)
#define TXD_W4_PLCP_LENGTH_LOW FIELD32(0x0000ffff)
#define TXD_W4_PLCP_LENGTH_HIGH FIELD32(0xffff0000)
/*
* Word5
*/
#define TXD_W5_BBCR4 FIELD32(0x0000ffff)
#define TXD_W5_AGC_REG FIELD32(0x007f0000)
#define TXD_W5_AGC_REG_VALID FIELD32(0x00800000)
#define TXD_W5_XXX_REG FIELD32(0x7f000000)
#define TXD_W5_XXX_REG_VALID FIELD32(0x80000000)
/*
* Word6
*/
#define TXD_W6_SK_BUFF FIELD32(0xffffffff)
/*
* Word7
*/
#define TXD_W7_RESERVED FIELD32(0xffffffff)
/*
* RX descriptor format for RX Ring.
*/
/*
* Word0
*/
#define RXD_W0_OWNER_NIC FIELD32(0x00000001)
#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
#define RXD_W0_MULTICAST FIELD32(0x00000004)
#define RXD_W0_BROADCAST FIELD32(0x00000008)
#define RXD_W0_MY_BSS FIELD32(0x00000010)
#define RXD_W0_CRC FIELD32(0x00000020)
#define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
#define RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000)
/*
* Word1
*/
#define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
/*
* Word2
*/
#define RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
#define RXD_W2_SIGNAL FIELD32(0x00ff0000)
#define RXD_W2_RSSI FIELD32(0xff000000)
/*
* Word3
*/
#define RXD_W3_BBR2 FIELD32(0x000000ff)
#define RXD_W3_BBR3 FIELD32(0x0000ff00)
#define RXD_W3_BBR4 FIELD32(0x00ff0000)
#define RXD_W3_BBR5 FIELD32(0xff000000)
/*
* Word4
*/
#define RXD_W4_RX_END_TIME FIELD32(0xffffffff)
/*
* Word5 & 6 & 7: Reserved
*/
#define RXD_W5_RESERVED FIELD32(0xffffffff)
#define RXD_W6_RESERVED FIELD32(0xffffffff)
#define RXD_W7_RESERVED FIELD32(0xffffffff)
/*
* Macro's for converting txpower from EEPROM to dscape value
* and from dscape value to register value.
* NOTE: Logics in rt2400pci for txpower are reversed
* compared to the other rt2x00 drivers. A higher txpower
* value means that the txpower must be lowered. This is
* important when converting the value coming from the
* dscape stack to the rt2400 acceptable value.
*/
#define MIN_TXPOWER 31
#define MAX_TXPOWER 62
#define DEFAULT_TXPOWER 39
#define TXPOWER_FROM_DEV(__txpower) \
({ \
((__txpower) > MAX_TXPOWER) ? DEFAULT_TXPOWER - MIN_TXPOWER : \
((__txpower) < MIN_TXPOWER) ? DEFAULT_TXPOWER - MIN_TXPOWER : \
(((__txpower) - MAX_TXPOWER) + MIN_TXPOWER); \
})
#define TXPOWER_TO_DEV(__txpower) \
({ \
(__txpower) += MIN_TXPOWER; \
((__txpower) <= MIN_TXPOWER) ? MAX_TXPOWER : \
(((__txpower) >= MAX_TXPOWER) ? MIN_TXPOWER : \
(MAX_TXPOWER - ((__txpower) - MIN_TXPOWER))); \
})
#endif /* RT2400PCI_H */

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/*
Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2500usb
Abstract: Data structures and registers for the rt2500usb module.
Supported chipsets: RT2570.
*/
#ifndef RT2500USB_H
#define RT2500USB_H
/*
* RF chip defines.
*/
#define RF2522 0x0000
#define RF2523 0x0001
#define RF2524 0x0002
#define RF2525 0x0003
#define RF2525E 0x0005
#define RF5222 0x0010
/*
* Max RSSI value, required for RSSI <-> dBm conversion.
*/
#define MAX_RX_SSI 120
#define MAX_RX_NOISE -110
/*
* Register layout information.
*/
#define CSR_REG_BASE 0x0400
#define CSR_REG_SIZE 0x0100
#define EEPROM_BASE 0x0000
#define EEPROM_SIZE 0x006a
#define BBP_SIZE 0x0060
/*
* Control/Status Registers(CSR).
* Some values are set in TU, whereas 1 TU == 1024 us.
*/
/*
* MAC_CSR0: ASIC revision number.
*/
#define MAC_CSR0 0x0400
/*
* MAC_CSR1: System control.
*/
#define MAC_CSR1 0x0402
/*
* MAC_CSR2: STA MAC register 0.
*/
#define MAC_CSR2 0x0404
#define MAC_CSR2_BYTE0 FIELD16(0x00ff)
#define MAC_CSR2_BYTE1 FIELD16(0xff00)
/*
* MAC_CSR3: STA MAC register 1.
*/
#define MAC_CSR3 0x0406
#define MAC_CSR3_BYTE2 FIELD16(0x00ff)
#define MAC_CSR3_BYTE3 FIELD16(0xff00)
/*
* MAC_CSR4: STA MAC register 2.
*/
#define MAC_CSR4 0X0408
#define MAC_CSR4_BYTE4 FIELD16(0x00ff)
#define MAC_CSR4_BYTE5 FIELD16(0xff00)
/*
* MAC_CSR5: BSSID register 0.
*/
#define MAC_CSR5 0x040a
#define MAC_CSR5_BYTE0 FIELD16(0x00ff)
#define MAC_CSR5_BYTE1 FIELD16(0xff00)
/*
* MAC_CSR6: BSSID register 1.
*/
#define MAC_CSR6 0x040c
#define MAC_CSR6_BYTE2 FIELD16(0x00ff)
#define MAC_CSR6_BYTE3 FIELD16(0xff00)
/*
* MAC_CSR7: BSSID register 2.
*/
#define MAC_CSR7 0x040e
#define MAC_CSR7_BYTE4 FIELD16(0x00ff)
#define MAC_CSR7_BYTE5 FIELD16(0xff00)
/*
* MAC_CSR8: Max frame length.
*/
#define MAC_CSR8 0x0410
#define MAC_CSR8_MAX_FRAME_UNIT FIELD16(0x0fff)
/*
* Misc MAC_CSR registers.
* MAC_CSR9: Timer control.
* MAC_CSR10: Slot time.
* MAC_CSR11: IFS.
* MAC_CSR12: EIFS.
* MAC_CSR13: Power mode0.
* MAC_CSR14: Power mode1.
* MAC_CSR15: Power saving transition0
* MAC_CSR16: Power saving transition1
*/
#define MAC_CSR9 0x0412
#define MAC_CSR10 0x0414
#define MAC_CSR11 0x0416
#define MAC_CSR12 0x0418
#define MAC_CSR13 0x041a
#define MAC_CSR14 0x041c
#define MAC_CSR15 0x041e
#define MAC_CSR16 0x0420
/*
* MAC_CSR17: Manual power control / status register.
* Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
* SET_STATE: Set state. Write 1 to trigger, self cleared.
* BBP_DESIRE_STATE: BBP desired state.
* RF_DESIRE_STATE: RF desired state.
* BBP_CURRENT_STATE: BBP current state.
* RF_CURRENT_STATE: RF current state.
* PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
*/
#define MAC_CSR17 0x0422
#define MAC_CSR17_SET_STATE FIELD16(0x0001)
#define MAC_CSR17_BBP_DESIRE_STATE FIELD16(0x0006)
#define MAC_CSR17_RF_DESIRE_STATE FIELD16(0x0018)
#define MAC_CSR17_BBP_CURR_STATE FIELD16(0x0060)
#define MAC_CSR17_RF_CURR_STATE FIELD16(0x0180)
#define MAC_CSR17_PUT_TO_SLEEP FIELD16(0x0200)
/*
* MAC_CSR18: Wakeup timer register.
* DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU.
* BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup.
* AUTO_WAKE: Enable auto wakeup / sleep mechanism.
*/
#define MAC_CSR18 0x0424
#define MAC_CSR18_DELAY_AFTER_BEACON FIELD16(0x00ff)
#define MAC_CSR18_BEACONS_BEFORE_WAKEUP FIELD16(0x7f00)
#define MAC_CSR18_AUTO_WAKE FIELD16(0x8000)
/*
* MAC_CSR19: GPIO control register.
*/
#define MAC_CSR19 0x0426
/*
* MAC_CSR20: LED control register.
* ACTIVITY: 0: idle, 1: active.
* LINK: 0: linkoff, 1: linkup.
* ACTIVITY_POLARITY: 0: active low, 1: active high.
*/
#define MAC_CSR20 0x0428
#define MAC_CSR20_ACTIVITY FIELD16(0x0001)
#define MAC_CSR20_LINK FIELD16(0x0002)
#define MAC_CSR20_ACTIVITY_POLARITY FIELD16(0x0004)
/*
* MAC_CSR21: LED control register.
* ON_PERIOD: On period, default 70ms.
* OFF_PERIOD: Off period, default 30ms.
*/
#define MAC_CSR21 0x042a
#define MAC_CSR21_ON_PERIOD FIELD16(0x00ff)
#define MAC_CSR21_OFF_PERIOD FIELD16(0xff00)
/*
* Collision window control register.
*/
#define MAC_CSR22 0x042c
/*
* Transmit related CSRs.
* Some values are set in TU, whereas 1 TU == 1024 us.
*/
/*
* TXRX_CSR0: Security control register.
*/
#define TXRX_CSR0 0x0440
#define TXRX_CSR0_ALGORITHM FIELD16(0x0007)
#define TXRX_CSR0_IV_OFFSET FIELD16(0x01f8)
#define TXRX_CSR0_KEY_ID FIELD16(0x1e00)
/*
* TXRX_CSR1: TX configuration.
* ACK_TIMEOUT: ACK Timeout in unit of 1-us.
* TSF_OFFSET: TSF offset in MAC header.
* AUTO_SEQUENCE: Let ASIC control frame sequence number.
*/
#define TXRX_CSR1 0x0442
#define TXRX_CSR1_ACK_TIMEOUT FIELD16(0x00ff)
#define TXRX_CSR1_TSF_OFFSET FIELD16(0x7f00)
#define TXRX_CSR1_AUTO_SEQUENCE FIELD16(0x8000)
/*
* TXRX_CSR2: RX control.
* DISABLE_RX: Disable rx engine.
* DROP_CRC: Drop crc error.
* DROP_PHYSICAL: Drop physical error.
* DROP_CONTROL: Drop control frame.
* DROP_NOT_TO_ME: Drop not to me unicast frame.
* DROP_TODS: Drop frame tods bit is true.
* DROP_VERSION_ERROR: Drop version error frame.
* DROP_MCAST: Drop multicast frames.
* DROP_BCAST: Drop broadcast frames.
*/
#define TXRX_CSR2 0x0444
#define TXRX_CSR2_DISABLE_RX FIELD16(0x0001)
#define TXRX_CSR2_DROP_CRC FIELD16(0x0002)
#define TXRX_CSR2_DROP_PHYSICAL FIELD16(0x0004)
#define TXRX_CSR2_DROP_CONTROL FIELD16(0x0008)
#define TXRX_CSR2_DROP_NOT_TO_ME FIELD16(0x0010)
#define TXRX_CSR2_DROP_TODS FIELD16(0x0020)
#define TXRX_CSR2_DROP_VERSION_ERROR FIELD16(0x0040)
#define TXRX_CSR2_DROP_MCAST FIELD16(0x0200)
#define TXRX_CSR2_DROP_BCAST FIELD16(0x0400)
/*
* RX BBP ID registers
* TXRX_CSR3: CCK RX BBP ID.
* TXRX_CSR4: OFDM RX BBP ID.
*/
#define TXRX_CSR3 0x0446
#define TXRX_CSR4 0x0448
/*
* TX BBP ID registers
* TXRX_CSR5: CCK TX BBP ID0.
* TXRX_CSR5: CCK TX BBP ID1.
* TXRX_CSR5: OFDM TX BBP ID0.
* TXRX_CSR5: OFDM TX BBP ID1.
*/
#define TXRX_CSR5 0x044a
#define TXRX_CSR6 0x044c
#define TXRX_CSR7 0x044e
#define TXRX_CSR8 0x0450
/*
* TXRX_CSR9: TX ACK time-out.
*/
#define TXRX_CSR9 0x0452
/*
* TXRX_CSR10: Auto responder control.
*/
#define TXRX_CSR10 0x0454
#define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004)
/*
* TXRX_CSR11: Auto responder basic rate.
*/
#define TXRX_CSR11 0x0456
/*
* ACK/CTS time registers.
*/
#define TXRX_CSR12 0x0458
#define TXRX_CSR13 0x045a
#define TXRX_CSR14 0x045c
#define TXRX_CSR15 0x045e
#define TXRX_CSR16 0x0460
#define TXRX_CSR17 0x0462
/*
* TXRX_CSR18: Synchronization control register.
*/
#define TXRX_CSR18 0x0464
#define TXRX_CSR18_OFFSET FIELD16(0x000f)
#define TXRX_CSR18_INTERVAL FIELD16(0xfff0)
/*
* TXRX_CSR19: Synchronization control register.
* TSF_COUNT: Enable TSF auto counting.
* TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
* TBCN: Enable Tbcn with reload value.
* BEACON_GEN: Enable beacon generator.
*/
#define TXRX_CSR19 0x0466
#define TXRX_CSR19_TSF_COUNT FIELD16(0x0001)
#define TXRX_CSR19_TSF_SYNC FIELD16(0x0006)
#define TXRX_CSR19_TBCN FIELD16(0x0008)
#define TXRX_CSR19_BEACON_GEN FIELD16(0x0010)
/*
* TXRX_CSR20: Tx BEACON offset time control register.
* OFFSET: In units of usec.
* BCN_EXPECT_WINDOW: Default: 2^CWmin
*/
#define TXRX_CSR20 0x0468
#define TXRX_CSR20_OFFSET FIELD16(0x1fff)
#define TXRX_CSR20_BCN_EXPECT_WINDOW FIELD16(0xe000)
/*
* TXRX_CSR21
*/
#define TXRX_CSR21 0x046a
/*
* Encryption related CSRs.
*
*/
/*
* SEC_CSR0-SEC_CSR7: Shared key 0, word 0-7
*/
#define SEC_CSR0 0x0480
#define SEC_CSR1 0x0482
#define SEC_CSR2 0x0484
#define SEC_CSR3 0x0486
#define SEC_CSR4 0x0488
#define SEC_CSR5 0x048a
#define SEC_CSR6 0x048c
#define SEC_CSR7 0x048e
/*
* SEC_CSR8-SEC_CSR15: Shared key 1, word 0-7
*/
#define SEC_CSR8 0x0490
#define SEC_CSR9 0x0492
#define SEC_CSR10 0x0494
#define SEC_CSR11 0x0496
#define SEC_CSR12 0x0498
#define SEC_CSR13 0x049a
#define SEC_CSR14 0x049c
#define SEC_CSR15 0x049e
/*
* SEC_CSR16-SEC_CSR23: Shared key 2, word 0-7
*/
#define SEC_CSR16 0x04a0
#define SEC_CSR17 0x04a2
#define SEC_CSR18 0X04A4
#define SEC_CSR19 0x04a6
#define SEC_CSR20 0x04a8
#define SEC_CSR21 0x04aa
#define SEC_CSR22 0x04ac
#define SEC_CSR23 0x04ae
/*
* SEC_CSR24-SEC_CSR31: Shared key 3, word 0-7
*/
#define SEC_CSR24 0x04b0
#define SEC_CSR25 0x04b2
#define SEC_CSR26 0x04b4
#define SEC_CSR27 0x04b6
#define SEC_CSR28 0x04b8
#define SEC_CSR29 0x04ba
#define SEC_CSR30 0x04bc
#define SEC_CSR31 0x04be
/*
* PHY control registers.
*/
/*
* PHY_CSR0: RF switching timing control.
*/
#define PHY_CSR0 0x04c0
/*
* PHY_CSR1: TX PA configuration.
*/
#define PHY_CSR1 0x04c2
/*
* MAC configuration registers.
* PHY_CSR2: TX MAC configuration.
* PHY_CSR3: RX MAC configuration.
*/
#define PHY_CSR2 0x04c4
#define PHY_CSR3 0x04c6
/*
* PHY_CSR4: Interface configuration.
*/
#define PHY_CSR4 0x04c8
/*
* BBP pre-TX registers.
* PHY_CSR5: BBP pre-TX CCK.
*/
#define PHY_CSR5 0x04ca
#define PHY_CSR5_CCK FIELD16(0x0003)
#define PHY_CSR5_CCK_FLIP FIELD16(0x0004)
/*
* BBP pre-TX registers.
* PHY_CSR6: BBP pre-TX OFDM.
*/
#define PHY_CSR6 0x04cc
#define PHY_CSR6_OFDM FIELD16(0x0003)
#define PHY_CSR6_OFDM_FLIP FIELD16(0x0004)
/*
* PHY_CSR7: BBP access register 0.
* BBP_DATA: BBP data.
* BBP_REG_ID: BBP register ID.
* BBP_READ_CONTROL: 0: write, 1: read.
*/
#define PHY_CSR7 0x04ce
#define PHY_CSR7_DATA FIELD16(0x00ff)
#define PHY_CSR7_REG_ID FIELD16(0x7f00)
#define PHY_CSR7_READ_CONTROL FIELD16(0x8000)
/*
* PHY_CSR8: BBP access register 1.
* BBP_BUSY: ASIC is busy execute BBP programming.
*/
#define PHY_CSR8 0x04d0
#define PHY_CSR8_BUSY FIELD16(0x0001)
/*
* PHY_CSR9: RF access register.
* RF_VALUE: Register value + id to program into rf/if.
*/
#define PHY_CSR9 0x04d2
#define PHY_CSR9_RF_VALUE FIELD16(0xffff)
/*
* PHY_CSR10: RF access register.
* RF_VALUE: Register value + id to program into rf/if.
* RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
* RF_IF_SELECT: Chip to program: 0: rf, 1: if.
* RF_PLL_LD: Rf pll_ld status.
* RF_BUSY: 1: asic is busy execute rf programming.
*/
#define PHY_CSR10 0x04d4
#define PHY_CSR10_RF_VALUE FIELD16(0x00ff)
#define PHY_CSR10_RF_NUMBER_OF_BITS FIELD16(0x1f00)
#define PHY_CSR10_RF_IF_SELECT FIELD16(0x2000)
#define PHY_CSR10_RF_PLL_LD FIELD16(0x4000)
#define PHY_CSR10_RF_BUSY FIELD16(0x8000)
/*
* STA_CSR0: FCS error count.
* FCS_ERROR: FCS error count, cleared when read.
*/
#define STA_CSR0 0x04e0
#define STA_CSR0_FCS_ERROR FIELD16(0xffff)
/*
* Statistic Register.
* STA_CSR1: PLCP error.
* STA_CSR2: LONG error.
* STA_CSR3: CCA false alarm.
* STA_CSR4: RX FIFO overflow.
* STA_CSR5: Beacon sent counter.
*/
#define STA_CSR1 0x04e2
#define STA_CSR2 0x04e4
#define STA_CSR3 0x04e6
#define STA_CSR4 0x04e8
#define STA_CSR5 0x04ea
#define STA_CSR6 0x04ec
#define STA_CSR7 0x04ee
#define STA_CSR8 0x04f0
#define STA_CSR9 0x04f2
#define STA_CSR10 0x04f4
/*
* RF registers.
*/
#define RF1_TUNER FIELD32(0x00020000)
#define RF3_TUNER FIELD32(0x00000100)
#define RF3_TXPOWER FIELD32(0x00003e00)
/*
* EEPROM contents.
*/
/*
* HW MAC address.
*/
#define EEPROM_MAC_ADDR_0 0x0002
#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
#define EEPROM_MAC_ADDR1 0x0003
#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
#define EEPROM_MAC_ADDR_2 0x0004
#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
/*
* EEPROM antenna.
* ANTENNA_NUM: Number of antenna's.
* TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
* RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
* LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd.
* DYN_TXAGC: Dynamic TX AGC control.
* HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
* RF_TYPE: Rf_type of this adapter.
*/
#define EEPROM_ANTENNA 0x000b
#define EEPROM_ANTENNA_NUM FIELD16(0x0003)
#define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
#define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
#define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0)
#define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
#define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
#define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
/*
* EEPROM NIC config.
* CARDBUS_ACCEL: 0: enable, 1: disable.
* DYN_BBP_TUNE: 0: enable, 1: disable.
* CCK_TX_POWER: CCK TX power compensation.
*/
#define EEPROM_NIC 0x000c
#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001)
#define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002)
#define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c)
/*
* EEPROM geography.
* GEO: Default geography setting for device.
*/
#define EEPROM_GEOGRAPHY 0x000d
#define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00)
/*
* EEPROM BBP.
*/
#define EEPROM_BBP_START 0x000e
#define EEPROM_BBP_SIZE 16
#define EEPROM_BBP_VALUE FIELD16(0x00ff)
#define EEPROM_BBP_REG_ID FIELD16(0xff00)
/*
* EEPROM TXPOWER
*/
#define EEPROM_TXPOWER_START 0x001e
#define EEPROM_TXPOWER_SIZE 7
#define EEPROM_TXPOWER_1 FIELD16(0x00ff)
#define EEPROM_TXPOWER_2 FIELD16(0xff00)
/*
* EEPROM Tuning threshold
*/
#define EEPROM_BBPTUNE 0x0030
#define EEPROM_BBPTUNE_THRESHOLD FIELD16(0x00ff)
/*
* EEPROM BBP R24 Tuning.
*/
#define EEPROM_BBPTUNE_R24 0x0031
#define EEPROM_BBPTUNE_R24_LOW FIELD16(0x00ff)
#define EEPROM_BBPTUNE_R24_HIGH FIELD16(0xff00)
/*
* EEPROM BBP R25 Tuning.
*/
#define EEPROM_BBPTUNE_R25 0x0032
#define EEPROM_BBPTUNE_R25_LOW FIELD16(0x00ff)
#define EEPROM_BBPTUNE_R25_HIGH FIELD16(0xff00)
/*
* EEPROM BBP R24 Tuning.
*/
#define EEPROM_BBPTUNE_R61 0x0033
#define EEPROM_BBPTUNE_R61_LOW FIELD16(0x00ff)
#define EEPROM_BBPTUNE_R61_HIGH FIELD16(0xff00)
/*
* EEPROM BBP VGC Tuning.
*/
#define EEPROM_BBPTUNE_VGC 0x0034
#define EEPROM_BBPTUNE_VGCUPPER FIELD16(0x00ff)
/*
* EEPROM BBP R17 Tuning.
*/
#define EEPROM_BBPTUNE_R17 0x0035
#define EEPROM_BBPTUNE_R17_LOW FIELD16(0x00ff)
#define EEPROM_BBPTUNE_R17_HIGH FIELD16(0xff00)
/*
* RSSI <-> dBm offset calibration
*/
#define EEPROM_CALIBRATE_OFFSET 0x0036
#define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff)
/*
* BBP content.
* The wordsize of the BBP is 8 bits.
*/
/*
* BBP_R2: TX antenna control
*/
#define BBP_R2_TX_ANTENNA FIELD8(0x03)
#define BBP_R2_TX_IQ_FLIP FIELD8(0x04)
/*
* BBP_R14: RX antenna control
*/
#define BBP_R14_RX_ANTENNA FIELD8(0x03)
#define BBP_R14_RX_IQ_FLIP FIELD8(0x04)
/*
* DMA descriptor defines.
*/
#define TXD_DESC_SIZE ( 5 * sizeof(struct data_desc) )
#define RXD_DESC_SIZE ( 4 * sizeof(struct data_desc) )
/*
* TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
*/
/*
* Word0
*/
#define TXD_W0_PACKET_ID FIELD32(0x0000000f)
#define TXD_W0_RETRY_LIMIT FIELD32(0x000000f0)
#define TXD_W0_MORE_FRAG FIELD32(0x00000100)
#define TXD_W0_ACK FIELD32(0x00000200)
#define TXD_W0_TIMESTAMP FIELD32(0x00000400)
#define TXD_W0_OFDM FIELD32(0x00000800)
#define TXD_W0_NEW_SEQ FIELD32(0x00001000)
#define TXD_W0_IFS FIELD32(0x00006000)
#define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
#define TXD_W0_CIPHER FIELD32(0x20000000)
#define TXD_W0_KEY_ID FIELD32(0xc0000000)
/*
* Word1
*/
#define TXD_W1_IV_OFFSET FIELD32(0x0000003f)
#define TXD_W1_AIFS FIELD32(0x000000c0)
#define TXD_W1_CWMIN FIELD32(0x00000f00)
#define TXD_W1_CWMAX FIELD32(0x0000f000)
/*
* Word2: PLCP information
*/
#define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
#define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
#define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
#define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
/*
* Word3
*/
#define TXD_W3_IV FIELD32(0xffffffff)
/*
* Word4
*/
#define TXD_W4_EIV FIELD32(0xffffffff)
/*
* RX descriptor format for RX Ring.
*/
/*
* Word0
*/
#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
#define RXD_W0_MULTICAST FIELD32(0x00000004)
#define RXD_W0_BROADCAST FIELD32(0x00000008)
#define RXD_W0_MY_BSS FIELD32(0x00000010)
#define RXD_W0_CRC FIELD32(0x00000020)
#define RXD_W0_OFDM FIELD32(0x00000040)
#define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
#define RXD_W0_CIPHER FIELD32(0x00000100)
#define RXD_W0_CI_ERROR FIELD32(0x00000200)
#define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
/*
* Word1
*/
#define RXD_W1_RSSI FIELD32(0x000000ff)
#define RXD_W1_SIGNAL FIELD32(0x0000ff00)
/*
* Word2
*/
#define RXD_W2_IV FIELD32(0xffffffff)
/*
* Word3
*/
#define RXD_W3_EIV FIELD32(0xffffffff)
/*
* Macro's for converting txpower from EEPROM to dscape value
* and from dscape value to register value.
*/
#define MIN_TXPOWER 0
#define MAX_TXPOWER 31
#define DEFAULT_TXPOWER 24
#define TXPOWER_FROM_DEV(__txpower) \
({ \
((__txpower) > MAX_TXPOWER) ? \
DEFAULT_TXPOWER : (__txpower); \
})
#define TXPOWER_TO_DEV(__txpower) \
({ \
((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
(((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
(__txpower)); \
})
/*
* Interrupt functions.
*/
static void rt2500usb_interrupt_rxdone(struct urb *urb);
#endif /* RT2500USB_H */

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package/rt2x00/src/rt2x00.h Normal file
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60
package/rt2x00/src/rt2x00_compat.h Normal file
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/*
* RT2X00 Compatability fixes for specific kernels.
*/
#ifndef RT2X00_COMPAT_H
#define RT2X00_COMPAT_H
/*
* First include the 2 config headers.
* The rt2x00_config.h should overrule
* the kernel configuration.
*/
#include <linux/autoconf.h>
#include "rt2x00_config.h"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/version.h>
/*
* Check minimal requirements.
*/
#if (!defined(CONFIG_MAC80211) && !defined(CONFIG_MAC80211_MODULE))
#error mac80211 support not enabled in kernel!
#endif
#if !defined(CONFIG_WLAN_80211)
#error 802.11 wlan card support not enabled in kernel!
#endif
#if (defined(CONFIG_RT2400PCI) || defined(CONFIG_RT2500PCI) || defined(CONFIG_RT61PCI))
#if (!defined(CONFIG_PCI) && !defined(CONFIG_PCI_MODULE))
#error PCI has been disabled in your kernel!
#endif
#if (!defined(CONFIG_EEPROM_93CX6) && !defined(CONFIG_EEPROM_93CX6_MODULE))
#error EEPROM_93CX6 has been disabled in your kernel!
#endif
#endif
#if (defined(CONFIG_RT2500USB) || defined(CONFIG_RT73USB))
#if (!defined(CONFIG_USB) && !defined(CONFIG_USB_MODULE))
#error USB has been disabled in your kernel!
#endif
#endif
#if (defined(CONFIG_RT61PCI) || defined(CONFIG_RT73USB))
#if (!defined(CONFIG_FW_LOADER) && !defined(CONFIG_FW_LOADER_MODULE))
#error Firmware loading has been disabled in your kernel!
#endif
#if (!defined(CONFIG_CRC_ITU_T) && !defined(CONFIG_CRC_ITU_T_MODULE))
#error CRC_ITU_T loading has been disabled in your kernel!
#endif
#endif
#if (defined(CONFIG_RT2400PCI_BUTTON) || defined(CONFIG_RT2500PCI_BUTTON) || defined(CONFIG_RT61PCI_BUTTON))
#if (!defined(CONFIG_RFKILL) && !defined (CONFIG_RFKILL_MODULE))
#error RFKILL has been disabled in your kernel!
#endif
#endif
#endif /* RT2X00_COMPAT_H */

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#ifndef CONFIG_RT2X00
#define CONFIG_RT2X00
#endif
#ifndef CONFIG_RT2X00_DEBUG
#define CONFIG_RT2X00_DEBUG
#endif
#ifndef CONFIG_RT2X00_DEBUGFS
#define CONFIG_RT2X00_DEBUGFS
#endif
#undef CONFIG_RT2X00_ASM
#ifndef CONFIG_RT2400PCI
#define CONFIG_RT2400PCI
#endif
#undef CONFIG_RT2400PCI_BUTTON
#ifndef CONFIG_RT2500PCI
#define CONFIG_RT2500PCI
#endif
#undef CONFIG_RT2500PCI_BUTTON
#ifndef CONFIG_RT2500USB
#define CONFIG_RT2500USB
#endif
#ifndef CONFIG_RT61PCI
#define CONFIG_RT61PCI
#endif
#undef CONFIG_RT61PCI_BUTTON
#ifndef CONFIG_RT73USB
#define CONFIG_RT73USB
#endif
#ifndef CONFIG_D80211
#define CONFIG_D80211
#endif
#ifndef CONFIG_D80211_DEBUG
#define CONFIG_D80211_DEBUG
#endif
#undef CONFIG_D80211_ASM
#ifndef CONFIG_CRC_ITU_T
#define CONFIG_CRC_ITU_T
#endif
#undef CONFIG_CRC_ITU_T_ASM
#ifndef CONFIG_EEPROM_93CX6
#define CONFIG_EEPROM_93CX6
#endif
#undef CONFIG_EEPROM_93CX6_ASM
#undef CONFIG_RFKILL
#undef CONFIG_RFKILL_ASM

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package/rt2x00/src/rt2x00debug.c Normal file
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/*
Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2x00lib
Abstract: rt2x00 debugfs specific routines.
Supported chipsets: RT2460, RT2560, RT2570,
rt2561, rt2561s, rt2661, rt2571W & rt2671.
*/
#include <linux/debugfs.h>
#include <asm/uaccess.h>
#include "rt2x00.h"
#define PRINT_REG8_STR ( "0x%.2x\n" )
#define PRINT_REG16_STR ( "0x%.4x\n" )
#define PRINT_REG32_STR ( "0x%.8x\n" )
#define PRINT_REG_LEN_MAX ( 16 )
#define PRINT_LINE_LEN_MAX ( 32 )
struct rt2x00debug_intf {
/*
* Pointer to driver structure where
* this debugfs entry belongs to.
*/
struct rt2x00_dev *rt2x00dev;
/*
* Reference to the rt2x00debug structure
* which can be used to communicate with
* the registers.
*/
const struct rt2x00debug *debug;
/*
* Debugfs entries for:
* - driver folder
* - driver file
* - chipset file
* - register offset/value files
* - eeprom offset/value files
* - bbp offset/value files
*/
struct dentry *driver_folder;
struct dentry *driver_entry;
struct dentry *chipset_entry;
struct dentry *csr_off_entry;
struct dentry *csr_val_entry;
struct dentry *eeprom_off_entry;
struct dentry *eeprom_val_entry;
struct dentry *bbp_off_entry;
struct dentry *bbp_val_entry;
/*
* Driver and chipset files will use a data buffer
* that has been created in advance. This will simplify
* the code since we can use the debugfs functions.
*/
struct debugfs_blob_wrapper driver_blob;
struct debugfs_blob_wrapper chipset_blob;
/*
* Requested offset for each register type.
*/
unsigned int offset_csr;
unsigned int offset_eeprom;
unsigned int offset_bbp;
};
static int rt2x00debug_file_open(struct inode *inode, struct file *file)
{
struct rt2x00debug_intf *intf = inode->i_private;
file->private_data = inode->i_private;
if (!try_module_get(intf->debug->owner))
return -EBUSY;
return 0;
}
static int rt2x00debug_file_release(struct inode *inode, struct file *file)
{
struct rt2x00debug_intf *intf = file->private_data;
module_put(intf->debug->owner);
return 0;
}
static ssize_t rt2x00debug_file_read(void *device, char __user *buf,
loff_t *offset, unsigned int word, const struct rt2x00debug_reg *reg)
{
unsigned long value;
unsigned int size;
char *line;
if (*offset)
return 0;
line = kzalloc(PRINT_REG_LEN_MAX, GFP_KERNEL);
if (!line)
return -ENOMEM;
reg->read(device, word, &value);
if (reg->word_size == sizeof(u8))
size = sprintf(line, PRINT_REG8_STR, (u8)value);
else if (reg->word_size == sizeof(u16))
size = sprintf(line, PRINT_REG16_STR, (u16)value);
else
size = sprintf(line, PRINT_REG32_STR, (u32)value);
if (copy_to_user(buf, line, size))
goto exit;
kfree(line);
*offset += size;
return size;
exit:
kfree(line);
return -EFAULT;
}
static ssize_t rt2x00debug_file_write(void *device, const char __user *buf,
loff_t *offset, unsigned int word, unsigned int length,
const struct rt2x00debug_reg *reg)
{
unsigned long value;
int size;
char *line;
line = kzalloc(length, GFP_KERNEL);
if (!line)
return -ENOMEM;
if (copy_from_user(line, buf, length))
goto exit;
size = strlen(line);
value = simple_strtoul(line, NULL, 0);
reg->write(device, word, &value);
kfree(line);
*offset += size;
return size;
exit:
kfree(line);
return -EFAULT;
}
#define RT2X00DEBUGFS_OPS_READ(__name) \
static ssize_t rt2x00debug_read_##__name(struct file *file, \
char __user *buf, size_t length, loff_t *offset) \
{ \
struct rt2x00debug_intf *intf = file->private_data; \
const struct rt2x00debug *debug = intf->debug; \
const struct rt2x00debug_reg *reg = &debug->reg_##__name;\
\
if (intf->offset_##__name > reg->word_count) \
return -EINVAL; \
\
return rt2x00debug_file_read(intf->rt2x00dev, buf, \
offset, intf->offset_##__name, reg); \
}
RT2X00DEBUGFS_OPS_READ(csr);
RT2X00DEBUGFS_OPS_READ(eeprom);
RT2X00DEBUGFS_OPS_READ(bbp);
#define RT2X00DEBUGFS_OPS_WRITE(__name) \
static ssize_t rt2x00debug_write_##__name(struct file *file, \
const char __user *buf, size_t length, loff_t *offset) \
{ \
struct rt2x00debug_intf *intf = file->private_data; \
const struct rt2x00debug *debug = intf->debug; \
const struct rt2x00debug_reg *reg = &debug->reg_##__name;\
\
if (intf->offset_##__name > reg->word_count) \
return -EINVAL; \
\
return rt2x00debug_file_write(intf->rt2x00dev, buf, \
offset, intf->offset_##__name, length, reg); \
}
RT2X00DEBUGFS_OPS_WRITE(csr);
RT2X00DEBUGFS_OPS_WRITE(eeprom);
RT2X00DEBUGFS_OPS_WRITE(bbp);
#define RT2X00DEBUGFS_OPS(__name) \
static const struct file_operations rt2x00debug_fop_##__name = {\
.owner = THIS_MODULE, \
.read = rt2x00debug_read_##__name, \
.write = rt2x00debug_write_##__name, \
.open = rt2x00debug_file_open, \
.release = rt2x00debug_file_release, \
};
RT2X00DEBUGFS_OPS(csr);
RT2X00DEBUGFS_OPS(eeprom);
RT2X00DEBUGFS_OPS(bbp);
static struct dentry *rt2x00debug_create_file_driver(const char *name,
struct rt2x00debug_intf *intf, struct debugfs_blob_wrapper *blob)
{
char *data;
data = kzalloc(3 * PRINT_LINE_LEN_MAX, GFP_KERNEL);
if (!data)
return NULL;
blob->data = data;
data += sprintf(data, "driver: %s\n", intf->rt2x00dev->ops->name);
data += sprintf(data, "version: %s\n", DRV_VERSION);
data += sprintf(data, "compiled: %s %s\n", __DATE__, __TIME__);
blob->size = strlen(blob->data);
return debugfs_create_blob(name, S_IRUGO, intf->driver_folder, blob);
}
static struct dentry *rt2x00debug_create_file_chipset(const char *name,
struct rt2x00debug_intf *intf, struct debugfs_blob_wrapper *blob)
{
const struct rt2x00debug *debug = intf->debug;
char *data;
data = kzalloc(3 * PRINT_LINE_LEN_MAX, GFP_KERNEL);
if (!data)
return NULL;
blob->data = data;
data += sprintf(data, "csr length: %d\n", debug->reg_csr.word_count);
data += sprintf(data, "eeprom length: %d\n",
debug->reg_eeprom.word_count);
data += sprintf(data, "bbp length: %d\n", debug->reg_bbp.word_count);
blob->size = strlen(blob->data);
return debugfs_create_blob(name, S_IRUGO, intf->driver_folder, blob);
}
void rt2x00debug_register(struct rt2x00_dev *rt2x00dev)
{
const struct rt2x00debug *debug = rt2x00dev->ops->debugfs;
struct rt2x00debug_intf *intf;
intf = kzalloc(sizeof(struct rt2x00debug_intf), GFP_KERNEL);
if (!intf) {
ERROR(rt2x00dev, "Failed to allocate debug handler.\n");
return;
}
intf->debug = debug;
intf->rt2x00dev = rt2x00dev;
rt2x00dev->debugfs_intf = intf;
intf->driver_folder = debugfs_create_dir(intf->rt2x00dev->ops->name,
rt2x00dev->hw->wiphy->debugfsdir);
if (IS_ERR(intf->driver_folder))
goto exit;
intf->driver_entry = rt2x00debug_create_file_driver("driver",
intf, &intf->driver_blob);
if (IS_ERR(intf->driver_entry))
goto exit;
intf->chipset_entry = rt2x00debug_create_file_chipset("chipset",
intf, &intf->chipset_blob);
if (IS_ERR(intf->chipset_entry))
goto exit;
intf->csr_off_entry = debugfs_create_u32("csr_offset",
S_IRUGO | S_IWUSR, intf->driver_folder, &intf->offset_csr);
if (IS_ERR(intf->csr_off_entry))
goto exit;
intf->csr_val_entry = debugfs_create_file("csr_value",
S_IRUGO | S_IWUSR, intf->driver_folder, intf,
&rt2x00debug_fop_csr);
if (IS_ERR(intf->csr_val_entry))
goto exit;
intf->eeprom_off_entry = debugfs_create_u32("eeprom_offset",
S_IRUGO | S_IWUSR, intf->driver_folder, &intf->offset_eeprom);
if (IS_ERR(intf->eeprom_off_entry))
goto exit;
intf->eeprom_val_entry = debugfs_create_file("eeprom_value",
S_IRUGO | S_IWUSR, intf->driver_folder, intf,
&rt2x00debug_fop_eeprom);
if (IS_ERR(intf->eeprom_val_entry))
goto exit;
intf->bbp_off_entry = debugfs_create_u32("bbp_offset",
S_IRUGO | S_IWUSR, intf->driver_folder, &intf->offset_bbp);
if (IS_ERR(intf->bbp_off_entry))
goto exit;
intf->bbp_val_entry = debugfs_create_file("bbp_value",
S_IRUGO | S_IWUSR, intf->driver_folder, intf,
&rt2x00debug_fop_bbp);
if (IS_ERR(intf->bbp_val_entry))
goto exit;
return;
exit:
rt2x00debug_deregister(rt2x00dev);
ERROR(rt2x00dev, "Failed to register debug handler.\n");
return;
}
void rt2x00debug_deregister(struct rt2x00_dev *rt2x00dev)
{
const struct rt2x00debug_intf *intf = rt2x00dev->debugfs_intf;
if (unlikely(!intf))
return;
debugfs_remove(intf->bbp_val_entry);
debugfs_remove(intf->bbp_off_entry);
debugfs_remove(intf->eeprom_val_entry);
debugfs_remove(intf->eeprom_off_entry);
debugfs_remove(intf->csr_val_entry);
debugfs_remove(intf->csr_off_entry);
debugfs_remove(intf->chipset_entry);
debugfs_remove(intf->driver_entry);
debugfs_remove(intf->driver_folder);
kfree(intf->chipset_blob.data);
kfree(intf->driver_blob.data);
kfree(intf);
rt2x00dev->debugfs_intf = NULL;
}

66
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/*
Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2x00debug
Abstract: Data structures for the rt2x00debug.
Supported chipsets: RT2460, RT2560, RT2570,
rt2561, rt2561s, rt2661, rt2571W & rt2671.
*/
#ifndef RT2X00DEBUG_H
#define RT2X00DEBUG_H
#include <net/wireless.h>
typedef void (debug_access_t)(struct rt2x00_dev *rt2x00dev,
const unsigned long word, void *data);
struct rt2x00debug_reg {
debug_access_t *read;
debug_access_t *write;
unsigned int word_size;
unsigned int word_count;
};
struct rt2x00debug {
/*
* Reference to the modules structure.
*/
struct module *owner;
/*
* Register access information.
*/
struct rt2x00debug_reg reg_csr;
struct rt2x00debug_reg reg_eeprom;
struct rt2x00debug_reg reg_bbp;
};
#ifdef CONFIG_RT2X00_LIB_DEBUGFS
void rt2x00debug_register(struct rt2x00_dev *rt2x00dev);
void rt2x00debug_deregister(struct rt2x00_dev *rt2x00dev);
#else /* CONFIG_RT2X00_LIB_DEBUGFS */
static inline void rt2x00debug_register(struct rt2x00_dev *rt2x00dev){}
static inline void rt2x00debug_deregister(struct rt2x00_dev *rt2x00dev){}
#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
#endif /* RT2X00DEBUG_H */

1082
package/rt2x00/src/rt2x00dev.c Normal file
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60
package/rt2x00/src/rt2x00dev.h Normal file
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/*
Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2x00lib
Abstract: Data structures for the rt2x00lib module.
Supported chipsets: RT2460, RT2560, RT2570,
rt2561, rt2561s, rt2661, rt2571W & rt2671.
*/
#ifndef RT2X00DEV_H
#define RT2X00DEV_H
#include "rt2x00debug.h"
#include "rt2x00firmware.h"
#include "rt2x00rfkill.h"
/*
* Radio control.
*/
int rt2x00lib_enable_radio(struct rt2x00_dev *rt2x00dev);
void rt2x00lib_disable_radio(struct rt2x00_dev *rt2x00dev);
void rt2x00lib_toggle_rx(struct rt2x00_dev *rt2x00dev, int enable);
/*
* Initialization/uninitialization handlers.
*/
int rt2x00lib_initialize(struct rt2x00_dev *rt2x00dev);
void rt2x00lib_uninitialize(struct rt2x00_dev *rt2x00dev);
/*
* Config handlers.
*/
void rt2x00lib_config_type(struct rt2x00_dev *rt2x00dev, const int type);
void rt2x00lib_config_phymode(struct rt2x00_dev *rt2x00dev, const int phymode);
void rt2x00lib_config_channel(struct rt2x00_dev *rt2x00dev, const int value,
const int channel, const int freq, const int txpower);
void rt2x00lib_config_promisc(struct rt2x00_dev *rt2x00dev, const int promisc);
void rt2x00lib_config_txpower(struct rt2x00_dev *rt2x00dev, const int txpower);
void rt2x00lib_config_antenna(struct rt2x00_dev *rt2x00dev,
const int antenna_tx, const int antenna_rx);
#endif /* RT2X00DEV_H */

124
package/rt2x00/src/rt2x00firmware.c Normal file
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/*
Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2x00lib
Abstract: rt2x00 firmware loading specific routines.
Supported chipsets: rt2561, rt2561s, rt2661, rt2571W & rt2671.
*/
/*
* Set enviroment defines for rt2x00.h
*/
#define DRV_NAME "rt2x00lib"
#include <linux/crc-itu-t.h>
#include <linux/firmware.h>
#include "rt2x00.h"
#include "rt2x00firmware.h"
static void rt2x00lib_load_firmware_continued(const struct firmware *fw,
void *context)
{
struct rt2x00_dev *rt2x00dev = context;
u16 crc;
u16 tmp;
if (!fw || !fw->size || !fw->data) {
ERROR(rt2x00dev, "Failed to read Firmware.\n");
goto exit_failed;
}
/*
* Validate the firmware using 16 bit CRC.
* The last 2 bytes of the firmware are the CRC
* so substract those 2 bytes from the CRC checksum,
* and set those 2 bytes to 0 when calculating CRC.
*/
tmp = 0;
crc = crc_itu_t(0, fw->data, fw->size - 2);
crc = crc_itu_t(crc, (u8*)&tmp, 2);
if (crc != (fw->data[fw->size - 2] << 8 | fw->data[fw->size - 1])) {
ERROR(rt2x00dev, "Firmware CRC error.\n");
goto exit_failed;
}
/*
* Send firmware to the device.
*/
if (rt2x00dev->ops->lib->load_firmware(rt2x00dev, fw->data, fw->size))
goto exit_failed;
INFO(rt2x00dev, "Firmware detected - version: %d.%d.\n",
fw->data[fw->size - 4], fw->data[fw->size - 3]);
__set_bit(FIRMWARE_LOADED, &rt2x00dev->flags);
return;
exit_failed:
rt2x00debug_deregister(rt2x00dev);
__set_bit(FIRMWARE_FAILED, &rt2x00dev->flags);
}
int rt2x00lib_load_firmware(struct rt2x00_dev *rt2x00dev)
{
char *fw_name;
int status = -EINVAL;
/*
* Read correct firmware from harddisk.
*/
fw_name = rt2x00dev->ops->lib->get_fw_name(rt2x00dev);
BUG_ON(fw_name == NULL);
INFO(rt2x00dev, "Loading firmware file '%s'.\n", fw_name);
status = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
fw_name, rt2x00dev->device, rt2x00dev,
&rt2x00lib_load_firmware_continued);
if (status)
ERROR(rt2x00dev, "Failed to request Firmware.\n");
return status;
}
int rt2x00lib_load_firmware_wait(struct rt2x00_dev *rt2x00dev)
{
unsigned int i;
if (!test_bit(FIRMWARE_REQUIRED, &rt2x00dev->flags))
return 0;
for (i = 0; i < 150; i++) {
if (test_bit(FIRMWARE_FAILED, &rt2x00dev->flags))
return -EIO;
if (test_bit(FIRMWARE_LOADED, &rt2x00dev->flags))
return 0;
msleep(20);
}
ERROR(rt2x00dev, "Firmware loading timed out.\n");
return -ETIMEDOUT;
}

49
package/rt2x00/src/rt2x00firmware.h Normal file
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/*
Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2x00lib
Abstract: Data structures for the firmware loader.
Supported chipsets: rt2561, rt2561s, rt2661, rt2571W & rt2671.
*/
#ifndef RT2X00FIRMWARE_H
#define RT2X00FIRMWARE_H
#ifdef CONFIG_RT2X00_LIB_FIRMWARE
int rt2x00lib_load_firmware(struct rt2x00_dev *rt2x00dev);
int rt2x00lib_load_firmware_wait(struct rt2x00_dev *rt2x00dev);
#else /* CONFIG_RT2X00_LIB_FIRMWARE */
static inline int rt2x00lib_load_firmware(struct rt2x00_dev *rt2x00dev)
{
/*
* This shouldn't happen.
*/
BUG();
return 0;
}
static inline int rt2x00lib_load_firmware_wait(struct rt2x00_dev *rt2x00dev)
{
return 0;
}
#endif /* CONFIG_RT2X00_LIB_FIRMWARE */
#endif /* RT2X00FIRMWARE_H */

118
package/rt2x00/src/rt2x00lib.h Normal file
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/*
Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2x00lib
Abstract: Data structures for the rt2x00lib module.
Supported chipsets: RT2460, RT2560, RT2570,
rt2561, rt2561s, rt2661, rt2571W & rt2671.
*/
#ifndef RT2X00LIB_H
#define RT2X00LIB_H
struct rt2x00_dev;
struct data_desc;
struct data_entry_desc;
struct data_entry;
/*
* Details about the supported modes, rates and channels
* of a particular chipset. This is used by rt2x00lib
* to build the ieee80211_hw_mode array for mac80211.
*/
struct hw_mode_spec {
/*
* Default mac address.
*/
char *mac_addr;
/*
* Number of modes, rates and channels.
*/
int num_modes;
int num_rates;
int num_channels;
/*
* txpower values.
*/
const u8 *tx_power_a;
const u8 *tx_power_bg;
u8 tx_power_default;
/*
* Device/chipset specific value.
*/
const u32 *chan_val_a;
const u32 *chan_val_bg;
};
/*
* Driver allocation handlers.
*/
int rt2x00lib_probe_dev(struct rt2x00_dev *rt2x00dev);
void rt2x00lib_remove_dev(struct rt2x00_dev *rt2x00dev);
/*
* Driver status handlers.
*/
int rt2x00lib_suspend(struct rt2x00_dev *rt2x00dev, pm_message_t state);
int rt2x00lib_resume(struct rt2x00_dev *rt2x00dev);
/*
* Interrupt context handlers.
*/
void rt2x00lib_txdone(struct data_entry *entry,
const int status, const int retry);
void rt2x00lib_rxdone(struct data_entry *entry, char *data,
const int size, const int signal, const int rssi, const int ofdm);
/*
* TX descriptor initializer
*/
void rt2x00lib_write_tx_desc(struct rt2x00_dev *rt2x00dev,
struct data_entry *entry, struct data_desc *txd,
struct ieee80211_hdr *ieee80211hdr, unsigned int length,
struct ieee80211_tx_control *control);
/*
* mac80211 handlers.
*/
int rt2x00lib_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
struct ieee80211_tx_control *control);
int rt2x00lib_reset(struct ieee80211_hw *hw);
int rt2x00lib_open(struct ieee80211_hw *hw);
int rt2x00lib_stop(struct ieee80211_hw *hw);
int rt2x00lib_add_interface(struct ieee80211_hw *hw,
struct ieee80211_if_init_conf *conf);
void rt2x00lib_remove_interface(struct ieee80211_hw *hw,
struct ieee80211_if_init_conf *conf);
int rt2x00lib_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
int rt2x00lib_config_interface(struct ieee80211_hw *hw, int if_id,
struct ieee80211_if_conf *conf);
void rt2x00lib_set_multicast_list(struct ieee80211_hw *hw,
unsigned short flags, int mc_count);
int rt2x00lib_get_tx_stats(struct ieee80211_hw *hw,
struct ieee80211_tx_queue_stats *stats);
int rt2x00lib_conf_tx(struct ieee80211_hw *hw, int queue,
const struct ieee80211_tx_queue_params *params);
#endif /* RT2X00LIB_H */

441
package/rt2x00/src/rt2x00mac.c Normal file
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@ -0,0 +1,441 @@
/*
Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2x00lib
Abstract: rt2x00 generic mac80211 routines.
Supported chipsets: RT2460, RT2560, RT2570,
rt2561, rt2561s, rt2661, rt2571W & rt2671.
*/
/*
* Set enviroment defines for rt2x00.h
*/
#define DRV_NAME "rt2x00lib"
#include <linux/netdevice.h>
#include "rt2x00.h"
#include "rt2x00dev.h"
static int rt2x00_tx_rts_cts(struct rt2x00_dev *rt2x00dev,
struct data_ring *ring, struct sk_buff *frag_skb,
struct ieee80211_tx_control *control)
{
struct sk_buff *skb;
int size;
if (control->flags & IEEE80211_TXCTL_USE_CTS_PROTECT)
size = sizeof(struct ieee80211_cts);
else
size = sizeof(struct ieee80211_rts);
skb = dev_alloc_skb(size + rt2x00dev->hw->extra_tx_headroom);
if (!skb) {
WARNING(rt2x00dev, "Failed to create RTS/CTS frame.\n");
return NETDEV_TX_BUSY;
}
skb_reserve(skb, rt2x00dev->hw->extra_tx_headroom);
skb_put(skb, size);
if (control->flags & IEEE80211_TXCTL_USE_CTS_PROTECT)
ieee80211_ctstoself_get(rt2x00dev->hw,
frag_skb->data, frag_skb->len, control,
(struct ieee80211_cts*)(skb->data));
else
ieee80211_rts_get(rt2x00dev->hw,
frag_skb->data, frag_skb->len, control,
(struct ieee80211_rts*)(skb->data));
if (rt2x00dev->ops->lib->write_tx_data(rt2x00dev, ring, skb, control)) {
WARNING(rt2x00dev, "Failed to send RTS/CTS frame.\n");
return NETDEV_TX_BUSY;
}
return NETDEV_TX_OK;
}
int rt2x00lib_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
struct ieee80211_tx_control *control)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr*)skb->data;
struct data_ring *ring;
u16 frame_control;
/*
* Determine which ring to put packet on.
*/
ring = rt2x00_get_ring(rt2x00dev, control->queue);
if (unlikely(!ring)) {
ERROR(rt2x00dev,
"Attempt to send packet over invalid queue %d.\n"
"Please file bug report to %s.\n",
control->queue, DRV_PROJECT);
dev_kfree_skb_any(skb);
return NETDEV_TX_OK;
}
/*
* If CTS/RTS is required. and this frame is not CTS or RTS,
* create and queue that frame first. But make sure we have
* at least enough entries available to send this CTS/RTS
* frame as well as the data frame.
*/
frame_control = le16_to_cpu(ieee80211hdr->frame_control);
if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS &&
!is_cts_frame(frame_control) && !is_rts_frame(frame_control)) {
if (rt2x00_ring_free(ring) <= 1)
return NETDEV_TX_BUSY;
if (rt2x00_tx_rts_cts(rt2x00dev, ring, skb, control))
return NETDEV_TX_BUSY;
}
if (rt2x00dev->ops->lib->write_tx_data(rt2x00dev, ring, skb, control))
return NETDEV_TX_BUSY;
if (rt2x00dev->ops->lib->kick_tx_queue)
rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
return NETDEV_TX_OK;
}
EXPORT_SYMBOL_GPL(rt2x00lib_tx);
int rt2x00lib_reset(struct ieee80211_hw *hw)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
rt2x00lib_disable_radio(rt2x00dev);
return rt2x00lib_enable_radio(rt2x00dev);
}
EXPORT_SYMBOL_GPL(rt2x00lib_reset);
int rt2x00lib_open(struct ieee80211_hw *hw)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
int status;
/*
* We must wait on the firmware before
* we can safely continue.
*/
status = rt2x00lib_load_firmware_wait(rt2x00dev);
if (status)
return status;
/*
* Initialize the device.
*/
status = rt2x00lib_initialize(rt2x00dev);
if (status)
return status;
/*
* Enable radio.
*/
status = rt2x00lib_enable_radio(rt2x00dev);
if (status) {
rt2x00lib_uninitialize(rt2x00dev);
return status;
}
return 0;
}
EXPORT_SYMBOL_GPL(rt2x00lib_open);
int rt2x00lib_stop(struct ieee80211_hw *hw)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
rt2x00lib_disable_radio(rt2x00dev);
return 0;
}
EXPORT_SYMBOL_GPL(rt2x00lib_stop);
int rt2x00lib_add_interface(struct ieee80211_hw *hw,
struct ieee80211_if_init_conf *conf)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
struct interface *intf = &rt2x00dev->interface;
/*
* We only support 1 non-monitor interface.
*/
if (conf->type != IEEE80211_IF_TYPE_MNTR &&
is_interface_present(&rt2x00dev->interface))
return -ENOBUFS;
/*
* We support muliple monitor mode interfaces.
* All we need to do is increase the monitor_count.
*/
if (conf->type == IEEE80211_IF_TYPE_MNTR) {
intf->monitor_count++;
} else {
intf->id = conf->if_id;
intf->type = conf->type;
if (conf->type == IEEE80211_IF_TYPE_AP)
memcpy(&intf->bssid, conf->mac_addr, ETH_ALEN);
intf->promisc = 0;
}
/*
* If this is the first interface which is being added,
* we should write the MAC address to the device.
*/
if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
rt2x00dev->ops->lib->config_mac_addr(rt2x00dev, conf->mac_addr);
/*
* Enable periodic link tuning if this is a non-monitor interface.
*/
if (conf->type != IEEE80211_IF_TYPE_MNTR)
rt2x00_start_link_tune(rt2x00dev);
return 0;
}
EXPORT_SYMBOL_GPL(rt2x00lib_add_interface);
void rt2x00lib_remove_interface(struct ieee80211_hw *hw,
struct ieee80211_if_init_conf *conf)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
struct interface *intf = &rt2x00dev->interface;
/*
* We only support 1 non-monitor interface.
*/
if (conf->type != IEEE80211_IF_TYPE_MNTR &&
!is_interface_present(&rt2x00dev->interface))
return;
/*
* We support muliple monitor mode interfaces.
* All we need to do is decrease the monitor_count.
*/
if (conf->type == IEEE80211_IF_TYPE_MNTR) {
intf->monitor_count--;
} else if (intf->type == conf->type) {
intf->id = 0;
intf->type = -EINVAL;
memset(&intf->bssid, 0x00, ETH_ALEN);
intf->promisc = 0;
}
/*
* When this is a non-monitor mode, stop the periodic link tuning.
*/
if (conf->type != IEEE80211_IF_TYPE_MNTR)
rt2x00_stop_link_tune(rt2x00dev);
/*
* Check if we still have 1 non-monitor or a monitor
* interface enabled. In that case we should update the
* registers.
*/
if (is_monitor_present(&rt2x00dev->interface) ^
is_interface_present(&rt2x00dev->interface)) {
if (is_interface_present(&rt2x00dev->interface))
rt2x00lib_config_type(rt2x00dev,
rt2x00dev->interface.type);
else
rt2x00lib_config_type(rt2x00dev,
IEEE80211_IF_TYPE_MNTR);
}
/*
* Check which interfaces have been disabled.
*/
if (!is_interface_present(&rt2x00dev->interface))
__clear_bit(INTERFACE_ENABLED, &rt2x00dev->flags);
else if (!is_monitor_present(&rt2x00dev->interface))
__clear_bit(INTERFACE_ENABLED_MONITOR, &rt2x00dev->flags);
}
EXPORT_SYMBOL_GPL(rt2x00lib_remove_interface);
int rt2x00lib_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
/*
* Check if we need to disable the radio,
* if this is not the case, at least the RX must be disabled.
*/
if (test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags)) {
if (!conf->radio_enabled)
rt2x00lib_disable_radio(rt2x00dev);
else
rt2x00lib_toggle_rx(rt2x00dev, 0);
}
rt2x00lib_config_phymode(rt2x00dev, conf->phymode);
rt2x00lib_config_channel(rt2x00dev, conf->channel_val,
conf->channel, conf->freq, conf->power_level);
rt2x00lib_config_txpower(rt2x00dev, conf->power_level);
rt2x00lib_config_antenna(rt2x00dev,
conf->antenna_sel_tx, conf->antenna_sel_rx);
rt2x00dev->ops->lib->config_duration(rt2x00dev,
(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME),
conf->beacon_int);
/*
* Reenable RX only if the radio should be on.
*/
if (test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
rt2x00lib_toggle_rx(rt2x00dev, 1);
else if (conf->radio_enabled)
return rt2x00lib_enable_radio(rt2x00dev);
return 0;
}
EXPORT_SYMBOL_GPL(rt2x00lib_config);
int rt2x00lib_config_interface(struct ieee80211_hw *hw, int if_id,
struct ieee80211_if_conf *conf)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
struct interface *intf = &rt2x00dev->interface;
int status;
/*
* Monitor mode does not need configuring.
* If the given type does not match the configured type,
* there has been a problem.
*/
if (conf->type == IEEE80211_IF_TYPE_MNTR)
return 0;
else if (conf->type != intf->type)
return -EINVAL;
/*
* If the interface does not work in master mode,
* then the bssid value in the interface structure
* should now be set.
*/
if (conf->type != IEEE80211_IF_TYPE_AP)
memcpy(&intf->bssid, conf->bssid, ETH_ALEN);
/*
* Enable configuration.
* For Monitor mode, promisc mode will be forced on.
*/
rt2x00lib_config_type(rt2x00dev, conf->type);
rt2x00lib_config_promisc(rt2x00dev, rt2x00dev->interface.promisc);
rt2x00dev->ops->lib->config_bssid(rt2x00dev, intf->bssid);
/*
* We only need to initialize the beacon when master mode is enabled.
*/
if (conf->type != IEEE80211_IF_TYPE_AP || !conf->beacon)
return 0;
status = rt2x00dev->ops->hw->beacon_update(rt2x00dev->hw,
conf->beacon, conf->beacon_control);
if (status)
dev_kfree_skb(conf->beacon);
return status;
}
EXPORT_SYMBOL_GPL(rt2x00lib_config_interface);
void rt2x00lib_set_multicast_list(struct ieee80211_hw *hw,
unsigned short flags, int mc_count)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
/*
* Promisc mode is forced on for Monitor interfaces.
*/
if (is_monitor_present(&rt2x00dev->interface))
return;
/*
* Check if the new state is different then the old state.
*/
if (test_bit(INTERFACE_ENABLED_PROMISC, &rt2x00dev->flags) ==
(flags & IFF_PROMISC))
return;
rt2x00dev->interface.promisc = (flags & IFF_PROMISC);
/*
* Schedule the link tuner if this does not run
* automatically. The link tuner will be automatically
* switched off when it is not required.
*/
if (!work_pending(&rt2x00dev->link.work.work))
queue_work(rt2x00dev->workqueue, &rt2x00dev->link.work.work);
}
EXPORT_SYMBOL_GPL(rt2x00lib_set_multicast_list);
int rt2x00lib_get_tx_stats(struct ieee80211_hw *hw,
struct ieee80211_tx_queue_stats *stats)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
unsigned int i;
for (i = 0; i < hw->queues; i++)
memcpy(&stats->data[i], &rt2x00dev->tx[i].stats,
sizeof(rt2x00dev->tx[i].stats));
return 0;
}
EXPORT_SYMBOL_GPL(rt2x00lib_get_tx_stats);
int rt2x00lib_conf_tx(struct ieee80211_hw *hw, int queue,
const struct ieee80211_tx_queue_params *params)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
struct data_ring *ring;
ring = rt2x00_get_ring(rt2x00dev, queue);
if (unlikely(!ring))
return -EINVAL;
/*
* The passed variables are stored as real value ((2^n)-1).
* Ralink registers require to know the bit number 'n'.
*/
if (params->cw_min)
ring->tx_params.cw_min = fls(params->cw_min);
else
ring->tx_params.cw_min = 5; /* cw_min: 2^5 = 32. */
if (params->cw_max)
ring->tx_params.cw_max = fls(params->cw_max);
else
ring->tx_params.cw_max = 10; /* cw_min: 2^10 = 1024. */
if (params->aifs)
ring->tx_params.aifs = params->aifs;
else
ring->tx_params.aifs = 2;
INFO(rt2x00dev,
"Configured TX ring %d - CWmin: %d, CWmax: %d, Aifs: %d.\n",
queue, ring->tx_params.cw_min, ring->tx_params.cw_max,
ring->tx_params.aifs);
return 0;
}
EXPORT_SYMBOL_GPL(rt2x00lib_conf_tx);

407
package/rt2x00/src/rt2x00pci.c Normal file
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/*
Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2x00pci
Abstract: rt2x00 generic pci device routines.
Supported chipsets: rt2460, rt2560, rt2561, rt2561s & rt2661.
*/
/*
* Set enviroment defines for rt2x00.h
*/
#define DRV_NAME "rt2x00pci"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/version.h>
#include <linux/init.h>
#include <linux/pci.h>
#include "rt2x00.h"
#include "rt2x00pci.h"
/*
* Beacon handlers.
*/
int rt2x00pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
struct ieee80211_tx_control *control)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
struct data_ring *ring =
rt2x00_get_ring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
struct data_entry *entry = rt2x00_get_data_entry(ring);
/*
* Just in case the ieee80211 doesn't set this,
* but we need this queue set for the descriptor
* initialization.
*/
control->queue = IEEE80211_TX_QUEUE_BEACON;
/*
* Update the beacon entry.
*/
memcpy(entry->data_addr, skb->data, skb->len);
rt2x00lib_write_tx_desc(rt2x00dev, entry, entry->priv,
(struct ieee80211_hdr*)skb->data, skb->len, control);
/*
* Enable beacon generation.
*/
rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
return 0;
}
EXPORT_SYMBOL_GPL(rt2x00pci_beacon_update);
void rt2x00pci_beacondone(struct rt2x00_dev *rt2x00dev, const int queue)
{
struct data_ring *ring = rt2x00_get_ring(rt2x00dev, queue);
struct data_entry *entry = rt2x00_get_data_entry(ring);
struct sk_buff *skb;
skb = ieee80211_beacon_get(rt2x00dev->hw,
rt2x00dev->interface.id, &entry->tx_status.control);
if (!skb)
return;
rt2x00dev->ops->hw->beacon_update(rt2x00dev->hw, skb,
&entry->tx_status.control);
dev_kfree_skb(skb);
}
EXPORT_SYMBOL_GPL(rt2x00pci_beacondone);
/*
* TX data handlers.
*/
int rt2x00pci_write_tx_data(struct rt2x00_dev *rt2x00dev,
struct data_ring *ring, struct sk_buff *skb,
struct ieee80211_tx_control *control)
{
struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr*)skb->data;
struct data_entry *entry = rt2x00_get_data_entry(ring);
struct data_desc *txd = entry->priv;
u32 word;
if (rt2x00_ring_full(ring)) {
ieee80211_stop_queue(rt2x00dev->hw, control->queue);
return -EINVAL;
}
rt2x00_desc_read(txd, 0, &word);
if (rt2x00_get_field32(word, TXD_ENTRY_AVAILABLE)) {
ERROR(rt2x00dev,
"Arrived at non-free entry in the non-full queue %d.\n"
"Please file bug report to %s.\n",
control->queue, DRV_PROJECT);
ieee80211_stop_queue(rt2x00dev->hw, control->queue);
return -EINVAL;
}
memcpy(entry->data_addr, skb->data, skb->len);
rt2x00lib_write_tx_desc(rt2x00dev, entry, txd, ieee80211hdr,
skb->len, control);
memcpy(&entry->tx_status.control, control, sizeof(*control));
entry->skb = skb;
rt2x00_ring_index_inc(ring);
if (rt2x00_ring_full(ring))
ieee80211_stop_queue(rt2x00dev->hw, control->queue);
return 0;
}
EXPORT_SYMBOL_GPL(rt2x00pci_write_tx_data);
/*
* Device initialization handlers.
*/
#define priv_offset(__ring, __i) \
({ \
ring->data_addr + (i * ring->desc_size); \
})
#define data_addr_offset(__ring, __i) \
({ \
(__ring)->data_addr \
+ ((__ring)->stats.limit * (__ring)->desc_size) \
+ ((__i) * (__ring)->data_size); \
})
#define data_dma_offset(__ring, __i) \
({ \
(__ring)->data_dma \
+ ((__ring)->stats.limit * (__ring)->desc_size) \
+ ((__i) * (__ring)->data_size); \
})
static int rt2x00pci_alloc_ring(struct rt2x00_dev *rt2x00dev,
struct data_ring *ring)
{
unsigned int i;
/*
* Allocate DMA memory for descriptor and buffer.
*/
ring->data_addr = pci_alloc_consistent(rt2x00dev_pci(rt2x00dev),
rt2x00_get_ring_size(ring), &ring->data_dma);
if (!ring->data_addr)
return -ENOMEM;
/*
* Initialize all ring entries to contain valid
* addresses.
*/
for (i = 0; i < ring->stats.limit; i++) {
ring->entry[i].priv = priv_offset(ring, i);
ring->entry[i].data_addr = data_addr_offset(ring, i);
ring->entry[i].data_dma = data_dma_offset(ring, i);
}
return 0;
}
int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
{
struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
struct data_ring *ring;
int status;
/*
* Allocate DMA
*/
ring_for_each(rt2x00dev, ring) {
status = rt2x00pci_alloc_ring(rt2x00dev, ring);
if (status)
goto exit;
}
/*
* Register interrupt handler.
*/
status = request_irq(pci_dev->irq, rt2x00dev->ops->lib->irq_handler,
IRQF_SHARED, pci_dev->driver->name, rt2x00dev);
if (status) {
ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
pci_dev->irq, status);
return status;
}
return 0;
exit:
rt2x00pci_uninitialize(rt2x00dev);
return status;
}
EXPORT_SYMBOL_GPL(rt2x00pci_initialize);
void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev)
{
struct data_ring *ring;
/*
* Free irq line.
*/
free_irq(rt2x00dev_pci(rt2x00dev)->irq, rt2x00dev);
/*
* Free DMA
*/
ring_for_each(rt2x00dev, ring) {
if (ring->data_addr)
pci_free_consistent(rt2x00dev_pci(rt2x00dev),
rt2x00_get_ring_size(ring),
ring->data_addr, ring->data_dma);
ring->data_addr = NULL;
}
}
EXPORT_SYMBOL_GPL(rt2x00pci_uninitialize);
/*
* PCI driver handlers.
*/
static int rt2x00pci_alloc_csr(struct rt2x00_dev *rt2x00dev)
{
rt2x00dev->csr_addr = ioremap(
pci_resource_start(rt2x00dev_pci(rt2x00dev), 0),
pci_resource_len(rt2x00dev_pci(rt2x00dev), 0));
if (!rt2x00dev->csr_addr) {
ERROR(rt2x00dev, "Ioremap failed.\n");
return -ENOMEM;
}
return 0;
}
static void rt2x00pci_free_csr(struct rt2x00_dev *rt2x00dev)
{
if (rt2x00dev->csr_addr) {
iounmap(rt2x00dev->csr_addr);
rt2x00dev->csr_addr = NULL;
}
}
int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
{
struct rt2x00_ops *ops = (struct rt2x00_ops*)id->driver_data;
struct ieee80211_hw *hw;
struct rt2x00_dev *rt2x00dev;
int retval;
retval = pci_request_regions(pci_dev, pci_name(pci_dev));
if (retval) {
ERROR_PROBE("PCI request regions failed.\n");
return retval;
}
retval = pci_enable_device(pci_dev);
if (retval) {
ERROR_PROBE("Enable device failed.\n");
goto exit_release_regions;
}
pci_set_master(pci_dev);
if (pci_set_mwi(pci_dev))
ERROR_PROBE("MWI not available.\n");
if (pci_set_dma_mask(pci_dev, DMA_64BIT_MASK) &&
pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
ERROR_PROBE("PCI DMA not supported.\n");
retval = -EIO;
goto exit_disable_device;
}
hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
if (!hw) {
ERROR_PROBE("Failed to allocate hardware.\n");
retval = -ENOMEM;
goto exit_disable_device;
}
pci_set_drvdata(pci_dev, hw);
rt2x00dev = hw->priv;
rt2x00dev->dev = pci_dev;
rt2x00dev->device = &pci_dev->dev;
rt2x00dev->ops = ops;
rt2x00dev->hw = hw;
retval = rt2x00pci_alloc_csr(rt2x00dev);
if (retval)
goto exit_free_device;
retval = rt2x00lib_probe_dev(rt2x00dev);
if (retval)
goto exit_free_csr;
return 0;
exit_free_csr:
rt2x00pci_free_csr(rt2x00dev);
exit_free_device:
ieee80211_free_hw(hw);
exit_disable_device:
if (retval != -EBUSY)
pci_disable_device(pci_dev);
exit_release_regions:
pci_release_regions(pci_dev);
pci_set_drvdata(pci_dev, NULL);
return retval;
}
EXPORT_SYMBOL_GPL(rt2x00pci_probe);
void rt2x00pci_remove(struct pci_dev *pci_dev)
{
struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
struct rt2x00_dev *rt2x00dev = hw->priv;
/*
* Free all allocated data.
*/
rt2x00lib_remove_dev(rt2x00dev);
ieee80211_free_hw(hw);
/*
* Free the PCI device data.
*/
pci_set_drvdata(pci_dev, NULL);
pci_disable_device(pci_dev);
pci_release_regions(pci_dev);
}
EXPORT_SYMBOL_GPL(rt2x00pci_remove);
#ifdef CONFIG_PM
int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state)
{
struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
struct rt2x00_dev *rt2x00dev = hw->priv;
int retval;
retval = rt2x00lib_suspend(rt2x00dev, state);
if (retval)
return retval;
rt2x00pci_free_csr(rt2x00dev);
pci_save_state(pci_dev);
pci_disable_device(pci_dev);
return pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
}
EXPORT_SYMBOL_GPL(rt2x00pci_suspend);
int rt2x00pci_resume(struct pci_dev *pci_dev)
{
struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
struct rt2x00_dev *rt2x00dev = hw->priv;
int retval;
if (pci_set_power_state(pci_dev, PCI_D0) ||
pci_enable_device(pci_dev) ||
pci_restore_state(pci_dev)) {
ERROR(rt2x00dev, "Failed to resume device.\n");
return -EIO;
}
retval = rt2x00pci_alloc_csr(rt2x00dev);
if (retval)
return retval;
return rt2x00lib_resume(rt2x00dev);
}
EXPORT_SYMBOL_GPL(rt2x00pci_resume);
#endif /* CONFIG_PM */
/*
* rt2x00pci module information.
*/
MODULE_AUTHOR(DRV_PROJECT);
MODULE_VERSION(DRV_VERSION);
MODULE_DESCRIPTION("rt2x00 library");
MODULE_LICENSE("GPL");

112
package/rt2x00/src/rt2x00pci.h Normal file
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@ -0,0 +1,112 @@
/*
Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2x00pci
Abstract: Data structures for the rt2x00pci module.
Supported chipsets: rt2460, rt2560, rt2561, rt2561s & rt2661.
*/
#ifndef RT2X00PCI_H
#define RT2X00PCI_H
/*
* This variable should be used with the
* pci_driver structure initialization.
*/
#define PCI_DEVICE_DATA(__ops) .driver_data = (kernel_ulong_t)(__ops)
/*
* Register defines.
* When register access attempts should be repeated
* only REGISTER_BUSY_COUNT attempts with a delay
* of REGISTER_BUSY_DELAY us should be taken.
*/
#define REGISTER_BUSY_COUNT 5
#define REGISTER_BUSY_DELAY 100
/*
* TX descriptor available flag.
* This flag is the combination of the TXD_W0_OWNER_NIC
* and TXD_W0_VALID flag which have the same value on all
* PCI drivers.
*/
#define TXD_ENTRY_AVAILABLE FIELD32(0x00000003)
/*
* Register access.
*/
static inline void rt2x00pci_register_read(const struct rt2x00_dev *rt2x00dev,
const unsigned long offset, u32 *value)
{
*value = readl(rt2x00dev->csr_addr + offset);
}
static inline void rt2x00pci_register_multiread(
const struct rt2x00_dev *rt2x00dev,
const unsigned long offset, void *value, const u16 length)
{
memcpy_fromio(value, rt2x00dev->csr_addr + offset, length);
}
static inline void rt2x00pci_register_write(const struct rt2x00_dev *rt2x00dev,
const unsigned long offset, u32 value)
{
writel(value, rt2x00dev->csr_addr + offset);
}
static inline void rt2x00pci_register_multiwrite(
const struct rt2x00_dev *rt2x00dev,
const unsigned long offset, void *value, const u16 length)
{
memcpy_toio(rt2x00dev->csr_addr + offset, value, length);
}
/*
* Beacon handlers.
*/
int rt2x00pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
struct ieee80211_tx_control *control);
void rt2x00pci_beacondone(struct rt2x00_dev *rt2x00dev, const int queue);
/*
* TX data handlers.
*/
int rt2x00pci_write_tx_data(struct rt2x00_dev *rt2x00dev,
struct data_ring *ring, struct sk_buff *skb,
struct ieee80211_tx_control *control);
/*
* Device initialization handlers.
*/
int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev);
void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev);
/*
* PCI driver handlers.
*/
int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id);
void rt2x00pci_remove(struct pci_dev *pci_dev);
#ifdef CONFIG_PM
int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state);
int rt2x00pci_resume(struct pci_dev *pci_dev);
#endif /* CONFIG_PM */
#endif /* RT2X00PCI_H */

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/*
Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2x00lib
Abstract: rt2x00 rfkill specific routines.
Supported chipsets: RT2460, RT2560, rt2561, rt2561s, rt2661.
*/
/*
* Set enviroment defines for rt2x00.h
*/
#define DRV_NAME "rt2x00lib"
#include <linux/rfkill.h>
#include "rt2x00.h"
static int rt2x00lib_toggle_radio(void *data, enum rfkill_state state)
{
struct rt2x00_dev* rt2x00dev = data;
int retval = 0;
if (unlikely(!rt2x00dev))
return 0;
/*
* Only continue if we have an active interface,
* either monitor or non-monitor should be present.
*/
if (!is_interface_present(&rt2x00dev->interface) &&
!is_monitor_present(&rt2x00dev->interface))
return 0;
if (state == RFKILL_STATE_ON) {
INFO(rt2x00dev, "Hardware button pressed, enabling radio.\n");
__set_bit(DEVICE_ENABLED_RADIO_HW, &rt2x00dev->flags);
retval = rt2x00lib_enable_radio(rt2x00dev);
} else if (state == RFKILL_STATE_OFF) {
INFO(rt2x00dev, "Hardware button pressed, disabling radio.\n");
__clear_bit(DEVICE_ENABLED_RADIO_HW, &rt2x00dev->flags);
rt2x00lib_disable_radio(rt2x00dev);
}
return retval;
}
static void rt2x00lib_rfkill_poll(struct work_struct *work)
{
struct rt2x00_dev *rt2x00dev =
container_of(work, struct rt2x00_dev, rfkill_work.work);
rfkill_switch_all(rt2x00dev->rfkill->type,
rt2x00dev->ops->lib->rfkill_poll(rt2x00dev));
queue_delayed_work(rt2x00dev->workqueue, &rt2x00dev->rfkill_work,
RFKILL_POLL_INTERVAL);
}
int rt2x00lib_register_rfkill(struct rt2x00_dev *rt2x00dev)
{
int status = rfkill_register(rt2x00dev->rfkill);
if (status) {
ERROR(rt2x00dev, "Failed to register rfkill handler.\n");
return status;
}
rt2x00lib_rfkill_poll(&rt2x00dev->rfkill_work.work);
return !schedule_delayed_work(&rt2x00dev->rfkill_work,
RFKILL_POLL_INTERVAL);
}
void rt2x00lib_unregister_rfkill(struct rt2x00_dev *rt2x00dev)
{
if (delayed_work_pending(&rt2x00dev->rfkill_work))
cancel_rearming_delayed_workqueue(
rt2x00dev->workqueue, &rt2x00dev->rfkill_work);
rfkill_unregister(rt2x00dev->rfkill);
}
int rt2x00lib_allocate_rfkill(struct rt2x00_dev *rt2x00dev)
{
struct rfkill *rfkill;
if (!test_bit(DEVICE_SUPPORT_HW_BUTTON, &rt2x00dev->flags))
return 0;
rfkill = rfkill_allocate(rt2x00dev->device, RFKILL_TYPE_WLAN);
if (!rfkill) {
ERROR(rt2x00dev, "Failed to allocate rfkill handler.\n");
return -ENOMEM;
}
rfkill->name = rt2x00dev->ops->name;
rfkill->data = rt2x00dev;
rfkill->toggle_radio = rt2x00lib_toggle_radio;
rt2x00dev->rfkill = rfkill;
INIT_DELAYED_WORK(&rt2x00dev->rfkill_work, rt2x00lib_rfkill_poll);
return 0;
}
void rt2x00lib_free_rfkill(struct rt2x00_dev *rt2x00dev)
{
if (!test_bit(DEVICE_SUPPORT_HW_BUTTON, &rt2x00dev->flags))
return;
rfkill_free(rt2x00dev->rfkill);
}

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/*
Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2x00lib
Abstract: Data structures for the rfkill.
Supported chipsets: RT2460, RT2560, rt2561, rt2561s, rt2661.
*/
#ifndef RT2X00RFKILL_H
#define RT2X00RFKILL_H
#ifdef CONFIG_RT2X00_LIB_RFKILL
int rt2x00lib_register_rfkill(struct rt2x00_dev *rt2x00dev);
void rt2x00lib_unregister_rfkill(struct rt2x00_dev *rt2x00dev);
int rt2x00lib_allocate_rfkill(struct rt2x00_dev *rt2x00dev);
void rt2x00lib_free_rfkill(struct rt2x00_dev *rt2x00dev);
#else /* CONFIG_RT2X00_LIB_RFKILL */
static inline int rt2x00lib_register_rfkill(struct rt2x00_dev *rt2x00dev)
{
return 0;
}
static inline void rt2x00lib_unregister_rfkill(struct rt2x00_dev *rt2x00dev){}
static inline int rt2x00lib_allocate_rfkill(struct rt2x00_dev *rt2x00dev)
{
return 0;
}
static inline void rt2x00lib_free_rfkill(struct rt2x00_dev *rt2x00dev){}
#endif /* CONFIG_RT2X00_LIB_RFKILL */
#endif /* RT2X00RFKILL_H */

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/*
Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2x00usb
Abstract: rt2x00 generic usb device routines.
Supported chipsets: rt2570, rt2571W & rt2671.
*/
/*
* Set enviroment defines for rt2x00.h
*/
#define DRV_NAME "rt2x00usb"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/version.h>
#include <linux/init.h>
#include <linux/usb.h>
#include "rt2x00.h"
#include "rt2x00usb.h"
/*
* Interfacing with the HW.
*/
int rt2x00usb_vendor_request(const struct rt2x00_dev *rt2x00dev,
const u8 request, const u8 type, const u16 offset,
u32 value, void *buffer, const u16 buffer_length, const u16 timeout)
{
struct usb_device *usb_dev = interface_to_usbdev(
rt2x00dev_usb(rt2x00dev));
int status;
unsigned int i;
for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
status = usb_control_msg(
usb_dev,
(type == USB_VENDOR_REQUEST_IN) ?
usb_rcvctrlpipe(usb_dev, 0) :
usb_sndctrlpipe(usb_dev, 0),
request, type, value, offset, buffer, buffer_length,
timeout);
if (status >= 0)
return 0;
}
ERROR(rt2x00dev, "vendor request error. Request 0x%02x failed "
"for offset 0x%04x with error %d.\n", request, offset, status);
return status;
}
EXPORT_SYMBOL_GPL(rt2x00usb_vendor_request);
/*
* Radio handlers
*/
void rt2x00usb_enable_radio(struct rt2x00_dev *rt2x00dev)
{
unsigned int i;
/*
* Start the RX ring.
*/
for (i = 0; i < rt2x00dev->rx->stats.limit; i++) {
__set_bit(ENTRY_OWNER_NIC, &rt2x00dev->rx->entry[i].flags);
usb_submit_urb(rt2x00dev->rx->entry[i].priv, GFP_ATOMIC);
}
}
EXPORT_SYMBOL_GPL(rt2x00usb_enable_radio);
void rt2x00usb_disable_radio(struct rt2x00_dev *rt2x00dev)
{
struct data_ring *ring;
unsigned int i;
rt2x00usb_vendor_request(rt2x00dev, USB_RX_CONTROL,
USB_VENDOR_REQUEST_OUT, 0x00, 0x00, NULL, 0, REGISTER_TIMEOUT);
/*
* Cancel all rings.
*/
ring_for_each(rt2x00dev, ring) {
for (i = 0; i < ring->stats.limit; i++)
usb_kill_urb(ring->entry[i].priv);
}
}
EXPORT_SYMBOL_GPL(rt2x00usb_disable_radio);
/*
* Beacon handlers.
*/
int rt2x00usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
struct ieee80211_tx_control *control)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
struct usb_device *usb_dev =
interface_to_usbdev(rt2x00dev_usb(rt2x00dev));
struct data_ring *ring =
rt2x00_get_ring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
struct data_entry *beacon;
struct data_entry *guardian;
int length;
/*
* Just in case the ieee80211 doesn't set this,
* but we need this queue set for the descriptor
* initialization.
*/
control->queue = IEEE80211_TX_QUEUE_BEACON;
/*
* Obtain 2 entries, one for the guardian byte,
* the second for the actual beacon.
*/
guardian = rt2x00_get_data_entry(ring);
rt2x00_ring_index_inc(ring);
beacon = rt2x00_get_data_entry(ring);
/*
* First we create the beacon.
*/
skb_push(skb, ring->desc_size);
rt2x00lib_write_tx_desc(rt2x00dev, beacon,
(struct data_desc*)skb->data,
(struct ieee80211_hdr*)(skb->data + ring->desc_size),
skb->len - ring->desc_size,
control);
/*
* Length passed to usb_fill_urb cannot be an odd number,
* so add 1 byte to make it even.
*/
length = skb->len;
if (length % 2)
length++;
usb_fill_bulk_urb(
beacon->priv,
usb_dev,
usb_sndbulkpipe(usb_dev, 1),
skb->data,
length,
rt2x00usb_beacondone,
beacon);
beacon->skb = skb;
/*
* Second we need to create the guardian byte.
* We only need a single byte, so lets recycle
* the 'flags' field we are not using for beacons.
*/
guardian->flags = 0;
usb_fill_bulk_urb(
guardian->priv,
usb_dev,
usb_sndbulkpipe(usb_dev, 1),
&guardian->flags,
1,
rt2x00usb_beacondone,
guardian);
/*
* Send out the guardian byte.
*/
usb_submit_urb(guardian->priv, GFP_ATOMIC);
/*
* Enable beacon generation.
*/
rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
return 0;
}
EXPORT_SYMBOL_GPL(rt2x00usb_beacon_update);
void rt2x00usb_beacondone(struct urb *urb)
{
struct data_entry *entry = (struct data_entry*)urb->context;
struct data_ring *ring = entry->ring;
if (!test_bit(DEVICE_ENABLED_RADIO, &ring->rt2x00dev->flags))
return;
/*
* Check if this was the guardian beacon,
* if that was the case we need to send the real beacon now.
* Otherwise we should free the sk_buffer, the device
* should be doing the rest of the work now.
*/
if (ring->index == 1) {
rt2x00_ring_index_done_inc(ring);
entry = rt2x00_get_data_entry(ring);
usb_submit_urb(entry->priv, GFP_ATOMIC);
rt2x00_ring_index_inc(ring);
} else if (ring->index_done == 1) {
entry = rt2x00_get_data_entry_done(ring);
if (entry->skb) {
dev_kfree_skb(entry->skb);
entry->skb = NULL;
}
rt2x00_ring_index_done_inc(ring);
}
}
EXPORT_SYMBOL_GPL(rt2x00usb_beacondone);
/*
* TX data handlers.
*/
static void rt2x00usb_interrupt_txdone(struct urb *urb)
{
struct data_entry *entry = (struct data_entry*)urb->context;
struct data_ring *ring = entry->ring;
struct rt2x00_dev *rt2x00dev = ring->rt2x00dev;
struct data_desc *txd = (struct data_desc *)entry->skb->data;
u32 word;
int tx_status;
if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags) ||
!__test_and_clear_bit(ENTRY_OWNER_NIC, &entry->flags))
return;
rt2x00_desc_read(txd, 0, &word);
/*
* Remove the descriptor data from the buffer.
*/
skb_pull(entry->skb, ring->desc_size);
/*
* Obtain the status about this packet.
*/
tx_status = !urb->status ? TX_SUCCESS : TX_FAIL_RETRY;
rt2x00lib_txdone(entry, tx_status, 0);
/*
* Make this entry available for reuse.
*/
entry->flags = 0;
rt2x00_ring_index_done_inc(entry->ring);
/*
* If the data ring was full before the txdone handler
* we must make sure the packet queue in the mac80211 stack
* is reenabled when the txdone handler has finished.
*/
if (!rt2x00_ring_full(ring))
ieee80211_wake_queue(rt2x00dev->hw,
entry->tx_status.control.queue);
}
int rt2x00usb_write_tx_data(struct rt2x00_dev *rt2x00dev,
struct data_ring *ring, struct sk_buff *skb,
struct ieee80211_tx_control *control)
{
struct usb_device *usb_dev =
interface_to_usbdev(rt2x00dev_usb(rt2x00dev));
struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr*)skb->data;
struct data_entry *entry = rt2x00_get_data_entry(ring);
struct data_desc *txd;
u32 length = skb->len;
if (rt2x00_ring_full(ring)) {
ieee80211_stop_queue(rt2x00dev->hw, control->queue);
return -EINVAL;
}
if (test_bit(ENTRY_OWNER_NIC, &entry->flags)) {
ERROR(rt2x00dev,
"Arrived at non-free entry in the non-full queue %d.\n"
"Please file bug report to %s.\n",
control->queue, DRV_PROJECT);
ieee80211_stop_queue( rt2x00dev->hw, control->queue);
return -EINVAL;
}
skb_push(skb, rt2x00dev->hw->extra_tx_headroom);
txd = (struct data_desc*)skb->data;
rt2x00lib_write_tx_desc(rt2x00dev, entry, txd, ieee80211hdr,
length, control);
memcpy(&entry->tx_status.control, control, sizeof(*control));
entry->skb = skb;
/*
* Length passed to usb_fill_urb cannot be an odd number,
* so add 1 byte to make it even.
*/
length += rt2x00dev->hw->extra_tx_headroom;
if (length % 2)
length++;
__set_bit(ENTRY_OWNER_NIC, &entry->flags);
usb_fill_bulk_urb(
entry->priv,
usb_dev,
usb_sndbulkpipe(usb_dev, 1),
skb->data,
length,
rt2x00usb_interrupt_txdone,
entry);
usb_submit_urb(entry->priv, GFP_ATOMIC);
rt2x00_ring_index_inc(ring);
if (rt2x00_ring_full(ring))
ieee80211_stop_queue(rt2x00dev->hw, control->queue);
return 0;
}
EXPORT_SYMBOL_GPL(rt2x00usb_write_tx_data);
/*
* Device initialization handlers.
*/
static int rt2x00usb_alloc_ring(struct rt2x00_dev *rt2x00dev,
struct data_ring *ring)
{
unsigned int i;
/*
* Allocate the URB's
*/
for (i = 0; i < ring->stats.limit; i++) {
ring->entry[i].priv = usb_alloc_urb(0, GFP_KERNEL);
if (!ring->entry[i].priv)
return -ENOMEM;
}
return 0;
}
int rt2x00usb_initialize(struct rt2x00_dev *rt2x00dev)
{
struct data_ring *ring;
struct sk_buff *skb;
unsigned int entry_size;
unsigned int i;
int status;
/*
* Allocate DMA
*/
ring_for_each(rt2x00dev, ring) {
status = rt2x00usb_alloc_ring(rt2x00dev, ring);
if (status)
goto exit;
}
/*
* For the RX ring, skb's should be allocated.
*/
entry_size = ring->data_size + ring->desc_size;
for (i = 0; i < rt2x00dev->rx->stats.limit; i++) {
skb = dev_alloc_skb(NET_IP_ALIGN + entry_size);
if (!skb)
goto exit;
skb_reserve(skb, NET_IP_ALIGN);
skb_put(skb, entry_size);
rt2x00dev->rx->entry[i].skb = skb;
}
return 0;
exit:
rt2x00usb_uninitialize(rt2x00dev);
return status;
}
EXPORT_SYMBOL_GPL(rt2x00usb_initialize);
void rt2x00usb_uninitialize(struct rt2x00_dev *rt2x00dev)
{
struct data_ring *ring;
unsigned int i;
ring_for_each(rt2x00dev, ring) {
if (!ring->entry)
continue;
for (i = 0; i < ring->stats.limit; i++) {
usb_kill_urb(ring->entry[i].priv);
usb_free_urb(ring->entry[i].priv);
if (ring->entry[i].skb)
kfree_skb(ring->entry[i].skb);
}
}
}
EXPORT_SYMBOL_GPL(rt2x00usb_uninitialize);
/*
* USB driver handlers.
*/
int rt2x00usb_probe(struct usb_interface *usb_intf,
const struct usb_device_id *id)
{
struct usb_device *usb_dev = interface_to_usbdev(usb_intf);
struct rt2x00_ops *ops = (struct rt2x00_ops*)id->driver_info;
struct ieee80211_hw *hw;
struct rt2x00_dev *rt2x00dev;
int retval;
usb_dev = usb_get_dev(usb_dev);
hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
if (!hw) {
ERROR_PROBE("Failed to allocate hardware.\n");
retval = -ENOMEM;
goto exit_put_device;
}
usb_set_intfdata(usb_intf, hw);
rt2x00dev = hw->priv;
rt2x00dev->dev = usb_intf;
rt2x00dev->device = &usb_intf->dev;
rt2x00dev->ops = ops;
rt2x00dev->hw = hw;
retval = rt2x00lib_probe_dev(rt2x00dev);
if (retval)
goto exit_free_device;
return 0;
exit_free_device:
ieee80211_free_hw(hw);
exit_put_device:
usb_put_dev(usb_dev);
usb_set_intfdata(usb_intf, NULL);
return retval;
}
EXPORT_SYMBOL_GPL(rt2x00usb_probe);
void rt2x00usb_disconnect(struct usb_interface *usb_intf)
{
struct ieee80211_hw *hw = usb_get_intfdata(usb_intf);
struct rt2x00_dev *rt2x00dev = hw->priv;
/*
* Free all allocated data.
*/
rt2x00lib_remove_dev(rt2x00dev);
ieee80211_free_hw(hw);
/*
* Free the USB device data.
*/
usb_set_intfdata(usb_intf, NULL);
usb_put_dev(interface_to_usbdev(usb_intf));
}
EXPORT_SYMBOL_GPL(rt2x00usb_disconnect);
#ifdef CONFIG_PM
int rt2x00usb_suspend(struct usb_interface *usb_intf, pm_message_t state)
{
struct ieee80211_hw *hw = usb_get_intfdata(usb_intf);
struct rt2x00_dev *rt2x00dev = hw->priv;
int retval;
retval = rt2x00lib_suspend(rt2x00dev, state);
if (retval)
return retval;
/*
* Decrease usbdev refcount.
*/
usb_put_dev(interface_to_usbdev(usb_intf));
return 0;
}
EXPORT_SYMBOL_GPL(rt2x00usb_suspend);
int rt2x00usb_resume(struct usb_interface *usb_intf)
{
struct ieee80211_hw *hw = usb_get_intfdata(usb_intf);
struct rt2x00_dev *rt2x00dev = hw->priv;
usb_get_dev(interface_to_usbdev(usb_intf));
return rt2x00lib_resume(rt2x00dev);
}
EXPORT_SYMBOL_GPL(rt2x00usb_resume);
#endif /* CONFIG_PM */
/*
* rt2x00pci module information.
*/
MODULE_AUTHOR(DRV_PROJECT);
MODULE_VERSION(DRV_VERSION);
MODULE_DESCRIPTION("rt2x00 library");
MODULE_LICENSE("GPL");

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/*
Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt2x00usb
Abstract: Data structures for the rt2x00usb module.
Supported chipsets: rt2570, rt2571W & rt2671.
*/
#ifndef RT2X00USB_H
#define RT2X00USB_H
/*
* This variable should be used with the
* usb_driver structure initialization.
*/
#define USB_DEVICE_DATA(__ops) .driver_info = (kernel_ulong_t)(__ops)
/*
* Register defines.
* When register access attempts should be repeated
* only REGISTER_BUSY_COUNT attempts with a delay
* of REGISTER_BUSY_DELAY us should be taken.
* For USB vendor requests we need to pass a timeout
* time in ms, for this we use the REGISTER_TIMEOUT,
* however when loading firmware a higher value is
* required. For that we use the REGISTER_TIMEOUT_FIRMWARE.
*/
#define REGISTER_BUSY_COUNT 5
#define REGISTER_BUSY_DELAY 100
#define REGISTER_TIMEOUT 20
#define REGISTER_TIMEOUT_FIRMWARE 1000
/*
* USB request types.
*/
#define USB_VENDOR_REQUEST ( USB_TYPE_VENDOR | USB_RECIP_DEVICE )
#define USB_VENDOR_REQUEST_IN ( USB_DIR_IN | USB_VENDOR_REQUEST )
#define USB_VENDOR_REQUEST_OUT ( USB_DIR_OUT | USB_VENDOR_REQUEST )
/*
* USB vendor commands.
*/
#define USB_DEVICE_MODE 0x01
#define USB_SINGLE_WRITE 0x02
#define USB_SINGLE_READ 0x03
#define USB_MULTI_WRITE 0x06
#define USB_MULTI_READ 0x07
#define USB_EEPROM_WRITE 0x08
#define USB_EEPROM_READ 0x09
#define USB_LED_CONTROL 0x0a /* RT73USB */
#define USB_RX_CONTROL 0x0c
/*
* Device modes offset
*/
#define USB_MODE_RESET 0x01
#define USB_MODE_UNPLUG 0x02
#define USB_MODE_FUNCTION 0x03
#define USB_MODE_TEST 0x04
#define USB_MODE_SLEEP 0x07 /* RT73USB */
#define USB_MODE_FIRMWARE 0x08 /* RT73USB */
#define USB_MODE_WAKEUP 0x09 /* RT73USB */
/*
* USB devices need an additional Beacon (guardian beacon) to be generated.
*/
#undef BEACON_ENTRIES
#define BEACON_ENTRIES 2
/*
* Interfacing with the HW.
*/
int rt2x00usb_vendor_request(const struct rt2x00_dev *rt2x00dev,
const u8 request, const u8 type, const u16 offset,
u32 value, void *buffer, const u16 buffer_length, const u16 timeout);
/*
* Radio handlers
*/
void rt2x00usb_enable_radio(struct rt2x00_dev *rt2x00dev);
void rt2x00usb_disable_radio(struct rt2x00_dev *rt2x00dev);
/*
* Beacon handlers.
*/
int rt2x00usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
struct ieee80211_tx_control *control);
void rt2x00usb_beacondone(struct urb *urb);
/*
* TX data handlers.
*/
int rt2x00usb_write_tx_data(struct rt2x00_dev *rt2x00dev,
struct data_ring *ring, struct sk_buff *skb,
struct ieee80211_tx_control *control);
/*
* Device initialization handlers.
*/
int rt2x00usb_initialize(struct rt2x00_dev *rt2x00dev);
void rt2x00usb_uninitialize(struct rt2x00_dev *rt2x00dev);
/*
* USB driver handlers.
*/
int rt2x00usb_probe(struct usb_interface *usb_intf,
const struct usb_device_id *id);
void rt2x00usb_disconnect(struct usb_interface *usb_intf);
#ifdef CONFIG_PM
int rt2x00usb_suspend(struct usb_interface *usb_intf, pm_message_t state);
int rt2x00usb_resume(struct usb_interface *usb_intf);
#endif /* CONFIG_PM */
#endif /* RT2X00USB_H */

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/*
Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
<http://rt2x00.serialmonkey.com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the
Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
Module: rt73usb
Abstract: Data structures and registers for the rt73usb module.
Supported chipsets: rt2571W & rt2671.
*/
#ifndef RT73USB_H
#define RT73USB_H
/*
* RF chip defines.
*/
#define RF5226 0x0001
#define RF2528 0x0002
#define RF5225 0x0003
#define RF2527 0x0004
/*
* Max RSSI value, required for RSSI <-> dBm conversion.
*/
#define MAX_RX_SSI 120
#define MAX_RX_NOISE -110
/*
* Register layout information.
*/
#define CSR_REG_BASE 0x3000
#define CSR_REG_SIZE 0x04b0
#define EEPROM_BASE 0x0000
#define EEPROM_SIZE 0x0100
#define BBP_SIZE 0x0080
/*
* USB registers.
*/
/*
* MCU_LEDCS: LED control for MCU Mailbox.
*/
#define MCU_LEDCS_LED_MODE FIELD16(0x001f)
#define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
#define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
#define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
#define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
#define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
#define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
#define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
#define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
#define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
#define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
#define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
/*
* 8051 firmware image.
*/
#define FIRMWARE_RT2571 "rt73.bin"
#define FIRMWARE_IMAGE_BASE 0x0800
/*
* Security key table memory.
* 16 entries 32-byte for shared key table
* 64 entries 32-byte for pairwise key table
* 64 entries 8-byte for pairwise ta key table
*/
#define SHARED_KEY_TABLE_BASE 0x1000
#define PAIRWISE_KEY_TABLE_BASE 0x1200
#define PAIRWISE_TA_TABLE_BASE 0x1a00
struct hw_key_entry {
u8 key[16];
u8 tx_mic[8];
u8 rx_mic[8];
} __attribute__ ((packed));
struct hw_pairwise_ta_entry {
u8 address[6];
u8 reserved[2];
} __attribute__ ((packed));
/*
* Since NULL frame won't be that long (256 byte),
* We steal 16 tail bytes to save debugging settings.
*/
#define HW_DEBUG_SETTING_BASE 0x2bf0
/*
* On-chip BEACON frame space.
*/
#define HW_BEACON_BASE0 0x2400
#define HW_BEACON_BASE1 0x2500
#define HW_BEACON_BASE2 0x2600
#define HW_BEACON_BASE3 0x2700
/*
* MAC Control/Status Registers(CSR).
* Some values are set in TU, whereas 1 TU == 1024 us.
*/
/*
* MAC_CSR0: ASIC revision number.
*/
#define MAC_CSR0 0x3000
/*
* MAC_CSR1: System control register.
* SOFT_RESET: Software reset bit, 1: reset, 0: normal.
* BBP_RESET: Hardware reset BBP.
* HOST_READY: Host is ready after initialization, 1: ready.
*/
#define MAC_CSR1 0x3004
#define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
#define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
#define MAC_CSR1_HOST_READY FIELD32(0x00000004)
/*
* MAC_CSR2: STA MAC register 0.
*/
#define MAC_CSR2 0x3008
#define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
#define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
#define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
#define MAC_CSR2_BYTE3 FIELD32(0xff000000)
/*
* MAC_CSR3: STA MAC register 1.
*/
#define MAC_CSR3 0x300c
#define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
#define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
#define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
/*
* MAC_CSR4: BSSID register 0.
*/
#define MAC_CSR4 0x3010
#define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
#define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
#define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
#define MAC_CSR4_BYTE3 FIELD32(0xff000000)
/*
* MAC_CSR5: BSSID register 1.
* BSS_ID_MASK: 3: one BSSID, 0: 4 BSSID, 2 or 1: 2 BSSID.
*/
#define MAC_CSR5 0x3014
#define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
#define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
#define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
/*
* MAC_CSR6: Maximum frame length register.
*/
#define MAC_CSR6 0x3018
#define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x000007ff)
/*
* MAC_CSR7: Reserved
*/
#define MAC_CSR7 0x301c
/*
* MAC_CSR8: SIFS/EIFS register.
* All units are in US.
*/
#define MAC_CSR8 0x3020
#define MAC_CSR8_SIFS FIELD32(0x000000ff)
#define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
#define MAC_CSR8_EIFS FIELD32(0xffff0000)
/*
* MAC_CSR9: Back-Off control register.
* SLOT_TIME: Slot time, default is 20us for 802.11BG.
* CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
* CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
* CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
*/
#define MAC_CSR9 0x3024
#define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
#define MAC_CSR9_CWMIN FIELD32(0x00000f00)
#define MAC_CSR9_CWMAX FIELD32(0x0000f000)
#define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
/*
* MAC_CSR10: Power state configuration.
*/
#define MAC_CSR10 0x3028
/*
* MAC_CSR11: Power saving transition time register.
* DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
* TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
* WAKEUP_LATENCY: In unit of TU.
*/
#define MAC_CSR11 0x302c
#define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
#define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
#define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
#define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
/*
* MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
* CURRENT_STATE: 0:sleep, 1:awake.
* FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
* BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
*/
#define MAC_CSR12 0x3030
#define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
#define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
#define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
#define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
/*
* MAC_CSR13: GPIO.
*/
#define MAC_CSR13 0x3034
/*
* MAC_CSR14: LED control register.
* ON_PERIOD: On period, default 70ms.
* OFF_PERIOD: Off period, default 30ms.
* HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
* SW_LED: s/w LED, 1: ON, 0: OFF.
* HW_LED_POLARITY: 0: active low, 1: active high.
*/
#define MAC_CSR14 0x3038
#define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
#define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
#define MAC_CSR14_HW_LED FIELD32(0x00010000)
#define MAC_CSR14_SW_LED FIELD32(0x00020000)
#define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
#define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
/*
* MAC_CSR15: NAV control.
*/
#define MAC_CSR15 0x303c
/*
* TXRX control registers.
* Some values are set in TU, whereas 1 TU == 1024 us.
*/
/*
* TXRX_CSR0: TX/RX configuration register.
* TSF_OFFSET: Default is 24.
* AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
* DISABLE_RX: Disable Rx engine.
* DROP_CRC: Drop CRC error.
* DROP_PHYSICAL: Drop physical error.
* DROP_CONTROL: Drop control frame.
* DROP_NOT_TO_ME: Drop not to me unicast frame.
* DROP_TO_DS: Drop fram ToDs bit is true.
* DROP_VERSION_ERROR: Drop version error frame.
* DROP_MULTICAST: Drop multicast frames.
* DROP_BORADCAST: Drop broadcast frames.
* ROP_ACK_CTS: Drop received ACK and CTS.
*/
#define TXRX_CSR0 0x3040
#define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
#define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
#define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
#define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
#define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
#define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
#define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
#define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
#define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
#define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
#define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
#define TXRX_CSR0_DROP_BORADCAST FIELD32(0x01000000)
#define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
#define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
/*
* TXRX_CSR1
*/
#define TXRX_CSR1 0x3044
/*
* TXRX_CSR2
*/
#define TXRX_CSR2 0x3048
/*
* TXRX_CSR3
*/
#define TXRX_CSR3 0x304c
/*
* TXRX_CSR4: Auto-Responder/Tx-retry register.
* AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
* OFDM_TX_RATE_DOWN: 1:enable.
* OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
* OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
*/
#define TXRX_CSR4 0x3050
#define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
#define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
#define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
#define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
#define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
#define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
#define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
#define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
#define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
#define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
/*
* TXRX_CSR5
*/
#define TXRX_CSR5 0x3054
/*
* ACK/CTS payload consumed time registers.
*/
#define TXRX_CSR6 0x3058
#define TXRX_CSR7 0x305c
#define TXRX_CSR8 0x3060
/*
* TXRX_CSR9: Synchronization control register.
* BEACON_INTERVAL: In unit of 1/16 TU.
* TSF_TICKING: Enable TSF auto counting.
* TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
* BEACON_GEN: Enable beacon generator.
*/
#define TXRX_CSR9 0x3064
#define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
#define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
#define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
#define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
#define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
#define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
/*
* TXRX_CSR10: BEACON alignment.
*/
#define TXRX_CSR10 0x3068
/*
* TXRX_CSR11: AES mask.
*/
#define TXRX_CSR11 0x306c
/*
* TXRX_CSR12: TSF low 32.
*/
#define TXRX_CSR12 0x3070
#define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
/*
* TXRX_CSR13: TSF high 32.
*/
#define TXRX_CSR13 0x3074
#define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
/*
* TXRX_CSR14: TBTT timer.
*/
#define TXRX_CSR14 0x3078
/*
* TXRX_CSR15: TKIP MIC priority byte "AND" mask.
*/
#define TXRX_CSR15 0x307c
/*
* PHY control registers.
* Some values are set in TU, whereas 1 TU == 1024 us.
*/
/*
* PHY_CSR0: RF/PS control.
*/
#define PHY_CSR0 0x3080
#define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
#define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
/*
* PHY_CSR1
*/
#define PHY_CSR1 0x3084
#define PHY_CSR1_RF_RPI FIELD32(0x00010000)
/*
* PHY_CSR2: Pre-TX BBP control.
*/
#define PHY_CSR2 0x3088
/*
* PHY_CSR3: BBP serial control register.
* VALUE: Register value to program into BBP.
* REG_NUM: Selected BBP register.
* READ_CONTROL: 0: Write BBP, 1: Read BBP.
* BUSY: 1: ASIC is busy execute BBP programming.
*/
#define PHY_CSR3 0x308c
#define PHY_CSR3_VALUE FIELD32(0x000000ff)
#define PHY_CSR3_REGNUM FIELD32(0x00007f00)
#define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
#define PHY_CSR3_BUSY FIELD32(0x00010000)
/*
* PHY_CSR4: RF serial control register
* VALUE: Register value (include register id) serial out to RF/IF chip.
* NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
* IF_SELECT: 1: select IF to program, 0: select RF to program.
* PLL_LD: RF PLL_LD status.
* BUSY: 1: ASIC is busy execute RF programming.
*/
#define PHY_CSR4 0x3090
#define PHY_CSR4_VALUE FIELD32(0x00ffffff)
#define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
#define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
#define PHY_CSR4_PLL_LD FIELD32(0x40000000)
#define PHY_CSR4_BUSY FIELD32(0x80000000)
/*
* PHY_CSR5: RX to TX signal switch timing control.
*/
#define PHY_CSR5 0x3094
/*
* PHY_CSR6: TX to RX signal timing control.
*/
#define PHY_CSR6 0x3098
/*
* PHY_CSR7: TX DAC switching timing control.
*/
#define PHY_CSR7 0x309c
/*
* Security control register.
*/
/*
* SEC_CSR0: Shared key table control.
*/
#define SEC_CSR0 0x30a0
/*
* SEC_CSR1: Shared key table security mode register.
*/
#define SEC_CSR1 0x30a4
#define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
#define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
#define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
#define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
#define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
#define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
#define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
#define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
/*
* Pairwise key table valid bitmap registers.
* SEC_CSR2: pairwise key table valid bitmap 0.
* SEC_CSR3: pairwise key table valid bitmap 1.
*/
#define SEC_CSR2 0x30a8
#define SEC_CSR3 0x30ac
/*
* SEC_CSR4: Pairwise key table lookup control.
*/
#define SEC_CSR4 0x30b0
/*
* SEC_CSR5: shared key table security mode register.
*/
#define SEC_CSR5 0x30b4
#define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
#define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
#define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
#define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
#define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
#define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
#define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
#define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
/*
* STA control registers.
*/
/*
* STA_CSR0: RX PLCP error count & RX FCS error count.
*/
#define STA_CSR0 0x30c0
#define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
#define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
/*
* STA_CSR1: RX False CCA count & RX LONG frame count.
*/
#define STA_CSR1 0x30c4
#define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
#define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
/*
* STA_CSR2: TX Beacon count and RX FIFO overflow count.
*/
#define STA_CSR2 0x30c8
#define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
#define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
/*
* STA_CSR3: TX Beacon count.
*/
#define STA_CSR3 0x30cc
#define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
/*
* STA_CSR4: TX Retry count.
*/
#define STA_CSR4 0x30d0
#define STA_CSR4_TX_NO_RETRY_COUNT FIELD32(0x0000ffff)
#define STA_CSR4_TX_ONE_RETRY_COUNT FIELD32(0xffff0000)
/*
* STA_CSR5: TX Retry count.
*/
#define STA_CSR5 0x30d4
#define STA_CSR4_TX_MULTI_RETRY_COUNT FIELD32(0x0000ffff)
#define STA_CSR4_TX_RETRY_FAIL_COUNT FIELD32(0xffff0000)
/*
* QOS control registers.
*/
/*
* QOS_CSR1: TXOP holder MAC address register.
*/
#define QOS_CSR1 0x30e4
#define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
#define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
/*
* QOS_CSR2: TXOP holder timeout register.
*/
#define QOS_CSR2 0x30e8
/*
* RX QOS-CFPOLL MAC address register.
* QOS_CSR3: RX QOS-CFPOLL MAC address 0.
* QOS_CSR4: RX QOS-CFPOLL MAC address 1.
*/
#define QOS_CSR3 0x30ec
#define QOS_CSR4 0x30f0
/*
* QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
*/
#define QOS_CSR5 0x30f4
/*
* WMM Scheduler Register
*/
/*
* AIFSN_CSR: AIFSN for each EDCA AC.
* AIFSN0: For AC_BK.
* AIFSN1: For AC_BE.
* AIFSN2: For AC_VI.
* AIFSN3: For AC_VO.
*/
#define AIFSN_CSR 0x0400
#define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
#define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
#define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
#define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
/*
* CWMIN_CSR: CWmin for each EDCA AC.
* CWMIN0: For AC_BK.
* CWMIN1: For AC_BE.
* CWMIN2: For AC_VI.
* CWMIN3: For AC_VO.
*/
#define CWMIN_CSR 0x0404
#define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
#define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
#define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
#define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
/*
* CWMAX_CSR: CWmax for each EDCA AC.
* CWMAX0: For AC_BK.
* CWMAX1: For AC_BE.
* CWMAX2: For AC_VI.
* CWMAX3: For AC_VO.
*/
#define CWMAX_CSR 0x0408
#define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
#define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
#define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
#define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
/*
* AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
* AC0_TX_OP: For AC_BK, in unit of 32us.
* AC1_TX_OP: For AC_BE, in unit of 32us.
*/
#define AC_TXOP_CSR0 0x040c
#define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
#define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
/*
* AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
* AC2_TX_OP: For AC_VI, in unit of 32us.
* AC3_TX_OP: For AC_VO, in unit of 32us.
*/
#define AC_TXOP_CSR1 0x0410
#define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
#define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
/*
* RF registers
*/
#define RF3_TXPOWER FIELD32(0x00003e00)
#define RF4_FREQ_OFFSET FIELD32(0x0003f000)
/*
* EEPROM content.
* The wordsize of the EEPROM is 16 bits.
*/
/*
* HW MAC address.
*/
#define EEPROM_MAC_ADDR_0 0x0002
#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
#define EEPROM_MAC_ADDR1 0x0003
#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
#define EEPROM_MAC_ADDR_2 0x0004
#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
/*
* EEPROM antenna.
* ANTENNA_NUM: Number of antenna's.
* TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
* RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
* FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
* DYN_TXAGC: Dynamic TX AGC control.
* HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
* RF_TYPE: Rf_type of this adapter.
*/
#define EEPROM_ANTENNA 0x0010
#define EEPROM_ANTENNA_NUM FIELD16(0x0003)
#define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
#define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
#define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
#define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
#define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
#define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
/*
* EEPROM NIC config.
* EXTERNAL_LNA: External LNA.
*/
#define EEPROM_NIC 0x0011
#define EEPROM_NIC_EXTERNAL_LNA FIELD16(0x0010)
/*
* EEPROM geography.
* GEO_A: Default geographical setting for 5GHz band
* GEO: Default geographical setting.
*/
#define EEPROM_GEOGRAPHY 0x0012
#define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
#define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
/*
* EEPROM BBP.
*/
#define EEPROM_BBP_START 0x0013
#define EEPROM_BBP_SIZE 16
#define EEPROM_BBP_VALUE FIELD16(0x00ff)
#define EEPROM_BBP_REG_ID FIELD16(0xff00)
/*
* EEPROM TXPOWER 802.11G
*/
#define EEPROM_TXPOWER_G_START 0x0023
#define EEPROM_TXPOWER_G_SIZE 7
#define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
#define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
/*
* EEPROM Frequency
*/
#define EEPROM_FREQ 0x002f
#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
#define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
#define EEPROM_FREQ_SEQ FIELD16(0x0300)
/*
* EEPROM LED.
* POLARITY_RDY_G: Polarity RDY_G setting.
* POLARITY_RDY_A: Polarity RDY_A setting.
* POLARITY_ACT: Polarity ACT setting.
* POLARITY_GPIO_0: Polarity GPIO0 setting.
* POLARITY_GPIO_1: Polarity GPIO1 setting.
* POLARITY_GPIO_2: Polarity GPIO2 setting.
* POLARITY_GPIO_3: Polarity GPIO3 setting.
* POLARITY_GPIO_4: Polarity GPIO4 setting.
* LED_MODE: Led mode.
*/
#define EEPROM_LED 0x0030
#define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
/*
* EEPROM TXPOWER 802.11A
*/
#define EEPROM_TXPOWER_A_START 0x0031
#define EEPROM_TXPOWER_A_SIZE 12
#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
/*
* BBP content.
* The wordsize of the BBP is 8 bits.
*/
/*
* BBP_R2
*/
#define BBP_R2_BG_MODE FIELD8(0x20)
/*
* BBP_R3
*/
#define BBP_R3_SMART_MODE FIELD8(0x01)
/*
* BBP_R4: RX antenna control
* FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
*/
#define BBP_R4_RX_ANTENNA FIELD8(0x03)
#define BBP_R4_RX_FRAME_END FIELD8(0x10)
#define BBP_R4_RX_BG_MODE FIELD8(0x20)
/*
* BBP_R77
*/
#define BBP_R77_PAIR FIELD8(0x03)
/*
* DMA descriptor defines.
*/
#define TXD_DESC_SIZE ( 6 * sizeof(struct data_desc) )
#define RXD_DESC_SIZE ( 6 * sizeof(struct data_desc) )
/*
* TX descriptor format for TX, PRIO and Beacon Ring.
*/
/*
* Word0
* BURST: Next frame belongs to same "burst" event.
* TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
* KEY_TABLE: Use per-client pairwise KEY table.
* KEY_INDEX:
* Key index (0~31) to the pairwise KEY table.
* 0~3 to shared KEY table 0 (BSS0).
* 4~7 to shared KEY table 1 (BSS1).
* 8~11 to shared KEY table 2 (BSS2).
* 12~15 to shared KEY table 3 (BSS3).
* BURST2: For backward compatibility, set to same value as BURST.
*/
#define TXD_W0_BURST FIELD32(0x00000001)
#define TXD_W0_VALID FIELD32(0x00000002)
#define TXD_W0_MORE_FRAG FIELD32(0x00000004)
#define TXD_W0_ACK FIELD32(0x00000008)
#define TXD_W0_TIMESTAMP FIELD32(0x00000010)
#define TXD_W0_OFDM FIELD32(0x00000020)
#define TXD_W0_IFS FIELD32(0x00000040)
#define TXD_W0_RETRY_MODE FIELD32(0x00000080)
#define TXD_W0_TKIP_MIC FIELD32(0x00000100)
#define TXD_W0_KEY_TABLE FIELD32(0x00000200)
#define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
#define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
#define TXD_W0_BURST2 FIELD32(0x10000000)
#define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
/*
* Word1
* HOST_Q_ID: EDCA/HCCA queue ID.
* HW_SEQUENCE: MAC overwrites the frame sequence number.
* BUFFER_COUNT: Number of buffers in this TXD.
*/
#define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
#define TXD_W1_AIFSN FIELD32(0x000000f0)
#define TXD_W1_CWMIN FIELD32(0x00000f00)
#define TXD_W1_CWMAX FIELD32(0x0000f000)
#define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
#define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
#define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
/*
* Word2: PLCP information
*/
#define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
#define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
#define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
#define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
/*
* Word3
*/
#define TXD_W3_IV FIELD32(0xffffffff)
/*
* Word4
*/
#define TXD_W4_EIV FIELD32(0xffffffff)
/*
* Word5
* FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
* PACKET_ID: Driver assigned packet ID to categorize TXResult in interrupt.
* WAITING_DMA_DONE_INT: TXD been filled with data
* and waiting for TxDoneISR housekeeping.
*/
#define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
#define TXD_W5_PACKET_ID FIELD32(0x0000ff00)
#define TXD_W5_TX_POWER FIELD32(0x00ff0000)
#define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
/*
* RX descriptor format for RX Ring.
*/
/*
* Word0
* CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
* KEY_INDEX: Decryption key actually used.
*/
#define RXD_W0_OWNER_NIC FIELD32(0x00000001)
#define RXD_W0_DROP FIELD32(0x00000002)
#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
#define RXD_W0_MULTICAST FIELD32(0x00000008)
#define RXD_W0_BROADCAST FIELD32(0x00000010)
#define RXD_W0_MY_BSS FIELD32(0x00000020)
#define RXD_W0_CRC FIELD32(0x00000040)
#define RXD_W0_OFDM FIELD32(0x00000080)
#define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
#define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
#define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
#define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
/*
* WORD1
* SIGNAL: RX raw data rate reported by BBP.
* RSSI: RSSI reported by BBP.
*/
#define RXD_W1_SIGNAL FIELD32(0x000000ff)
#define RXD_W1_RSSI FIELD32(0x0000ff00)
#define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
/*
* Word2
* IV: Received IV of originally encrypted.
*/
#define RXD_W2_IV FIELD32(0xffffffff)
/*
* Word3
* EIV: Received EIV of originally encrypted.
*/
#define RXD_W3_EIV FIELD32(0xffffffff)
/*
* Word4
*/
#define RXD_W4_RESERVED FIELD32(0xffffffff)
/*
* the above 20-byte is called RXINFO and will be DMAed to MAC RX block
* and passed to the HOST driver.
* The following fields are for DMA block and HOST usage only.
* Can't be touched by ASIC MAC block.
*/
/*
* Word5
*/
#define RXD_W5_RESERVED FIELD32(0xffffffff)
/*
* Macro's for converting txpower from EEPROM to dscape value
* and from dscape value to register value.
*/
#define MIN_TXPOWER 0
#define MAX_TXPOWER 31
#define DEFAULT_TXPOWER 24
#define TXPOWER_FROM_DEV(__txpower) \
({ \
((__txpower) > MAX_TXPOWER) ? \
DEFAULT_TXPOWER : (__txpower); \
})
#define TXPOWER_TO_DEV(__txpower) \
({ \
((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
(((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
(__txpower)); \
})
/*
* Interrupt functions.
*/
static void rt73usb_interrupt_rxdone(struct urb *urb);
#endif /* RT73USB_H */