ralink: fix ethernet feature TSO not work
* fix TSO features verify on mt7621 firewrt board * improve tx clean up. no need to access uncached memory. also use TX_DTX register instead of read tx ring DONE bit * mt7621 need napi weight 64 to get more performance * remove netif_receive_skb, after kernel version 3.7 tcp4_gro_receive can handle tcp checksum. on rt2880 use iperf tcp LAN to WAN throughput test. with gro 135 Mbits/sec. without gro 80.4Mbits/sec. Signed-off-by: michael lee <igvtee@gmail.com> SVN-Revision: 44118
This commit is contained in:
parent
3ec294a825
commit
bef829efa5
7 changed files with 196 additions and 154 deletions
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@ -208,5 +208,5 @@ void fe_set_ethtool_ops(struct net_device *netdev)
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fe_ethtool_ops.get_ethtool_stats = fe_get_ethtool_stats;
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fe_ethtool_ops.get_ethtool_stats = fe_get_ethtool_stats;
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}
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}
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SET_ETHTOOL_OPS(netdev, &fe_ethtool_ops);
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netdev->ethtool_ops = &fe_ethtool_ops;
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}
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}
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@ -190,14 +190,6 @@ static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
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rxd->rxd4 = dma_rxd->rxd4;
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rxd->rxd4 = dma_rxd->rxd4;
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}
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}
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static inline void fe_get_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
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{
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txd->txd1 = dma_txd->txd1;
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txd->txd2 = dma_txd->txd2;
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txd->txd3 = dma_txd->txd3;
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txd->txd4 = dma_txd->txd4;
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}
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static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
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static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
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{
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{
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dma_txd->txd1 = txd->txd1;
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dma_txd->txd1 = txd->txd1;
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@ -289,17 +281,41 @@ no_rx_mem:
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return -ENOMEM;
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return -ENOMEM;
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}
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}
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static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
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{
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if (tx_buf->flags & FE_TX_FLAGS_SINGLE0) {
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dma_unmap_single(dev,
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dma_unmap_addr(tx_buf, dma_addr0),
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dma_unmap_len(tx_buf, dma_len0),
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DMA_TO_DEVICE);
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} else if (tx_buf->flags & FE_TX_FLAGS_PAGE0) {
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dma_unmap_page(dev,
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dma_unmap_addr(tx_buf, dma_addr0),
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dma_unmap_len(tx_buf, dma_len0),
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DMA_TO_DEVICE);
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}
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if (tx_buf->flags & FE_TX_FLAGS_PAGE1)
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dma_unmap_page(dev,
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dma_unmap_addr(tx_buf, dma_addr1),
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dma_unmap_len(tx_buf, dma_len1),
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DMA_TO_DEVICE);
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tx_buf->flags = 0;
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if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *) DMA_DUMMY_DESC)) {
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dev_kfree_skb_any(tx_buf->skb);
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}
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tx_buf->skb = NULL;
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}
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static void fe_clean_tx(struct fe_priv *priv)
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static void fe_clean_tx(struct fe_priv *priv)
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{
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{
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int i;
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int i;
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if (priv->tx_skb) {
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if (priv->tx_buf) {
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for (i = 0; i < NUM_DMA_DESC; i++) {
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for (i = 0; i < NUM_DMA_DESC; i++)
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if (priv->tx_skb[i])
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fe_txd_unmap(&priv->netdev->dev, &priv->tx_buf[i]);
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dev_kfree_skb_any(priv->tx_skb[i]);
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kfree(priv->tx_buf);
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}
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priv->tx_buf = NULL;
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kfree(priv->tx_skb);
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priv->tx_skb = NULL;
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}
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}
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if (priv->tx_dma) {
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if (priv->tx_dma) {
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@ -317,9 +333,9 @@ static int fe_alloc_tx(struct fe_priv *priv)
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priv->tx_free_idx = 0;
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priv->tx_free_idx = 0;
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priv->tx_skb = kcalloc(NUM_DMA_DESC, sizeof(*priv->tx_skb),
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priv->tx_buf = kcalloc(NUM_DMA_DESC, sizeof(*priv->tx_buf),
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GFP_KERNEL);
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GFP_KERNEL);
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if (!priv->tx_skb)
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if (!priv->tx_buf)
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goto no_tx_mem;
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goto no_tx_mem;
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priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
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priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
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@ -332,7 +348,6 @@ static int fe_alloc_tx(struct fe_priv *priv)
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for (i = 0; i < NUM_DMA_DESC; i++) {
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for (i = 0; i < NUM_DMA_DESC; i++) {
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if (priv->soc->tx_dma) {
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if (priv->soc->tx_dma) {
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priv->soc->tx_dma(&priv->tx_dma[i]);
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priv->soc->tx_dma(&priv->tx_dma[i]);
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continue;
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}
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}
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priv->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
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priv->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
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}
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}
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@ -372,39 +387,19 @@ static void fe_free_dma(struct fe_priv *priv)
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netdev_reset_queue(priv->netdev);
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netdev_reset_queue(priv->netdev);
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}
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}
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static inline void txd_unmap_single(struct device *dev, struct fe_tx_dma *txd)
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{
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if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
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dma_unmap_single(dev, txd->txd1,
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TX_DMA_GET_PLEN0(txd->txd2),
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DMA_TO_DEVICE);
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}
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static inline void txd_unmap_page0(struct device *dev, struct fe_tx_dma *txd)
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{
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if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
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dma_unmap_page(dev, txd->txd1,
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TX_DMA_GET_PLEN0(txd->txd2),
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DMA_TO_DEVICE);
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}
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static inline void txd_unmap_page1(struct device *dev, struct fe_tx_dma *txd)
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{
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if (txd->txd3 && TX_DMA_GET_PLEN1(txd->txd2))
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dma_unmap_page(dev, txd->txd3,
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TX_DMA_GET_PLEN1(txd->txd2),
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DMA_TO_DEVICE);
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}
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void fe_stats_update(struct fe_priv *priv)
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void fe_stats_update(struct fe_priv *priv)
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{
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{
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struct fe_hw_stats *hwstats = priv->hw_stats;
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struct fe_hw_stats *hwstats = priv->hw_stats;
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unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
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unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
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u64 stats;
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u64_stats_update_begin(&hwstats->syncp);
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u64_stats_update_begin(&hwstats->syncp);
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if (IS_ENABLED(CONFIG_SOC_MT7621)) {
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if (IS_ENABLED(CONFIG_SOC_MT7621)) {
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hwstats->rx_bytes += fe_r32(base);
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hwstats->rx_bytes += fe_r32(base);
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stats = fe_r32(base + 0x04);
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if (stats)
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hwstats->rx_bytes += (stats << 32);
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hwstats->rx_packets += fe_r32(base + 0x08);
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hwstats->rx_packets += fe_r32(base + 0x08);
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hwstats->rx_overflow += fe_r32(base + 0x10);
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hwstats->rx_overflow += fe_r32(base + 0x10);
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hwstats->rx_fcs_errors += fe_r32(base + 0x14);
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hwstats->rx_fcs_errors += fe_r32(base + 0x14);
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@ -415,6 +410,9 @@ void fe_stats_update(struct fe_priv *priv)
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hwstats->tx_skip += fe_r32(base + 0x28);
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hwstats->tx_skip += fe_r32(base + 0x28);
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hwstats->tx_collisions += fe_r32(base + 0x2c);
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hwstats->tx_collisions += fe_r32(base + 0x2c);
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hwstats->tx_bytes += fe_r32(base + 0x30);
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hwstats->tx_bytes += fe_r32(base + 0x30);
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stats = fe_r32(base + 0x34);
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if (stats)
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hwstats->tx_bytes += (stats << 32);
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hwstats->tx_packets += fe_r32(base + 0x38);
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hwstats->tx_packets += fe_r32(base + 0x38);
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} else {
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} else {
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hwstats->tx_bytes += fe_r32(base);
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hwstats->tx_bytes += fe_r32(base);
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@ -525,19 +523,21 @@ static int fe_vlan_rx_kill_vid(struct net_device *dev,
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}
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}
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static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
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static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
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int idx)
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int idx, int tx_num)
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{
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{
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struct fe_priv *priv = netdev_priv(dev);
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struct fe_priv *priv = netdev_priv(dev);
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struct skb_frag_struct *frag;
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struct skb_frag_struct *frag;
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struct fe_tx_dma txd, *ptxd;
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struct fe_tx_dma txd, *ptxd;
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struct fe_tx_buf *tx_buf;
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dma_addr_t mapped_addr;
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dma_addr_t mapped_addr;
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unsigned int nr_frags;
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unsigned int nr_frags;
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u32 def_txd4;
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u32 def_txd4;
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int i, j, unmap_idx, tx_num;
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int i, j, k, frag_size, frag_map_size, offset;
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tx_buf = &priv->tx_buf[idx];
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memset(tx_buf, 0, sizeof(*tx_buf));
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memset(&txd, 0, sizeof(txd));
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memset(&txd, 0, sizeof(txd));
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nr_frags = skb_shinfo(skb)->nr_frags;
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nr_frags = skb_shinfo(skb)->nr_frags;
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tx_num = 1 + (nr_frags >> 1);
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/* init tx descriptor */
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/* init tx descriptor */
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if (priv->soc->tx_dma)
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if (priv->soc->tx_dma)
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@ -546,9 +546,6 @@ static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
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txd.txd4 = TX_DMA_DESP4_DEF;
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txd.txd4 = TX_DMA_DESP4_DEF;
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def_txd4 = txd.txd4;
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def_txd4 = txd.txd4;
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/* use dma_unmap_single to free it */
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txd.txd4 |= priv->soc->tx_udf_bit;
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/* TX Checksum offload */
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/* TX Checksum offload */
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if (skb->ip_summed == CHECKSUM_PARTIAL)
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if (skb->ip_summed == CHECKSUM_PARTIAL)
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txd.txd4 |= TX_DMA_CHKSUM;
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txd.txd4 |= TX_DMA_CHKSUM;
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@ -584,78 +581,92 @@ static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
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txd.txd1 = mapped_addr;
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txd.txd1 = mapped_addr;
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txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
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txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
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tx_buf->flags |= FE_TX_FLAGS_SINGLE0;
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dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
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dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
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/* TX SG offload */
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/* TX SG offload */
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j = idx;
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j = idx;
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k = 0;
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for (i = 0; i < nr_frags; i++) {
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for (i = 0; i < nr_frags; i++) {
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offset = 0;
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frag = &skb_shinfo(skb)->frags[i];
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frag = &skb_shinfo(skb)->frags[i];
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mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0,
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frag_size = skb_frag_size(frag);
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skb_frag_size(frag), DMA_TO_DEVICE);
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while (frag_size > 0) {
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frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
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mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
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frag_map_size, DMA_TO_DEVICE);
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if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
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if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
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goto err_dma;
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goto err_dma;
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if (i & 0x1) {
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if (k & 0x1) {
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j = NEXT_TX_DESP_IDX(j);
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j = NEXT_TX_DESP_IDX(j);
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txd.txd1 = mapped_addr;
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txd.txd1 = mapped_addr;
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txd.txd2 = TX_DMA_PLEN0(frag->size);
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txd.txd2 = TX_DMA_PLEN0(frag_map_size);
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txd.txd4 = def_txd4;
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txd.txd4 = def_txd4;
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tx_buf = &priv->tx_buf[j];
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memset(tx_buf, 0, sizeof(*tx_buf));
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tx_buf->flags |= FE_TX_FLAGS_PAGE0;
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dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
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dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
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} else {
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} else {
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txd.txd3 = mapped_addr;
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txd.txd3 = mapped_addr;
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txd.txd2 |= TX_DMA_PLEN1(frag->size);
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txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
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if (i != (nr_frags -1)) {
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tx_buf->skb = (struct sk_buff *) DMA_DUMMY_DESC;
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tx_buf->flags |= FE_TX_FLAGS_PAGE1;
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dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
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dma_unmap_len_set(tx_buf, dma_len1, frag_map_size);
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if (!((i == (nr_frags -1)) &&
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(frag_map_size == frag_size))) {
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fe_set_txd(&txd, &priv->tx_dma[j]);
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fe_set_txd(&txd, &priv->tx_dma[j]);
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memset(&txd, 0, sizeof(txd));
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memset(&txd, 0, sizeof(txd));
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}
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}
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priv->tx_skb[j] = (struct sk_buff *) DMA_DUMMY_DESC;
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}
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frag_size -= frag_map_size;
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offset += frag_map_size;
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k++;
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}
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}
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}
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}
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/* set last segment */
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/* set last segment */
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if (nr_frags & 0x1)
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if (k & 0x1)
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txd.txd2 |= TX_DMA_LS1;
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txd.txd2 |= TX_DMA_LS1;
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else
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else
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txd.txd2 |= TX_DMA_LS0;
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txd.txd2 |= TX_DMA_LS0;
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fe_set_txd(&txd, &priv->tx_dma[j]);
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fe_set_txd(&txd, &priv->tx_dma[j]);
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/* store skb to cleanup */
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/* store skb to cleanup */
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priv->tx_skb[j] = skb;
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tx_buf->skb = skb;
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netdev_sent_queue(dev, skb->len);
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netdev_sent_queue(dev, skb->len);
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skb_tx_timestamp(skb);
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skb_tx_timestamp(skb);
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wmb();
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j = NEXT_TX_DESP_IDX(j);
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j = NEXT_TX_DESP_IDX(j);
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wmb();
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fe_reg_w32(j, FE_REG_TX_CTX_IDX0);
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fe_reg_w32(j, FE_REG_TX_CTX_IDX0);
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return 0;
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return 0;
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err_dma:
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err_dma:
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/* unmap dma */
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ptxd = &priv->tx_dma[idx];
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txd_unmap_single(&dev->dev, ptxd);
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j = idx;
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unmap_idx = i;
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for (i = 0; i < unmap_idx; i++) {
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if (i & 0x1) {
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j = NEXT_TX_DESP_IDX(j);
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ptxd = &priv->tx_dma[j];
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txd_unmap_page0(&dev->dev, ptxd);
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} else {
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txd_unmap_page1(&dev->dev, ptxd);
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}
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}
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err_out:
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/* reinit descriptors and skb */
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j = idx;
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j = idx;
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for (i = 0; i < tx_num; i++) {
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for (i = 0; i < tx_num; i++) {
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priv->tx_dma[j].txd2 = TX_DMA_DESP2_DEF;
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ptxd = &priv->tx_dma[j];
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priv->tx_skb[j] = NULL;
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tx_buf = &priv->tx_buf[j];
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/* unmap dma */
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fe_txd_unmap(&dev->dev, tx_buf);
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||||||
|
ptxd->txd2 = TX_DMA_DESP2_DEF;
|
||||||
j = NEXT_TX_DESP_IDX(j);
|
j = NEXT_TX_DESP_IDX(j);
|
||||||
}
|
}
|
||||||
wmb();
|
wmb();
|
||||||
|
|
||||||
|
err_out:
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -695,6 +706,24 @@ static inline u32 fe_empty_txd(struct fe_priv *priv, u32 tx_fill_idx)
|
||||||
(NUM_DMA_DESC - 1)));
|
(NUM_DMA_DESC - 1)));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static inline int fe_cal_txd_req(struct sk_buff *skb)
|
||||||
|
{
|
||||||
|
int i, nfrags;
|
||||||
|
struct skb_frag_struct *frag;
|
||||||
|
|
||||||
|
nfrags = 1;
|
||||||
|
if (skb_is_gso(skb)) {
|
||||||
|
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
|
||||||
|
frag = &skb_shinfo(skb)->frags[i];
|
||||||
|
nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
nfrags += skb_shinfo(skb)->nr_frags;
|
||||||
|
}
|
||||||
|
|
||||||
|
return DIV_ROUND_UP(nfrags, 2);
|
||||||
|
}
|
||||||
|
|
||||||
static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
||||||
{
|
{
|
||||||
struct fe_priv *priv = netdev_priv(dev);
|
struct fe_priv *priv = netdev_priv(dev);
|
||||||
|
@ -708,7 +737,7 @@ static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
||||||
return NETDEV_TX_OK;
|
return NETDEV_TX_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
tx_num = 1 + (skb_shinfo(skb)->nr_frags >> 1);
|
tx_num = fe_cal_txd_req(skb);
|
||||||
tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
|
tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
|
||||||
if (unlikely(fe_empty_txd(priv, tx) <= tx_num))
|
if (unlikely(fe_empty_txd(priv, tx) <= tx_num))
|
||||||
{
|
{
|
||||||
|
@ -718,9 +747,7 @@ static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
||||||
return NETDEV_TX_BUSY;
|
return NETDEV_TX_BUSY;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (fe_tx_map_dma(skb, dev, tx) < 0) {
|
if (fe_tx_map_dma(skb, dev, tx, tx_num) < 0) {
|
||||||
kfree_skb(skb);
|
|
||||||
|
|
||||||
stats->tx_dropped++;
|
stats->tx_dropped++;
|
||||||
} else {
|
} else {
|
||||||
stats->tx_packets++;
|
stats->tx_packets++;
|
||||||
|
@ -745,7 +772,7 @@ static inline void fe_rx_vlan(struct sk_buff *skb)
|
||||||
}
|
}
|
||||||
|
|
||||||
static int fe_poll_rx(struct napi_struct *napi, int budget,
|
static int fe_poll_rx(struct napi_struct *napi, int budget,
|
||||||
struct fe_priv *priv)
|
struct fe_priv *priv, u32 rx_intr)
|
||||||
{
|
{
|
||||||
struct net_device *netdev = priv->netdev;
|
struct net_device *netdev = priv->netdev;
|
||||||
struct net_device_stats *stats = &netdev->stats;
|
struct net_device_stats *stats = &netdev->stats;
|
||||||
|
@ -767,6 +794,7 @@ static int fe_poll_rx(struct napi_struct *napi, int budget,
|
||||||
pad = 0;
|
pad = 0;
|
||||||
else
|
else
|
||||||
pad = NET_IP_ALIGN;
|
pad = NET_IP_ALIGN;
|
||||||
|
|
||||||
while (done < budget) {
|
while (done < budget) {
|
||||||
unsigned int pktlen;
|
unsigned int pktlen;
|
||||||
dma_addr_t dma_addr;
|
dma_addr_t dma_addr;
|
||||||
|
@ -818,9 +846,6 @@ static int fe_poll_rx(struct napi_struct *napi, int budget,
|
||||||
stats->rx_packets++;
|
stats->rx_packets++;
|
||||||
stats->rx_bytes += pktlen;
|
stats->rx_bytes += pktlen;
|
||||||
|
|
||||||
if (skb->ip_summed == CHECKSUM_NONE)
|
|
||||||
netif_receive_skb(skb);
|
|
||||||
else
|
|
||||||
napi_gro_receive(napi, skb);
|
napi_gro_receive(napi, skb);
|
||||||
|
|
||||||
priv->rx_data[idx] = new_data;
|
priv->rx_data[idx] = new_data;
|
||||||
|
@ -837,40 +862,39 @@ release_desc:
|
||||||
done++;
|
done++;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (done < budget)
|
||||||
|
fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
|
||||||
|
|
||||||
return done;
|
return done;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int fe_poll_tx(struct fe_priv *priv, int budget)
|
static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr)
|
||||||
{
|
{
|
||||||
struct net_device *netdev = priv->netdev;
|
struct net_device *netdev = priv->netdev;
|
||||||
struct device *dev = &netdev->dev;
|
struct device *dev = &netdev->dev;
|
||||||
unsigned int bytes_compl = 0;
|
unsigned int bytes_compl = 0;
|
||||||
struct sk_buff *skb;
|
struct sk_buff *skb;
|
||||||
struct fe_tx_dma txd;
|
struct fe_tx_buf *tx_buf;
|
||||||
int done = 0, idx;
|
int done = 0;
|
||||||
u32 udf_bit = priv->soc->tx_udf_bit;
|
u32 idx, hwidx;
|
||||||
|
|
||||||
|
hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
|
||||||
idx = priv->tx_free_idx;
|
idx = priv->tx_free_idx;
|
||||||
while (done < budget) {
|
|
||||||
fe_get_txd(&txd, &priv->tx_dma[idx]);
|
|
||||||
skb = priv->tx_skb[idx];
|
|
||||||
|
|
||||||
if (!(txd.txd2 & TX_DMA_DONE) || !skb)
|
txpoll_again:
|
||||||
|
while ((idx != hwidx) && budget) {
|
||||||
|
tx_buf = &priv->tx_buf[idx];
|
||||||
|
skb = tx_buf->skb;
|
||||||
|
|
||||||
|
if (!skb)
|
||||||
break;
|
break;
|
||||||
|
|
||||||
txd_unmap_page1(dev, &txd);
|
|
||||||
|
|
||||||
if (txd.txd4 & udf_bit)
|
|
||||||
txd_unmap_single(dev, &txd);
|
|
||||||
else
|
|
||||||
txd_unmap_page0(dev, &txd);
|
|
||||||
|
|
||||||
if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
|
if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
|
||||||
bytes_compl += skb->len;
|
bytes_compl += skb->len;
|
||||||
dev_kfree_skb_any(skb);
|
|
||||||
done++;
|
done++;
|
||||||
|
budget--;
|
||||||
}
|
}
|
||||||
priv->tx_skb[idx] = NULL;
|
fe_txd_unmap(dev, tx_buf);
|
||||||
idx = NEXT_TX_DESP_IDX(idx);
|
idx = NEXT_TX_DESP_IDX(idx);
|
||||||
}
|
}
|
||||||
priv->tx_free_idx = idx;
|
priv->tx_free_idx = idx;
|
||||||
|
@ -878,6 +902,13 @@ static int fe_poll_tx(struct fe_priv *priv, int budget)
|
||||||
if (!done)
|
if (!done)
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
|
if (done < budget) {
|
||||||
|
hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
|
||||||
|
if (idx != hwidx)
|
||||||
|
goto txpoll_again;
|
||||||
|
fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
|
||||||
|
}
|
||||||
|
|
||||||
netdev_completed_queue(netdev, done, bytes_compl);
|
netdev_completed_queue(netdev, done, bytes_compl);
|
||||||
if (unlikely(netif_queue_stopped(netdev) &&
|
if (unlikely(netif_queue_stopped(netdev) &&
|
||||||
netif_carrier_ok(netdev))) {
|
netif_carrier_ok(netdev))) {
|
||||||
|
@ -900,21 +931,11 @@ static int fe_poll(struct napi_struct *napi, int budget)
|
||||||
rx_intr = priv->soc->rx_int;
|
rx_intr = priv->soc->rx_int;
|
||||||
tx_done = rx_done = 0;
|
tx_done = rx_done = 0;
|
||||||
|
|
||||||
poll_again:
|
if (status & tx_intr)
|
||||||
if (status & tx_intr) {
|
tx_done = fe_poll_tx(priv, budget, tx_intr);
|
||||||
tx_done += fe_poll_tx(priv, budget - tx_done);
|
|
||||||
if (tx_done < budget) {
|
|
||||||
fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
|
|
||||||
}
|
|
||||||
status = fe_reg_r32(FE_REG_FE_INT_STATUS);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (status & rx_intr) {
|
if (status & rx_intr)
|
||||||
rx_done += fe_poll_rx(napi, budget - rx_done, priv);
|
rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
|
||||||
if (rx_done < budget) {
|
|
||||||
fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (unlikely(hwstat && (status & FE_CNT_GDM_AF))) {
|
if (unlikely(hwstat && (status & FE_CNT_GDM_AF))) {
|
||||||
if (spin_trylock(&hwstat->stats_lock)) {
|
if (spin_trylock(&hwstat->stats_lock)) {
|
||||||
|
@ -933,13 +954,14 @@ poll_again:
|
||||||
|
|
||||||
if ((tx_done < budget) && (rx_done < budget)) {
|
if ((tx_done < budget) && (rx_done < budget)) {
|
||||||
status = fe_reg_r32(FE_REG_FE_INT_STATUS);
|
status = fe_reg_r32(FE_REG_FE_INT_STATUS);
|
||||||
if (status & (tx_intr | rx_intr )) {
|
if (status & (tx_intr | rx_intr ))
|
||||||
goto poll_again;
|
goto poll_again;
|
||||||
}
|
|
||||||
napi_complete(napi);
|
napi_complete(napi);
|
||||||
fe_int_enable(tx_intr | rx_intr);
|
fe_int_enable(tx_intr | rx_intr);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
poll_again:
|
||||||
return rx_done;
|
return rx_done;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -984,8 +1006,10 @@ static irqreturn_t fe_handle_irq(int irq, void *dev)
|
||||||
|
|
||||||
int_mask = (priv->soc->rx_int | priv->soc->tx_int);
|
int_mask = (priv->soc->rx_int | priv->soc->tx_int);
|
||||||
if (likely(status & int_mask)) {
|
if (likely(status & int_mask)) {
|
||||||
|
if (likely(napi_schedule_prep(&priv->rx_napi))) {
|
||||||
fe_int_disable(int_mask);
|
fe_int_disable(int_mask);
|
||||||
napi_schedule(&priv->rx_napi);
|
__napi_schedule(&priv->rx_napi);
|
||||||
|
}
|
||||||
} else {
|
} else {
|
||||||
fe_reg_w32(status, FE_REG_FE_INT_STATUS);
|
fe_reg_w32(status, FE_REG_FE_INT_STATUS);
|
||||||
}
|
}
|
||||||
|
@ -1086,6 +1110,9 @@ static int fe_hw_init(struct net_device *dev)
|
||||||
else
|
else
|
||||||
fe_hw_set_macaddr(priv, dev->dev_addr);
|
fe_hw_set_macaddr(priv, dev->dev_addr);
|
||||||
|
|
||||||
|
/* disable delay interrupt */
|
||||||
|
fe_reg_w32(0, FE_REG_DLY_INT_CFG);
|
||||||
|
|
||||||
fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
|
fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
|
||||||
|
|
||||||
/* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
|
/* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
|
||||||
|
@ -1373,7 +1400,7 @@ static int fe_probe(struct platform_device *pdev)
|
||||||
struct net_device *netdev;
|
struct net_device *netdev;
|
||||||
struct fe_priv *priv;
|
struct fe_priv *priv;
|
||||||
struct clk *sysclk;
|
struct clk *sysclk;
|
||||||
int err;
|
int err, napi_weight;
|
||||||
|
|
||||||
device_reset(&pdev->dev);
|
device_reset(&pdev->dev);
|
||||||
|
|
||||||
|
@ -1449,7 +1476,10 @@ static int fe_probe(struct platform_device *pdev)
|
||||||
}
|
}
|
||||||
INIT_WORK(&priv->pending_work, fe_pending_work);
|
INIT_WORK(&priv->pending_work, fe_pending_work);
|
||||||
|
|
||||||
netif_napi_add(netdev, &priv->rx_napi, fe_poll, 32);
|
napi_weight = 32;
|
||||||
|
if (priv->flags & FE_FLAG_NAPI_WEIGHT)
|
||||||
|
napi_weight = 64;
|
||||||
|
netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
|
||||||
fe_set_ethtool_ops(netdev);
|
fe_set_ethtool_ops(netdev);
|
||||||
|
|
||||||
err = register_netdev(netdev);
|
err = register_netdev(netdev);
|
||||||
|
|
|
@ -51,7 +51,7 @@ enum fe_work_flag {
|
||||||
FE_FLAG_MAX
|
FE_FLAG_MAX
|
||||||
};
|
};
|
||||||
|
|
||||||
#define FE_DRV_VERSION "0.1.1"
|
#define FE_DRV_VERSION "0.1.2"
|
||||||
|
|
||||||
/* power of 2 to let NEXT_TX_DESP_IDX work */
|
/* power of 2 to let NEXT_TX_DESP_IDX work */
|
||||||
#ifdef CONFIG_SOC_MT7621
|
#ifdef CONFIG_SOC_MT7621
|
||||||
|
@ -322,11 +322,12 @@ struct fe_rx_dma {
|
||||||
unsigned int rxd4;
|
unsigned int rxd4;
|
||||||
} __packed __aligned(4);
|
} __packed __aligned(4);
|
||||||
|
|
||||||
#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
|
#define TX_DMA_BUF_LEN 0x3fff
|
||||||
#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
|
#define TX_DMA_PLEN0_MASK (TX_DMA_BUF_LEN << 16)
|
||||||
#define TX_DMA_PLEN1(_x) ((_x) & 0x3fff)
|
#define TX_DMA_PLEN0(_x) (((_x) & TX_DMA_BUF_LEN) << 16)
|
||||||
#define TX_DMA_GET_PLEN0(_x) (((_x) >> 16 ) & 0x3fff)
|
#define TX_DMA_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
|
||||||
#define TX_DMA_GET_PLEN1(_x) ((_x) & 0x3fff)
|
#define TX_DMA_GET_PLEN0(_x) (((_x) >> 16 ) & TX_DMA_BUF_LEN)
|
||||||
|
#define TX_DMA_GET_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
|
||||||
#define TX_DMA_LS1 BIT(14)
|
#define TX_DMA_LS1 BIT(14)
|
||||||
#define TX_DMA_LS0 BIT(30)
|
#define TX_DMA_LS0 BIT(30)
|
||||||
#define TX_DMA_DONE BIT(31)
|
#define TX_DMA_DONE BIT(31)
|
||||||
|
@ -401,7 +402,6 @@ struct fe_soc_data
|
||||||
u32 rx_int;
|
u32 rx_int;
|
||||||
u32 tx_int;
|
u32 tx_int;
|
||||||
u32 checksum_bit;
|
u32 checksum_bit;
|
||||||
u32 tx_udf_bit;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#define FE_FLAG_PADDING_64B BIT(0)
|
#define FE_FLAG_PADDING_64B BIT(0)
|
||||||
|
@ -410,6 +410,7 @@ struct fe_soc_data
|
||||||
#define FE_FLAG_RX_2B_OFFSET BIT(3)
|
#define FE_FLAG_RX_2B_OFFSET BIT(3)
|
||||||
#define FE_FLAG_RX_SG_DMA BIT(4)
|
#define FE_FLAG_RX_SG_DMA BIT(4)
|
||||||
#define FE_FLAG_RX_VLAN_CTAG BIT(5)
|
#define FE_FLAG_RX_VLAN_CTAG BIT(5)
|
||||||
|
#define FE_FLAG_NAPI_WEIGHT BIT(6)
|
||||||
|
|
||||||
#define FE_STAT_REG_DECLARE \
|
#define FE_STAT_REG_DECLARE \
|
||||||
_FE(tx_bytes) \
|
_FE(tx_bytes) \
|
||||||
|
@ -434,6 +435,22 @@ FE_STAT_REG_DECLARE
|
||||||
#undef _FE
|
#undef _FE
|
||||||
};
|
};
|
||||||
|
|
||||||
|
enum fe_tx_flags {
|
||||||
|
FE_TX_FLAGS_SINGLE0 = 0x01,
|
||||||
|
FE_TX_FLAGS_PAGE0 = 0x02,
|
||||||
|
FE_TX_FLAGS_PAGE1 = 0x04,
|
||||||
|
};
|
||||||
|
|
||||||
|
struct fe_tx_buf
|
||||||
|
{
|
||||||
|
struct sk_buff *skb;
|
||||||
|
u32 flags;
|
||||||
|
DEFINE_DMA_UNMAP_ADDR(dma_addr0);
|
||||||
|
DEFINE_DMA_UNMAP_LEN(dma_len0);
|
||||||
|
DEFINE_DMA_UNMAP_ADDR(dma_addr1);
|
||||||
|
DEFINE_DMA_UNMAP_LEN(dma_len1);
|
||||||
|
};
|
||||||
|
|
||||||
struct fe_priv
|
struct fe_priv
|
||||||
{
|
{
|
||||||
spinlock_t page_lock;
|
spinlock_t page_lock;
|
||||||
|
@ -454,7 +471,7 @@ struct fe_priv
|
||||||
struct napi_struct rx_napi;
|
struct napi_struct rx_napi;
|
||||||
|
|
||||||
struct fe_tx_dma *tx_dma;
|
struct fe_tx_dma *tx_dma;
|
||||||
struct sk_buff **tx_skb;
|
struct fe_tx_buf *tx_buf;
|
||||||
dma_addr_t tx_phys;
|
dma_addr_t tx_phys;
|
||||||
unsigned int tx_free_idx;
|
unsigned int tx_free_idx;
|
||||||
|
|
||||||
|
|
|
@ -161,7 +161,7 @@ static int mt7621_fwd_config(struct fe_priv *priv)
|
||||||
|
|
||||||
fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff, MT7620A_GDMA1_FWD_CFG);
|
fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff, MT7620A_GDMA1_FWD_CFG);
|
||||||
|
|
||||||
mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
|
/* mt7621 don't have txcsum config */
|
||||||
mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
|
mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
|
||||||
mt7621_rxvlan_config((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
|
mt7621_rxvlan_config((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
|
||||||
(priv->flags & FE_FLAG_RX_VLAN_CTAG));
|
(priv->flags & FE_FLAG_RX_VLAN_CTAG));
|
||||||
|
@ -171,7 +171,6 @@ static int mt7621_fwd_config(struct fe_priv *priv)
|
||||||
|
|
||||||
static void mt7620_tx_dma(struct fe_tx_dma *txd)
|
static void mt7620_tx_dma(struct fe_tx_dma *txd)
|
||||||
{
|
{
|
||||||
txd->txd4 = 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void mt7621_tx_dma(struct fe_tx_dma *txd)
|
static void mt7621_tx_dma(struct fe_tx_dma *txd)
|
||||||
|
@ -189,7 +188,7 @@ static void mt7620_init_data(struct fe_soc_data *data,
|
||||||
|
|
||||||
netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
|
netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
|
||||||
NETIF_F_HW_VLAN_CTAG_TX;
|
NETIF_F_HW_VLAN_CTAG_TX;
|
||||||
if (mt7620_get_eco() >= 5 || IS_ENABLED(CONFIG_SOC_MT7621))
|
if (mt7620_get_eco() >= 5)
|
||||||
netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
|
netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
|
||||||
NETIF_F_IPV6_CSUM;
|
NETIF_F_IPV6_CSUM;
|
||||||
}
|
}
|
||||||
|
@ -200,9 +199,11 @@ static void mt7621_init_data(struct fe_soc_data *data,
|
||||||
struct fe_priv *priv = netdev_priv(netdev);
|
struct fe_priv *priv = netdev_priv(netdev);
|
||||||
|
|
||||||
priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
|
priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
|
||||||
FE_FLAG_RX_SG_DMA;
|
FE_FLAG_RX_SG_DMA | FE_FLAG_NAPI_WEIGHT;
|
||||||
|
|
||||||
netdev->hw_features = NETIF_F_HW_VLAN_CTAG_TX;
|
netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
|
||||||
|
NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_SG | NETIF_F_TSO |
|
||||||
|
NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
|
static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
|
||||||
|
@ -231,7 +232,6 @@ static struct fe_soc_data mt7620_data = {
|
||||||
.rx_int = RT5350_RX_DONE_INT,
|
.rx_int = RT5350_RX_DONE_INT,
|
||||||
.tx_int = RT5350_TX_DONE_INT,
|
.tx_int = RT5350_TX_DONE_INT,
|
||||||
.checksum_bit = MT7620_L4_VALID,
|
.checksum_bit = MT7620_L4_VALID,
|
||||||
.tx_udf_bit = MT7620_TX_DMA_UDF,
|
|
||||||
.has_carrier = mt7620a_has_carrier,
|
.has_carrier = mt7620a_has_carrier,
|
||||||
.mdio_read = mt7620_mdio_read,
|
.mdio_read = mt7620_mdio_read,
|
||||||
.mdio_write = mt7620_mdio_write,
|
.mdio_write = mt7620_mdio_write,
|
||||||
|
@ -252,7 +252,6 @@ static struct fe_soc_data mt7621_data = {
|
||||||
.rx_int = RT5350_RX_DONE_INT,
|
.rx_int = RT5350_RX_DONE_INT,
|
||||||
.tx_int = RT5350_TX_DONE_INT,
|
.tx_int = RT5350_TX_DONE_INT,
|
||||||
.checksum_bit = MT7621_L4_VALID,
|
.checksum_bit = MT7621_L4_VALID,
|
||||||
.tx_udf_bit = MT7621_TX_DMA_UDF,
|
|
||||||
.has_carrier = mt7620a_has_carrier,
|
.has_carrier = mt7620a_has_carrier,
|
||||||
.mdio_read = mt7620_mdio_read,
|
.mdio_read = mt7620_mdio_read,
|
||||||
.mdio_write = mt7620_mdio_write,
|
.mdio_write = mt7620_mdio_write,
|
||||||
|
|
|
@ -63,7 +63,6 @@ struct fe_soc_data rt2880_data = {
|
||||||
.fwd_config = rt2880_fwd_config,
|
.fwd_config = rt2880_fwd_config,
|
||||||
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
|
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
|
||||||
.checksum_bit = RX_DMA_L4VALID,
|
.checksum_bit = RX_DMA_L4VALID,
|
||||||
.tx_udf_bit = TX_DMA_UDF,
|
|
||||||
.rx_int = FE_RX_DONE_INT,
|
.rx_int = FE_RX_DONE_INT,
|
||||||
.tx_int = FE_TX_DONE_INT,
|
.tx_int = FE_TX_DONE_INT,
|
||||||
.mdio_read = rt2880_mdio_read,
|
.mdio_read = rt2880_mdio_read,
|
||||||
|
|
|
@ -131,7 +131,6 @@ static struct fe_soc_data rt3050_data = {
|
||||||
.fwd_config = rt3050_fwd_config,
|
.fwd_config = rt3050_fwd_config,
|
||||||
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
|
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
|
||||||
.checksum_bit = RX_DMA_L4VALID,
|
.checksum_bit = RX_DMA_L4VALID,
|
||||||
.tx_udf_bit = TX_DMA_UDF,
|
|
||||||
.rx_int = FE_RX_DONE_INT,
|
.rx_int = FE_RX_DONE_INT,
|
||||||
.tx_int = FE_TX_DONE_INT,
|
.tx_int = FE_TX_DONE_INT,
|
||||||
};
|
};
|
||||||
|
@ -146,7 +145,6 @@ static struct fe_soc_data rt5350_data = {
|
||||||
.tx_dma = rt5350_tx_dma,
|
.tx_dma = rt5350_tx_dma,
|
||||||
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
|
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
|
||||||
.checksum_bit = RX_DMA_L4VALID,
|
.checksum_bit = RX_DMA_L4VALID,
|
||||||
.tx_udf_bit = TX_DMA_UDF,
|
|
||||||
.rx_int = RT5350_RX_DONE_INT,
|
.rx_int = RT5350_RX_DONE_INT,
|
||||||
.tx_int = RT5350_TX_DONE_INT,
|
.tx_int = RT5350_TX_DONE_INT,
|
||||||
};
|
};
|
||||||
|
|
|
@ -64,7 +64,6 @@ static struct fe_soc_data rt3883_data = {
|
||||||
.rx_int = FE_RX_DONE_INT,
|
.rx_int = FE_RX_DONE_INT,
|
||||||
.tx_int = FE_TX_DONE_INT,
|
.tx_int = FE_TX_DONE_INT,
|
||||||
.checksum_bit = RX_DMA_L4VALID,
|
.checksum_bit = RX_DMA_L4VALID,
|
||||||
.tx_udf_bit = TX_DMA_UDF,
|
|
||||||
.mdio_read = rt2880_mdio_read,
|
.mdio_read = rt2880_mdio_read,
|
||||||
.mdio_write = rt2880_mdio_write,
|
.mdio_write = rt2880_mdio_write,
|
||||||
.mdio_adjust_link = rt2880_mdio_link_adjust,
|
.mdio_adjust_link = rt2880_mdio_link_adjust,
|
||||||
|
|
Loading…
Reference in a new issue