imx6: add missing patches from 3.14
Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 45378
This commit is contained in:
Luka Perkov
parent
e8126cbfbd
commit
bb828e30b0
3 changed files with 678 additions and 0 deletions
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@ -0,0 +1,260 @@
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From 16df7dc5901c1cb2a40f6adbd0d9423768ed8210 Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Thu, 15 May 2014 00:29:18 -0700
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Subject: [PATCH] net: igb: add phy read/write functions that accept phy addr
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Add igb_write_reg_gs40g/igb_read_reg_gs40g that can be passed a phy address.
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The existing igb_write_phy_reg_gs40g/igb_read_phy_reg_gs40g become wrappers
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to this function.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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drivers/net/ethernet/intel/igb/e1000_82575.c | 4 +-
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drivers/net/ethernet/intel/igb/e1000_phy.c | 74 +++++++++++++++++++---------
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drivers/net/ethernet/intel/igb/e1000_phy.h | 6 ++-
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3 files changed, 58 insertions(+), 26 deletions(-)
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--- a/drivers/net/ethernet/intel/igb/e1000_82575.c
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+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
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@@ -2129,7 +2129,7 @@ static s32 igb_read_phy_reg_82580(struct
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if (ret_val)
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goto out;
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- ret_val = igb_read_phy_reg_mdic(hw, offset, data);
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+ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, offset, data);
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hw->phy.ops.release(hw);
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@@ -2154,7 +2154,7 @@ static s32 igb_write_phy_reg_82580(struc
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if (ret_val)
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goto out;
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- ret_val = igb_write_phy_reg_mdic(hw, offset, data);
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+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, offset, data);
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hw->phy.ops.release(hw);
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--- a/drivers/net/ethernet/intel/igb/e1000_phy.c
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+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c
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@@ -132,9 +132,8 @@ out:
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* Reads the MDI control regsiter in the PHY at offset and stores the
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* information read to data.
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**/
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-s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
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+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
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{
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- struct e1000_phy_info *phy = &hw->phy;
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u32 i, mdicnfg, mdic = 0;
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s32 ret_val = 0;
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@@ -153,14 +152,14 @@ s32 igb_read_phy_reg_mdic(struct e1000_h
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case e1000_i211:
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mdicnfg = rd32(E1000_MDICNFG);
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mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
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- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
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+ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
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wr32(E1000_MDICNFG, mdicnfg);
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mdic = ((offset << E1000_MDIC_REG_SHIFT) |
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(E1000_MDIC_OP_READ));
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break;
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default:
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mdic = ((offset << E1000_MDIC_REG_SHIFT) |
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- (phy->addr << E1000_MDIC_PHY_SHIFT) |
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+ (addr << E1000_MDIC_PHY_SHIFT) |
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(E1000_MDIC_OP_READ));
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break;
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}
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@@ -214,9 +213,8 @@ out:
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*
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* Writes data to MDI control register in the PHY at offset.
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**/
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-s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
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+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
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{
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- struct e1000_phy_info *phy = &hw->phy;
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u32 i, mdicnfg, mdic = 0;
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s32 ret_val = 0;
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@@ -235,7 +233,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
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case e1000_i211:
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mdicnfg = rd32(E1000_MDICNFG);
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mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
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- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);
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+ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
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wr32(E1000_MDICNFG, mdicnfg);
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mdic = (((u32)data) |
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(offset << E1000_MDIC_REG_SHIFT) |
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@@ -244,7 +242,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_
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default:
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mdic = (((u32)data) |
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(offset << E1000_MDIC_REG_SHIFT) |
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- (phy->addr << E1000_MDIC_PHY_SHIFT) |
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+ (addr << E1000_MDIC_PHY_SHIFT) |
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(E1000_MDIC_OP_WRITE));
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break;
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}
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@@ -464,7 +462,7 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
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goto out;
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if (offset > MAX_PHY_MULTI_PAGE_REG) {
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- ret_val = igb_write_phy_reg_mdic(hw,
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+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
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IGP01E1000_PHY_PAGE_SELECT,
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(u16)offset);
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if (ret_val) {
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@@ -473,8 +471,8 @@ s32 igb_read_phy_reg_igp(struct e1000_hw
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}
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}
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- ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
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- data);
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+ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr,
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+ MAX_PHY_REG_ADDRESS & offset, data);
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hw->phy.ops.release(hw);
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@@ -503,7 +501,7 @@ s32 igb_write_phy_reg_igp(struct e1000_h
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goto out;
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if (offset > MAX_PHY_MULTI_PAGE_REG) {
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- ret_val = igb_write_phy_reg_mdic(hw,
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+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
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IGP01E1000_PHY_PAGE_SELECT,
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(u16)offset);
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if (ret_val) {
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@@ -512,8 +510,8 @@ s32 igb_write_phy_reg_igp(struct e1000_h
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}
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}
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- ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
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- data);
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+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
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+ MAX_PHY_REG_ADDRESS & offset, data);
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hw->phy.ops.release(hw);
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@@ -2464,8 +2462,9 @@ out:
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}
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/**
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- * igb_write_phy_reg_gs40g - Write GS40G PHY register
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+ * igb_write_reg_gs40g - Write GS40G PHY register
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* @hw: pointer to the HW structure
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+ * @addr: phy address to write to
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* @offset: lower half is register offset to write to
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* upper half is page to use.
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* @data: data to write at register offset
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@@ -2473,7 +2472,7 @@ out:
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* Acquires semaphore, if necessary, then writes the data to PHY register
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* at the offset. Release any acquired semaphores before exiting.
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**/
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-s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
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+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
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{
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s32 ret_val;
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u16 page = offset >> GS40G_PAGE_SHIFT;
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@@ -2483,10 +2482,10 @@ s32 igb_write_phy_reg_gs40g(struct e1000
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if (ret_val)
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return ret_val;
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- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
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+ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
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if (ret_val)
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goto release;
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- ret_val = igb_write_phy_reg_mdic(hw, offset, data);
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+ ret_val = igb_write_phy_reg_mdic(hw, addr, offset, data);
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release:
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hw->phy.ops.release(hw);
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@@ -2494,8 +2493,24 @@ release:
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}
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/**
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- * igb_read_phy_reg_gs40g - Read GS40G PHY register
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+ * igb_write_phy_reg_gs40g - Write GS40G PHY register
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+ * @hw: pointer to the HW structure
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+ * @offset: lower half is register offset to write to
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+ * upper half is page to use.
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+ * @data: data to write at register offset
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+ *
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+ * Acquires semaphore, if necessary, then writes the data to PHY register
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+ * at the offset. Release any acquired semaphores before exiting.
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+ **/
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+s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
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+{
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+ return igb_write_reg_gs40g(hw, hw->phy.addr, offset, data);
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+}
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+
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+/**
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+ * igb_read_reg_gs40g - Read GS40G PHY register
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* @hw: pointer to the HW structure
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+ * @addr: phy address to read from
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* @offset: lower half is register offset to read to
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* upper half is page to use.
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* @data: data to read at register offset
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@@ -2503,7 +2518,7 @@ release:
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* Acquires semaphore, if necessary, then reads the data in the PHY register
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* at the offset. Release any acquired semaphores before exiting.
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**/
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-s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
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+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
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{
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s32 ret_val;
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u16 page = offset >> GS40G_PAGE_SHIFT;
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@@ -2513,10 +2528,10 @@ s32 igb_read_phy_reg_gs40g(struct e1000_
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if (ret_val)
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return ret_val;
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- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
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+ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
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if (ret_val)
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goto release;
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- ret_val = igb_read_phy_reg_mdic(hw, offset, data);
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+ ret_val = igb_read_phy_reg_mdic(hw, addr, offset, data);
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release:
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hw->phy.ops.release(hw);
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@@ -2524,6 +2539,21 @@ release:
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}
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/**
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+ * igb_read_phy_reg_gs40g - Read GS40G PHY register
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+ * @hw: pointer to the HW structure
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+ * @offset: lower half is register offset to read to
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+ * upper half is page to use.
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+ * @data: data to read at register offset
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+ *
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+ * Acquires semaphore, if necessary, then reads the data in the PHY register
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+ * at the offset. Release any acquired semaphores before exiting.
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+ **/
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+s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
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+{
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+ return igb_read_reg_gs40g(hw, hw->phy.addr, offset, data);
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+}
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+
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+/**
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* igb_set_master_slave_mode - Setup PHY for Master/slave mode
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* @hw: pointer to the HW structure
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*
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--- a/drivers/net/ethernet/intel/igb/e1000_phy.h
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+++ b/drivers/net/ethernet/intel/igb/e1000_phy.h
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@@ -61,8 +61,8 @@ s32 igb_phy_has_link(struct e1000_hw *h
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void igb_power_up_phy_copper(struct e1000_hw *hw);
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void igb_power_down_phy_copper(struct e1000_hw *hw);
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s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
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-s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
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-s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
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+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
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+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
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s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
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s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
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@@ -72,6 +72,8 @@ s32 igb_phy_force_speed_duplex_82580(st
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s32 igb_get_cable_length_82580(struct e1000_hw *hw);
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s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
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+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
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+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
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s32 igb_check_polarity_m88(struct e1000_hw *hw);
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/* IGP01E1000 Specific Registers */
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@ -0,0 +1,308 @@
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From 03855caf93f7332a3f320228ba1a0e7baae8a749 Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Thu, 15 May 2014 12:36:23 -0700
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Subject: [PATCH] net: igb: register mii_bus for SerDes w/ external phy
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If an i210 is configured for 1000BASE-BX link_mode and has an external phy
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specified, then register an mii bus using the external phy address as
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a mask.
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An i210 hooked to an external standard phy will be configured with a link_mo
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of SGMII in which case phy ops will be configured and used internall in the
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igb driver for link status. However, in certain cases one might be using a
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backplane SerDes connection to something that talks on the mdio bus but is
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not a standard phy, such as a switch. In this case by registering an mdio
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bus a phy driver can manage the device.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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drivers/net/ethernet/intel/igb/e1000_82575.c | 15 +++
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drivers/net/ethernet/intel/igb/e1000_hw.h | 7 ++
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drivers/net/ethernet/intel/igb/igb_main.c | 168 ++++++++++++++++++++++++++-
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3 files changed, 185 insertions(+), 5 deletions(-)
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--- a/drivers/net/ethernet/intel/igb/e1000_82575.c
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+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
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@@ -598,13 +598,25 @@ static s32 igb_get_invariants_82575(stru
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switch (link_mode) {
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case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
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hw->phy.media_type = e1000_media_type_internal_serdes;
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+ if (igb_sgmii_uses_mdio_82575(hw)) {
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+ u32 mdicnfg = rd32(E1000_MDICNFG);
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+ mdicnfg &= E1000_MDICNFG_PHY_MASK;
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+ hw->phy.addr = mdicnfg >> E1000_MDICNFG_PHY_SHIFT;
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+ hw_dbg("1000BASE_KX w/ external MDIO device at 0x%x\n",
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+ hw->phy.addr);
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+ } else {
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+ hw_dbg("1000BASE_KX");
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+ }
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break;
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case E1000_CTRL_EXT_LINK_MODE_SGMII:
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/* Get phy control interface type set (MDIO vs. I2C)*/
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if (igb_sgmii_uses_mdio_82575(hw)) {
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||||||
|
hw->phy.media_type = e1000_media_type_copper;
|
||||||
|
dev_spec->sgmii_active = true;
|
||||||
|
+ hw_dbg("SGMII with external MDIO PHY");
|
||||||
|
break;
|
||||||
|
+ } else {
|
||||||
|
+ hw_dbg("SGMII with external I2C PHY");
|
||||||
|
}
|
||||||
|
/* fall through for I2C based SGMII */
|
||||||
|
case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
|
||||||
|
@@ -621,8 +633,11 @@ static s32 igb_get_invariants_82575(stru
|
||||||
|
hw->phy.media_type = e1000_media_type_copper;
|
||||||
|
dev_spec->sgmii_active = true;
|
||||||
|
}
|
||||||
|
+ hw_dbg("SERDES with external SFP");
|
||||||
|
|
||||||
|
break;
|
||||||
|
+ } else {
|
||||||
|
+ hw_dbg("SERDES");
|
||||||
|
}
|
||||||
|
|
||||||
|
/* do not change link mode for 100BaseFX */
|
||||||
|
--- a/drivers/net/ethernet/intel/igb/e1000_hw.h
|
||||||
|
+++ b/drivers/net/ethernet/intel/igb/e1000_hw.h
|
||||||
|
@@ -27,6 +27,7 @@
|
||||||
|
#include <linux/delay.h>
|
||||||
|
#include <linux/io.h>
|
||||||
|
#include <linux/netdevice.h>
|
||||||
|
+#include <linux/phy.h>
|
||||||
|
|
||||||
|
#include "e1000_regs.h"
|
||||||
|
#include "e1000_defines.h"
|
||||||
|
@@ -543,6 +544,12 @@ struct e1000_hw {
|
||||||
|
struct e1000_mbx_info mbx;
|
||||||
|
struct e1000_host_mng_dhcp_cookie mng_cookie;
|
||||||
|
|
||||||
|
+#ifdef CONFIG_PHYLIB
|
||||||
|
+ /* Phylib and MDIO interface */
|
||||||
|
+ struct mii_bus *mii_bus;
|
||||||
|
+ struct phy_device *phy_dev;
|
||||||
|
+ phy_interface_t phy_interface;
|
||||||
|
+#endif
|
||||||
|
union {
|
||||||
|
struct e1000_dev_spec_82575 _82575;
|
||||||
|
} dev_spec;
|
||||||
|
--- a/drivers/net/ethernet/intel/igb/igb_main.c
|
||||||
|
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
|
||||||
|
@@ -41,6 +41,7 @@
|
||||||
|
#include <linux/if_vlan.h>
|
||||||
|
#include <linux/pci.h>
|
||||||
|
#include <linux/pci-aspm.h>
|
||||||
|
+#include <linux/phy.h>
|
||||||
|
#include <linux/delay.h>
|
||||||
|
#include <linux/interrupt.h>
|
||||||
|
#include <linux/ip.h>
|
||||||
|
@@ -2231,6 +2232,126 @@ static s32 igb_init_i2c(struct igb_adapt
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
+
|
||||||
|
+#ifdef CONFIG_PHYLIB
|
||||||
|
+/*
|
||||||
|
+ * MMIO/PHYdev support
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+static int igb_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
|
||||||
|
+{
|
||||||
|
+ struct e1000_hw *hw = bus->priv;
|
||||||
|
+ u16 out;
|
||||||
|
+ int err;
|
||||||
|
+
|
||||||
|
+ err = igb_read_reg_gs40g(hw, mii_id, regnum, &out);
|
||||||
|
+ if (err)
|
||||||
|
+ return err;
|
||||||
|
+ return out;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int igb_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
|
||||||
|
+ u16 val)
|
||||||
|
+{
|
||||||
|
+ struct e1000_hw *hw = bus->priv;
|
||||||
|
+
|
||||||
|
+ return igb_write_reg_gs40g(hw, mii_id, regnum, val);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int igb_enet_mdio_reset(struct mii_bus *bus)
|
||||||
|
+{
|
||||||
|
+ udelay(300);
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void igb_enet_mii_link(struct net_device *netdev)
|
||||||
|
+{
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+/* Probe the mdio bus for phys and connect them */
|
||||||
|
+static int igb_enet_mii_probe(struct net_device *netdev)
|
||||||
|
+{
|
||||||
|
+ struct igb_adapter *adapter = netdev_priv(netdev);
|
||||||
|
+ struct e1000_hw *hw = &adapter->hw;
|
||||||
|
+ struct phy_device *phy_dev = NULL;
|
||||||
|
+ int phy_id;
|
||||||
|
+
|
||||||
|
+ /* check for attached phy */
|
||||||
|
+ for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
|
||||||
|
+ if (hw->mii_bus->phy_map[phy_id]) {
|
||||||
|
+ phy_dev = hw->mii_bus->phy_map[phy_id];
|
||||||
|
+ break;
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
+ if (!phy_dev) {
|
||||||
|
+ netdev_err(netdev, "no PHY found\n");
|
||||||
|
+ return -ENODEV;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ hw->phy_interface = PHY_INTERFACE_MODE_RGMII;
|
||||||
|
+ phy_dev = phy_connect(netdev, dev_name(&phy_dev->dev),
|
||||||
|
+ igb_enet_mii_link, hw->phy_interface);
|
||||||
|
+ if (IS_ERR(phy_dev)) {
|
||||||
|
+ netdev_err(netdev, "could not attach to PHY\n");
|
||||||
|
+ return PTR_ERR(phy_dev);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ hw->phy_dev = phy_dev;
|
||||||
|
+ netdev_info(netdev, "igb PHY driver [%s] (mii_bus:phy_addr=%s)\n",
|
||||||
|
+ hw->phy_dev->drv->name, dev_name(&hw->phy_dev->dev));
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+/* Create and register mdio bus */
|
||||||
|
+static int igb_enet_mii_init(struct pci_dev *pdev)
|
||||||
|
+{
|
||||||
|
+ struct mii_bus *mii_bus;
|
||||||
|
+ struct net_device *netdev = pci_get_drvdata(pdev);
|
||||||
|
+ struct igb_adapter *adapter = netdev_priv(netdev);
|
||||||
|
+ struct e1000_hw *hw = &adapter->hw;
|
||||||
|
+ int err;
|
||||||
|
+
|
||||||
|
+ mii_bus = mdiobus_alloc();
|
||||||
|
+ if (mii_bus == NULL) {
|
||||||
|
+ err = -ENOMEM;
|
||||||
|
+ goto err_out;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ mii_bus->name = "igb_enet_mii_bus";
|
||||||
|
+ mii_bus->read = igb_enet_mdio_read;
|
||||||
|
+ mii_bus->write = igb_enet_mdio_write;
|
||||||
|
+ mii_bus->reset = igb_enet_mdio_reset;
|
||||||
|
+ snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
|
||||||
|
+ pci_name(pdev), hw->device_id + 1);
|
||||||
|
+ mii_bus->priv = hw;
|
||||||
|
+ mii_bus->parent = &pdev->dev;
|
||||||
|
+ mii_bus->phy_mask = ~(1 << hw->phy.addr);
|
||||||
|
+
|
||||||
|
+ err = mdiobus_register(mii_bus);
|
||||||
|
+ if (err) {
|
||||||
|
+ printk(KERN_ERR "failed to register mii_bus: %d\n", err);
|
||||||
|
+ goto err_out_free_mdiobus;
|
||||||
|
+ }
|
||||||
|
+ hw->mii_bus = mii_bus;
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+
|
||||||
|
+err_out_free_mdiobus:
|
||||||
|
+ mdiobus_free(mii_bus);
|
||||||
|
+err_out:
|
||||||
|
+ return err;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void igb_enet_mii_remove(struct e1000_hw *hw)
|
||||||
|
+{
|
||||||
|
+ if (hw->mii_bus) {
|
||||||
|
+ mdiobus_unregister(hw->mii_bus);
|
||||||
|
+ mdiobus_free(hw->mii_bus);
|
||||||
|
+ }
|
||||||
|
+}
|
||||||
|
+#endif /* CONFIG_PHYLIB */
|
||||||
|
+
|
||||||
|
/**
|
||||||
|
* igb_probe - Device Initialization Routine
|
||||||
|
* @pdev: PCI device information struct
|
||||||
|
@@ -2653,6 +2774,13 @@ static int igb_probe(struct pci_dev *pde
|
||||||
|
}
|
||||||
|
}
|
||||||
|
pm_runtime_put_noidle(&pdev->dev);
|
||||||
|
+
|
||||||
|
+#ifdef CONFIG_PHYLIB
|
||||||
|
+ /* create and register the mdio bus if using ext phy */
|
||||||
|
+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
|
||||||
|
+ igb_enet_mii_init(pdev);
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
err_register:
|
||||||
|
@@ -2796,6 +2924,10 @@ static void igb_remove(struct pci_dev *p
|
||||||
|
struct e1000_hw *hw = &adapter->hw;
|
||||||
|
|
||||||
|
pm_runtime_get_noresume(&pdev->dev);
|
||||||
|
+#ifdef CONFIG_PHYLIB
|
||||||
|
+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
|
||||||
|
+ igb_enet_mii_remove(hw);
|
||||||
|
+#endif
|
||||||
|
#ifdef CONFIG_IGB_HWMON
|
||||||
|
igb_sysfs_exit(adapter);
|
||||||
|
#endif
|
||||||
|
@@ -3101,6 +3233,12 @@ static int __igb_open(struct net_device
|
||||||
|
if (!resuming)
|
||||||
|
pm_runtime_put(&pdev->dev);
|
||||||
|
|
||||||
|
+#ifdef CONFIG_PHYLIB
|
||||||
|
+ /* Probe and connect to PHY if using ext phy */
|
||||||
|
+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
|
||||||
|
+ igb_enet_mii_probe(netdev);
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
/* start the watchdog. */
|
||||||
|
hw->mac.get_link_status = 1;
|
||||||
|
schedule_work(&adapter->watchdog_task);
|
||||||
|
@@ -7097,21 +7235,41 @@ void igb_alloc_rx_buffers(struct igb_rin
|
||||||
|
static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
|
||||||
|
{
|
||||||
|
struct igb_adapter *adapter = netdev_priv(netdev);
|
||||||
|
+ struct e1000_hw *hw = &adapter->hw;
|
||||||
|
struct mii_ioctl_data *data = if_mii(ifr);
|
||||||
|
|
||||||
|
- if (adapter->hw.phy.media_type != e1000_media_type_copper)
|
||||||
|
+ if (adapter->hw.phy.media_type != e1000_media_type_copper &&
|
||||||
|
+ !(rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO))
|
||||||
|
return -EOPNOTSUPP;
|
||||||
|
|
||||||
|
switch (cmd) {
|
||||||
|
case SIOCGMIIPHY:
|
||||||
|
- data->phy_id = adapter->hw.phy.addr;
|
||||||
|
+ data->phy_id = hw->phy.addr;
|
||||||
|
break;
|
||||||
|
case SIOCGMIIREG:
|
||||||
|
- if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
|
||||||
|
- &data->val_out))
|
||||||
|
- return -EIO;
|
||||||
|
+ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
|
||||||
|
+ if (igb_read_reg_gs40g(&adapter->hw, data->phy_id,
|
||||||
|
+ data->reg_num & 0x1F,
|
||||||
|
+ &data->val_out))
|
||||||
|
+ return -EIO;
|
||||||
|
+ } else {
|
||||||
|
+ if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
|
||||||
|
+ &data->val_out))
|
||||||
|
+ return -EIO;
|
||||||
|
+ }
|
||||||
|
break;
|
||||||
|
case SIOCSMIIREG:
|
||||||
|
+ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
|
||||||
|
+ if (igb_write_reg_gs40g(hw, data->phy_id,
|
||||||
|
+ data->reg_num & 0x1F,
|
||||||
|
+ data->val_in))
|
||||||
|
+ return -EIO;
|
||||||
|
+ } else {
|
||||||
|
+ if (igb_write_phy_reg(hw, data->reg_num & 0x1F,
|
||||||
|
+ data->val_in))
|
||||||
|
+ return -EIO;
|
||||||
|
+ }
|
||||||
|
+ break;
|
||||||
|
default:
|
||||||
|
return -EOPNOTSUPP;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,110 @@
|
||||||
|
From 840202d23892baaff74be11ec71c3ffc6ad6298e Mon Sep 17 00:00:00 2001
|
||||||
|
From: Tim Harvey <tharvey@gateworks.com>
|
||||||
|
Date: Tue, 20 Jan 2015 08:46:55 -0800
|
||||||
|
Subject: [PATCH] ARM: dts: imx6 ventana: Add PCI nodes for on-board PCI
|
||||||
|
devices
|
||||||
|
|
||||||
|
If the PCI nodes are defined, drivers can access information from the DT.
|
||||||
|
For example, the sky2 enet driver can obtain the mac address configured
|
||||||
|
from the bootloader (which is applied to the DT node with the ethernet1 alias).
|
||||||
|
|
||||||
|
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
||||||
|
---
|
||||||
|
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 38 +++++++++++++++++++++++++++++++++--
|
||||||
|
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 38 +++++++++++++++++++++++++++++++++--
|
||||||
|
2 files changed, 72 insertions(+), 4 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
|
||||||
|
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
|
||||||
|
@@ -280,8 +280,42 @@
|
||||||
|
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
- eth1: sky2@8 { /* MAC/PHY on bus 8 */
|
||||||
|
- compatible = "marvell,sky2";
|
||||||
|
+ pcie@0,0 {
|
||||||
|
+ /* 00:00.0 0604: 16c3:abcd root host-bridge */
|
||||||
|
+ #address-cells = <3>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+ device_type = "pci";
|
||||||
|
+ reg = <0x0 0 0 0 0>;
|
||||||
|
+
|
||||||
|
+ pcie@0,0 {
|
||||||
|
+ /* 01:00.0 0604: 10b5:8609 PEX switch bridge */
|
||||||
|
+ #address-cells = <3>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+ device_type = "pci";
|
||||||
|
+ reg = <0x0 0 0 0 0>;
|
||||||
|
+
|
||||||
|
+ /*
|
||||||
|
+ * GigE PCI dev node needs to be defined so that enet
|
||||||
|
+ * driver can use it to obtain its boot-loader
|
||||||
|
+ * specified MAC
|
||||||
|
+ */
|
||||||
|
+ pcie@4,0 {
|
||||||
|
+ /* 02:04.0 0604: 10b5:8609: PEX port bridge */
|
||||||
|
+ #address-cells = <3>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+ device_type = "pci";
|
||||||
|
+ reg = <0x2000 0 0 0 0>;
|
||||||
|
+
|
||||||
|
+ eth1: pci@0,0 {
|
||||||
|
+ /* 04:00.0 0200: 11ab:4380: GigE */
|
||||||
|
+ #address-cells = <3>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+ device_type = "pci";
|
||||||
|
+ reg = <0x0 0 0 0 0>;
|
||||||
|
+ compatible = "marvell,sky2";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
|
||||||
|
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
|
||||||
|
@@ -369,8 +369,42 @@
|
||||||
|
reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
- eth1: sky2@8 { /* MAC/PHY on bus 8 */
|
||||||
|
- compatible = "marvell,sky2";
|
||||||
|
+ pcie@0,0 {
|
||||||
|
+ /* 00:00.0 0604: 16c3:abcd root host-bridge */
|
||||||
|
+ #address-cells = <3>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+ device_type = "pci";
|
||||||
|
+ reg = <0x0 0 0 0 0>;
|
||||||
|
+
|
||||||
|
+ pcie@0,0 {
|
||||||
|
+ /* 01:00.0 0604: 10b5:8609 PEX switch bridge */
|
||||||
|
+ #address-cells = <3>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+ device_type = "pci";
|
||||||
|
+ reg = <0x0 0 0 0 0>;
|
||||||
|
+
|
||||||
|
+ /*
|
||||||
|
+ * GigE PCI dev node needs to be defined so that enet
|
||||||
|
+ * driver can use it to obtain its boot-loader
|
||||||
|
+ * specified MAC
|
||||||
|
+ */
|
||||||
|
+ pcie@8,0 {
|
||||||
|
+ /* 02:08.0 0604: 10b5:8609: PEX port bridge */
|
||||||
|
+ #address-cells = <3>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+ device_type = "pci";
|
||||||
|
+ reg = <0x4000 0 0 0 0>;
|
||||||
|
+
|
||||||
|
+ eth1: pci@0,0 {
|
||||||
|
+ /* 08:00.0 0200: 11ab:4380: GigE */
|
||||||
|
+ #address-cells = <3>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+ device_type = "pci";
|
||||||
|
+ reg = <0x0 0 0 0 0>;
|
||||||
|
+ compatible = "marvell,sky2";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
Loading…
Reference in a new issue