ramips: Rename POC registers
Rename POC registers. The current code uses POC1-POC3. The datasheet uses: POC1: Port Control 0 POC1: Port Control 1 POC2: Port Control 2 So the first POC1 is a typo that should have been POC0, rename the registers to POC0-POC2 accordingly. Signed-off-by: Tobias Diedrich <ranma+openwrt@tdiedrich.de> SVN-Revision: 33302
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1 changed files with 31 additions and 31 deletions
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@ -23,9 +23,9 @@
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#define RT305X_ESW_REG_POA 0x80
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#define RT305X_ESW_REG_POA 0x80
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#define RT305X_ESW_REG_FPA 0x84
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#define RT305X_ESW_REG_FPA 0x84
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#define RT305X_ESW_REG_SOCPC 0x8c
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#define RT305X_ESW_REG_SOCPC 0x8c
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#define RT305X_ESW_REG_POC1 0x90
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#define RT305X_ESW_REG_POC0 0x90
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#define RT305X_ESW_REG_POC2 0x94
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#define RT305X_ESW_REG_POC1 0x94
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#define RT305X_ESW_REG_POC3 0x98
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#define RT305X_ESW_REG_POC2 0x98
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#define RT305X_ESW_REG_SGC 0x9c
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#define RT305X_ESW_REG_SGC 0x9c
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#define RT305X_ESW_REG_STRT 0xa0
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#define RT305X_ESW_REG_STRT 0xa0
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#define RT305X_ESW_REG_PCR0 0xc0
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#define RT305X_ESW_REG_PCR0 0xc0
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@ -85,16 +85,16 @@
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#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
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#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
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#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
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#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
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#define RT305X_ESW_POC1_EN_BP_S 0
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#define RT305X_ESW_POC0_EN_BP_S 0
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#define RT305X_ESW_POC1_EN_FC_S 8
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#define RT305X_ESW_POC0_EN_FC_S 8
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#define RT305X_ESW_POC1_DIS_RMC2CPU_S 16
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#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
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#define RT305X_ESW_POC1_DIS_PORT_M 0x7f
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#define RT305X_ESW_POC0_DIS_PORT_M 0x7f
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#define RT305X_ESW_POC1_DIS_PORT_S 23
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#define RT305X_ESW_POC0_DIS_PORT_S 23
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#define RT305X_ESW_POC3_UNTAG_EN_M 0xff
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#define RT305X_ESW_POC2_UNTAG_EN_M 0xff
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#define RT305X_ESW_POC3_UNTAG_EN_S 0
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#define RT305X_ESW_POC2_UNTAG_EN_S 0
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#define RT305X_ESW_POC3_ENAGING_S 8
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#define RT305X_ESW_POC2_ENAGING_S 8
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#define RT305X_ESW_POC3_DIS_UC_PAUSE_S 16
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#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
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#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
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#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
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#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
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#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
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@ -345,15 +345,15 @@ rt305x_esw_hw_init(struct rt305x_esw *esw)
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/* Enable Back Pressure, and Flow Control */
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/* Enable Back Pressure, and Flow Control */
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rt305x_esw_wr(esw,
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rt305x_esw_wr(esw,
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((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_BP_S) |
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((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
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(RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_FC_S)),
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(RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
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RT305X_ESW_REG_POC1);
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RT305X_ESW_REG_POC0);
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/* Enable Aging, and VLAN TAG removal */
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/* Enable Aging, and VLAN TAG removal */
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rt305x_esw_wr(esw,
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rt305x_esw_wr(esw,
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((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC3_ENAGING_S) |
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((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
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(RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC3_UNTAG_EN_S)),
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(RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
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RT305X_ESW_REG_POC3);
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RT305X_ESW_REG_POC2);
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rt305x_esw_wr(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
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rt305x_esw_wr(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
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@ -482,9 +482,9 @@ rt305x_esw_apply_config(struct switch_dev *dev)
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RT305X_ESW_REG_P0LED + 4*i);
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RT305X_ESW_REG_P0LED + 4*i);
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}
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}
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rt305x_esw_rmw(esw, RT305X_ESW_REG_POC1,
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rt305x_esw_rmw(esw, RT305X_ESW_REG_POC0,
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RT305X_ESW_POC1_DIS_PORT_M << RT305X_ESW_POC1_DIS_PORT_S,
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RT305X_ESW_POC0_DIS_PORT_M << RT305X_ESW_POC0_DIS_PORT_S,
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disable << RT305X_ESW_POC1_DIS_PORT_S);
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disable << RT305X_ESW_POC0_DIS_PORT_S);
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rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2,
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rt305x_esw_rmw(esw, RT305X_ESW_REG_SGC2,
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(RT305X_ESW_SGC2_DOUBLE_TAG_M <<
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(RT305X_ESW_SGC2_DOUBLE_TAG_M <<
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RT305X_ESW_SGC2_DOUBLE_TAG_S),
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RT305X_ESW_SGC2_DOUBLE_TAG_S),
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@ -492,9 +492,9 @@ rt305x_esw_apply_config(struct switch_dev *dev)
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rt305x_esw_rmw(esw, RT305X_ESW_REG_PFC1,
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rt305x_esw_rmw(esw, RT305X_ESW_REG_PFC1,
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RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
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RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
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en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
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en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
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rt305x_esw_rmw(esw, RT305X_ESW_REG_POC3,
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rt305x_esw_rmw(esw, RT305X_ESW_REG_POC2,
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RT305X_ESW_POC3_UNTAG_EN_M << RT305X_ESW_POC3_UNTAG_EN_S,
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RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
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untag << RT305X_ESW_POC3_UNTAG_EN_S);
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untag << RT305X_ESW_POC2_UNTAG_EN_S);
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if (!esw->global_vlan_enable) {
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if (!esw->global_vlan_enable) {
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/*
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/*
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@ -624,16 +624,16 @@ rt305x_esw_get_port_bool(struct switch_dev *dev,
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switch (attr->id) {
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switch (attr->id) {
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case RT305X_ESW_ATTR_PORT_DISABLE:
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case RT305X_ESW_ATTR_PORT_DISABLE:
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reg = RT305X_ESW_REG_POC1;
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reg = RT305X_ESW_REG_POC0;
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shift = RT305X_ESW_POC1_DIS_PORT_S;
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shift = RT305X_ESW_POC0_DIS_PORT_S;
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break;
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break;
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case RT305X_ESW_ATTR_PORT_DOUBLETAG:
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case RT305X_ESW_ATTR_PORT_DOUBLETAG:
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reg = RT305X_ESW_REG_SGC2;
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reg = RT305X_ESW_REG_SGC2;
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shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
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shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
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break;
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break;
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case RT305X_ESW_ATTR_PORT_UNTAG:
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case RT305X_ESW_ATTR_PORT_UNTAG:
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reg = RT305X_ESW_REG_POC3;
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reg = RT305X_ESW_REG_POC2;
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shift = RT305X_ESW_POC3_UNTAG_EN_S;
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shift = RT305X_ESW_POC2_UNTAG_EN_S;
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break;
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break;
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case RT305X_ESW_ATTR_PORT_LAN:
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case RT305X_ESW_ATTR_PORT_LAN:
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reg = RT305X_ESW_REG_SGC2;
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reg = RT305X_ESW_REG_SGC2;
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@ -760,7 +760,7 @@ static int
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rt305x_esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
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rt305x_esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
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{
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{
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struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
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struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
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u32 vmsc, poc3;
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u32 vmsc, poc2;
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int vlan_idx = -1;
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int vlan_idx = -1;
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int i;
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int i;
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@ -782,7 +782,7 @@ rt305x_esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
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return -EINVAL;
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return -EINVAL;
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vmsc = rt305x_esw_get_vmsc(esw, vlan_idx);
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vmsc = rt305x_esw_get_vmsc(esw, vlan_idx);
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poc3 = rt305x_esw_rr(esw, RT305X_ESW_REG_POC3);
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poc2 = rt305x_esw_rr(esw, RT305X_ESW_REG_POC2);
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for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
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for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
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struct switch_port *p;
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struct switch_port *p;
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@ -793,7 +793,7 @@ rt305x_esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
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p = &val->value.ports[val->len++];
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p = &val->value.ports[val->len++];
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p->id = i;
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p->id = i;
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if (poc3 & (port_mask << RT305X_ESW_POC3_UNTAG_EN_S))
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if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
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p->flags = 0;
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p->flags = 0;
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else
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else
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p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
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p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
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