ar71xx: update early_printk code
SVN-Revision: 27165
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parent
1277bd7186
commit
b58ede16a5
2 changed files with 111 additions and 43 deletions
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@ -15,72 +15,82 @@
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#include <asm/addrspace.h>
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#include <asm/mach-ar71xx/ar71xx.h>
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#include <asm/mach-ar71xx/ar933x_uart.h>
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static void __iomem *prom_uart_base;
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static void (*_putchar)(unsigned char);
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static void (*_prom_putchar) (unsigned char);
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#define UART_READ(r) \
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__raw_readl(prom_uart_base + 4 * (r))
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static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
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{
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u32 t;
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#define UART_WRITE(r, v) \
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__raw_writel((v), prom_uart_base + 4 * (r))
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do {
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t = __raw_readl(reg);
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if ((t & mask) == val)
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break;
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} while (1);
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}
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static void prom_putchar_ar71xx(unsigned char ch)
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{
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while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0)
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;
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UART_WRITE(UART_TX, ch);
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while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0)
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;
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void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
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prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
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__raw_writel(ch, base + UART_TX * 4);
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prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
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}
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static void prom_putchar_ar933x(unsigned char ch)
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{
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while (((UART_READ(0)) & 0x200) == 0)
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;
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UART_WRITE(0, 0x200 | ch);
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while (((UART_READ(0)) & 0x200) == 0)
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;
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void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE));
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prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
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AR933X_UART_DATA_TX_CSR);
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__raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG);
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prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
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AR933X_UART_DATA_TX_CSR);
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}
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static int prom_putchar_init(void)
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static void prom_putchar_dummy(unsigned char ch)
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{
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if (_putchar)
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return 0;
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/* nothing to do */
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}
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switch(ar71xx_soc) {
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case AR71XX_SOC_AR7130:
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case AR71XX_SOC_AR7141:
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case AR71XX_SOC_AR7161:
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case AR71XX_SOC_AR7240:
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case AR71XX_SOC_AR7241:
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case AR71XX_SOC_AR7242:
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case AR71XX_SOC_AR9130:
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case AR71XX_SOC_AR9132:
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case AR71XX_SOC_AR9341:
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case AR71XX_SOC_AR9342:
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case AR71XX_SOC_AR9344:
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prom_uart_base = (void __iomem *) KSEG1ADDR(AR71XX_UART_BASE);
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_putchar = prom_putchar_ar71xx;
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static void prom_putchar_init(void)
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{
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void __iomem *base;
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u32 id;
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base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE));
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id = __raw_readl(base + AR71XX_RESET_REG_REV_ID);
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id &= REV_ID_MAJOR_MASK;
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switch (id) {
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case REV_ID_MAJOR_AR71XX:
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case REV_ID_MAJOR_AR7240:
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case REV_ID_MAJOR_AR7241:
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case REV_ID_MAJOR_AR7242:
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case REV_ID_MAJOR_AR913X:
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case REV_ID_MAJOR_AR9341:
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case REV_ID_MAJOR_AR9342:
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case REV_ID_MAJOR_AR9344:
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_prom_putchar = prom_putchar_ar71xx;
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break;
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case AR71XX_SOC_AR9330:
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case AR71XX_SOC_AR9331:
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prom_uart_base = (void __iomem *) KSEG1ADDR(AR933X_UART_BASE);
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_putchar = prom_putchar_ar933x;
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case REV_ID_MAJOR_AR9330:
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case REV_ID_MAJOR_AR9331:
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_prom_putchar = prom_putchar_ar933x;
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break;
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default:
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return -ENODEV;
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_prom_putchar = prom_putchar_dummy;
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break;
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}
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return 0;
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}
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void prom_putchar(unsigned char ch)
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{
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if (prom_putchar_init())
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return;
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if (!_prom_putchar)
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prom_putchar_init();
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_putchar(ch);
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_prom_putchar(ch);
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}
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@ -0,0 +1,58 @@
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/*
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* Atheros AR933X UART defines
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*
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* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef __AR933X_UART_H
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#define __AR933X_UART_H
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#define AR933X_UART_DATA_REG 0x00
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#define AR933X_UART_CS_REG 0x04
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#define AR933X_UART_CLOCK_REG 0x08
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#define AR933X_UART_INT_REG 0x0c
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#define AR933X_UART_INT_EN_REG 0x10
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#define AR933X_UART_DATA_TX_RX_MASK 0xff
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#define AR933X_UART_DATA_RX_CSR BIT(8)
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#define AR933X_UART_DATA_TX_CSR BIT(9)
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#define AR933X_UART_CS_PARITY_S 0
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#define AR933X_UART_CS_PARITY_M 0x3
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#define AR933X_UART_CS_PARITY_M 0x3
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#define AR933X_UART_CS_IF_MODE_S 2
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#define AR933X_UART_CS_IF_MODE_M 0x3
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#define AR933X_UART_CS_FLOW_CTRL_S 4
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#define AR933X_UART_CS_FLOW_CTRL_M 0x3
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#define AR933X_UART_CS_DMA_EN BIT(6)
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#define AR933X_UART_CS_TX_READY_ORIDE BIT(7)
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#define AR933X_UART_CS_RX_READY_ORIDE BIT(8)
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#define AR933X_UART_CS_TX_READY BIT(9)
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#define AR933X_UART_CS_RX_BREAK BIT(10)
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#define AR933X_UART_CS_TX_BREAK BIT(11)
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#define AR933X_UART_CS_HOST_INT BIT(12)
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#define AR933X_UART_CS_HOST_INT_EN BIT(13)
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#define AR933X_UART_CS_TX_BUSY BIT(14)
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#define AR933X_UART_CS_RX_BUSY BIT(15)
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#define AR933X_UART_CLOCK_STEP_M 0xffff
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#define AR933X_UART_CLOCK_SCALE_M 0xfff
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#define AR933X_UART_CLCOK_SCALE_S 16
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#define AR933X_UART_INT_RX_VALID BIT(0)
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#define AR933X_UART_INT_TX_READY BIT(1)
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#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2)
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#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3)
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#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4)
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#define AR933X_UART_INT_RX_PARITY_ERR BIT(5)
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#define AR933X_UART_INT_RX_BREAK_ON BIT(6)
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#define AR933X_UART_INT_RX_BREAK_OFF BIT(7)
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#define AR933X_UART_INT_RX_FULL BIT(8)
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#define AR933X_UART_INT_TX_EMPTY BIT(9)
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#define AR933X_UART_INT_ALLINTS 0x3ff
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#endif /* __AR933X_UART_H */
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