ar71xx: allow to register ethernet interfaces for AR934X
SVN-Revision: 28978
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2f9e535e89
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1 changed files with 54 additions and 0 deletions
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@ -298,6 +298,16 @@ static void ar933x_set_pll_ge1(int speed)
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/* TODO */
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/* TODO */
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}
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}
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static void ar934x_set_pll_ge0(int speed)
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{
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/* TODO */
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}
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static void ar934x_set_pll_ge1(int speed)
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{
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/* TODO */
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}
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static void ar71xx_ddr_flush_ge0(void)
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static void ar71xx_ddr_flush_ge0(void)
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{
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{
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ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
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ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
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@ -338,6 +348,16 @@ static void ar933x_ddr_flush_ge1(void)
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ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
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ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
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}
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}
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static void ar934x_ddr_flush_ge0(void)
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{
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ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0);
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}
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static void ar934x_ddr_flush_ge1(void)
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{
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ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1);
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}
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static struct resource ar71xx_eth0_resources[] = {
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static struct resource ar71xx_eth0_resources[] = {
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{
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{
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.name = "mac_base",
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.name = "mac_base",
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@ -424,6 +444,10 @@ struct platform_device ar71xx_eth1_device = {
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#define AR933X_PLL_VAL_100 0x00001099
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#define AR933X_PLL_VAL_100 0x00001099
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#define AR933X_PLL_VAL_10 0x00991099
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#define AR933X_PLL_VAL_10 0x00991099
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#define AR934X_PLL_VAL_1000 0x00110000
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#define AR934X_PLL_VAL_100 0x00001099
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#define AR934X_PLL_VAL_10 0x00991099
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static void __init ar71xx_init_eth_pll_data(unsigned int id)
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static void __init ar71xx_init_eth_pll_data(unsigned int id)
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{
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{
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struct ar71xx_eth_pll_data *pll_data;
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struct ar71xx_eth_pll_data *pll_data;
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@ -476,6 +500,14 @@ static void __init ar71xx_init_eth_pll_data(unsigned int id)
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pll_1000 = AR933X_PLL_VAL_1000;
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pll_1000 = AR933X_PLL_VAL_1000;
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break;
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break;
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case AR71XX_SOC_AR9341:
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case AR71XX_SOC_AR9342:
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case AR71XX_SOC_AR9344:
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pll_10 = AR934X_PLL_VAL_10;
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pll_100 = AR934X_PLL_VAL_100;
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pll_1000 = AR934X_PLL_VAL_1000;
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break;
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default:
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default:
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BUG();
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BUG();
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}
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}
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@ -640,6 +672,28 @@ void __init ar71xx_add_device_eth(unsigned int id)
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pdata->fifo_cfg3 = 0x01f00140;
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pdata->fifo_cfg3 = 0x01f00140;
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break;
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break;
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case AR71XX_SOC_AR9341:
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case AR71XX_SOC_AR9342:
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case AR71XX_SOC_AR9344:
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ar71xx_eth0_data.reset_bit = AR934X_RESET_GE0_MAC |
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AR934X_RESET_GE0_MDIO;
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ar71xx_eth1_data.reset_bit = AR934X_RESET_GE1_MAC |
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AR934X_RESET_GE1_MDIO;
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pdata->ddr_flush = id ? ar934x_ddr_flush_ge1
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: ar934x_ddr_flush_ge0;
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pdata->set_pll = id ? ar934x_set_pll_ge1
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: ar934x_set_pll_ge0;
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pdata->has_gbit = 1;
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pdata->is_ar724x = 1;
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if (!pdata->fifo_cfg1)
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pdata->fifo_cfg1 = 0x0010ffff;
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if (!pdata->fifo_cfg2)
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pdata->fifo_cfg2 = 0x015500aa;
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if (!pdata->fifo_cfg3)
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pdata->fifo_cfg3 = 0x01f00140;
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break;
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default:
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default:
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BUG();
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BUG();
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}
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}
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